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| author |   Yulong Pei <yulong.pei@intel.com> | 2018-11-20 00:51:58 +0800 |
|---|---|---|
| committer |   Tibor Frank <tifrank@cisco.com> | 2018-11-21 11:00:07 +0000 |
| commit | 038eac9472666920a5fbdd8bb55e58bc8044ddc5 (patch) | |
| tree | 7856dee9bb966d8e68e085a1720ec4ff066a84d7 /docs/fdio_csit_dev_plan.txt | |
| parent | 02b24d068e4327870129ef814719080da5dd080d (diff) | |
doc: add 2-node denverton section to physical testbeds
Change-Id: I7e35622f8b6b8e1a76f0e1c8fe17f4c9c40937b4
Signed-off-by: Yulong Pei <yulong.pei@intel.com>
Diffstat (limited to 'docs/fdio_csit_dev_plan.txt')
0 files changed, 0 insertions, 0 deletions