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author | 2020-01-09 15:02:10 +0100 | |
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committer | 2020-01-10 07:50:26 +0000 | |
commit | 80e558550b0f076857618c4451987fb60ced19b9 (patch) | |
tree | 78a2fe2dcd9e59405449e5493f5a16d4803cfa24 /docs/report/vpp_performance_tests/hdrh_packet_latency_graphs/ipsec.rst | |
parent | a08fc340f548a4b223c7c139b4fe59531cf7c694 (diff) |
Report: Add 2n-clx
Change-Id: I34dc11c28d21f0b9fed87d76942fe8b8cdd86c88
Signed-off-by: Tibor Frank <tifrank@cisco.com>
Diffstat (limited to 'docs/report/vpp_performance_tests/hdrh_packet_latency_graphs/ipsec.rst')
-rw-r--r-- | docs/report/vpp_performance_tests/hdrh_packet_latency_graphs/ipsec.rst | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/docs/report/vpp_performance_tests/hdrh_packet_latency_graphs/ipsec.rst b/docs/report/vpp_performance_tests/hdrh_packet_latency_graphs/ipsec.rst index 2a0233a942..279ac66d93 100644 --- a/docs/report/vpp_performance_tests/hdrh_packet_latency_graphs/ipsec.rst +++ b/docs/report/vpp_performance_tests/hdrh_packet_latency_graphs/ipsec.rst @@ -16,7 +16,7 @@ a.k.a. VPP data plane thread(s), and their physical CPU core(s) placement. CSIT source code for the test cases used for plots can be found in -`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/crypto?h=rls1908>`_. +`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/crypto?h=rls2001>`_. .. toctree:: |