diff options
| -rw-r--r-- | docs/report/introduction/test_environment_intro.rst | 18 | ||||
| -rw-r--r-- | docs/report/vpp_performance_tests/csit_release_notes.rst | 29 |
2 files changed, 17 insertions, 30 deletions
diff --git a/docs/report/introduction/test_environment_intro.rst b/docs/report/introduction/test_environment_intro.rst index 4f645713aa..2aa4f44e40 100644 --- a/docs/report/introduction/test_environment_intro.rst +++ b/docs/report/introduction/test_environment_intro.rst @@ -70,17 +70,23 @@ Following is the list of CSIT versions to date: - The main change is TRex data-plane core resource adjustments: `increase from 7 to 8 cores and pinning cores to interfaces <https://gerrit.fd.io/r/c/csit/+/28184>`_ for better TRex performance with symmetric traffic profiles. +- Ver. 6 associated with CSIT rls2101 branch (`HW + <https://git.fd.io/csit/tree/docs/lab?h=rls2101>`_, `Linux + <https://docs.fd.io/csit/rls2101/report/vpp_performance_tests/test_environment.html#sut-settings-linux>`_, + `TRex + <https://docs.fd.io/csit/rls2101/report/vpp_performance_tests/test_environment.html#tg-settings-trex>`_, + `CSIT <https://git.fd.io/csit/tree/?h=rls2101>`_). + + - The main change is TRex version upgrade: + `increase from 2.82 to 2.86 <https://gerrit.fd.io/r/c/csit/+/29980>`_. -To identify performance changes due to VPP code development from -v20.05.0 to v20.09.0, both have been tested in CSIT environment ver. 5 -and compared against each other. All substantial progressions and +To identify performance changes due to VPP code development between previous +and current VPP release version, both have been tested in CSIT environment of +latest version and compared against each other. All substantial progressions and regressions have been marked up with RCA analysis. See :ref:`vpp_throughput_comparisons` and :ref:`vpp_known_issues`. -CSIT environment ver. 5 has been evaluated against the ver. 4 by -benchmarking VPP v20.05.0 in both environment versions. - Physical Testbeds ----------------- diff --git a/docs/report/vpp_performance_tests/csit_release_notes.rst b/docs/report/vpp_performance_tests/csit_release_notes.rst index 16a7db38e6..c279f1091d 100644 --- a/docs/report/vpp_performance_tests/csit_release_notes.rst +++ b/docs/report/vpp_performance_tests/csit_release_notes.rst @@ -9,13 +9,6 @@ Changes in |csit-release| - CSIT test environment is versioned, see :ref:`test_environment_versioning`. - - To identify performance changes due to VPP code changes from - v20.05.0 to v20.09.0, both have been tested in CSIT environment - ver. 5 and compared against each other. All substantial - progressions has been marked up with RCA analysis. See - :ref:`vpp_compare_current_vs_previous_release` and - :ref:`vpp_known_issues`. - - **GENEVE tests**: Added VPP performance tests for GENEVE tunnels. - See :ref:`geneve_methodology` for more details. @@ -46,33 +39,24 @@ Changes in |csit-release| - **IPSec async mode tests**: Added VPP performance tests for async crypto engine. - - **AMD 2n-zn2 testbed**: New physical testbed type installed in - FD.io CSIT, with VPP and DPDK performance data added to CSIT - trending and this report. - - **AMD 2n-tx2 testbed**: New physical testbed type installed in FD.io CSIT, with VPP and DPDK performance data added to CSIT trending and this report. #. TEST FRAMEWORK - - **TRex ASTF**: Added capability to run TRex in advanced stateful mode. + - **TRex ASTF**: Improved capability to run TRex in advanced stateful mode. - **CSIT PAPI support**: Due to issues with PAPI performance, VAT is still used in CSIT for all VPP scale tests. See known issues below. - - **General Code Housekeeping**: Ongoing RF keywords optimizations, - removal of redundant RF keywords and aligning of suite/test - setup/teardowns. - - - **Intel E810CQ 100G NIC**: Added configuration for Intel E810CQ 100G NIC. - No tests run for this NIC as it is not present in FD.io CSIT lab yet. + - **General Code Housekeeping**: Ongoing code optimizations, + speed ups and bug fixes. #. PRESENTATION AND ANALYTICS LAYER - - **Graphs improvements**: Added possibility to use Gbps on Y-axis in - Packet Throughput and Speedup Multi-Core graphs, added unidirectional - mode to the Latency graphs. + - **Graphs improvements**: Updated Packet Latency graphs, + see :ref:`latency_methodology`. .. raw:: latex @@ -113,9 +97,6 @@ List of known issues in |csit-release| for VPP performance tests: | | | interface link via i40e driver to up. | | | | CSIT implemented `workaround for AVF interface <https://gerrit.fd.io/r/c/csit/+/29086>`_ until fixed. | +----+-----------------------------------------+-----------------------------------------------------------------------------------------------------------+ -| 7 | `CSIT-1760 | All Mellanox / rdma driver tests are failing on LF testbed28 while successfully run on other LF testbeds. | -| | <https://jira.fd.io/browse/CSIT-1760>`_ | | -+----+-----------------------------------------+-----------------------------------------------------------------------------------------------------------+ Root Cause Analysis for Performance Changes ------------------------------------------- |