From 80e558550b0f076857618c4451987fb60ced19b9 Mon Sep 17 00:00:00 2001
From: Tibor Frank <tifrank@cisco.com>
Date: Thu, 9 Jan 2020 15:02:10 +0100
Subject: Report: Add 2n-clx

Change-Id: I34dc11c28d21f0b9fed87d76942fe8b8cdd86c88
Signed-off-by: Tibor Frank <tifrank@cisco.com>
---
 docs/report/vpp_performance_tests/hdrh_packet_latency_graphs/vts.rst | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'docs/report/vpp_performance_tests/hdrh_packet_latency_graphs/vts.rst')

diff --git a/docs/report/vpp_performance_tests/hdrh_packet_latency_graphs/vts.rst b/docs/report/vpp_performance_tests/hdrh_packet_latency_graphs/vts.rst
index 8a4c27e2d1..6e47279072 100644
--- a/docs/report/vpp_performance_tests/hdrh_packet_latency_graphs/vts.rst
+++ b/docs/report/vpp_performance_tests/hdrh_packet_latency_graphs/vts.rst
@@ -14,7 +14,7 @@ a.k.a. VPP data plane thread(s), and their physical CPU core(s)
 placement.
 
 CSIT source code for the test cases used for plots can be found in
-`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/vts?h=rls1908>`_.
+`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/vts?h=rls2001>`_.
 
 .. toctree::
 
-- 
cgit 1.2.3-korg