From 61407a72649b7b355472350c2186aa36bf8182e7 Mon Sep 17 00:00:00 2001 From: Peter Mikus Date: Mon, 24 Jul 2017 14:22:02 +0200 Subject: CSIT-618 Release report update VII Change-Id: Ide7771b59cc3ee7619502a6805c8401528a8c874 Signed-off-by: Peter Mikus --- .../packet_latency_graphs/l2.rst | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) (limited to 'docs/report/vpp_performance_tests/packet_latency_graphs/l2.rst') diff --git a/docs/report/vpp_performance_tests/packet_latency_graphs/l2.rst b/docs/report/vpp_performance_tests/packet_latency_graphs/l2.rst index c46fd03a38..d6e76a7c88 100644 --- a/docs/report/vpp_performance_tests/packet_latency_graphs/l2.rst +++ b/docs/report/vpp_performance_tests/packet_latency_graphs/l2.rst @@ -11,9 +11,15 @@ VPP packet latency in 1t1c setup (1thread, 1core) is presented in the graph belo .. raw:: html - + -*Figure 1. VPP 1thread 1core - packet latency for Phy-to-Phy L2 Ethernet Switching.* +*Figure 1a. VPP 1thread 1core - packet latency for Phy-to-Phy L2 Ethernet Switching.* + +.. raw:: html + + + +*Figure 1b. VPP 1thread 1core - packet latency for Phy-to-Phy L2 Ethernet Switching.* CSIT source code for the test cases used for above plots can be found in CSIT git repository: @@ -25,9 +31,15 @@ VPP packet latency in 2t2c setup (2thread, 2core) is presented in the graph belo .. raw:: html - + + +*Figure 2a. VPP 2threads 2cores - packet latency for Phy-to-Phy L2 Ethernet Switching.* + +.. raw:: html + + -*Figure 2. VPP 2threads 2cores - packet latency for Phy-to-Phy L2 Ethernet Switching.* +*Figure 2b. VPP 2threads 2cores - packet latency for Phy-to-Phy L2 Ethernet Switching.* CSIT source code for the test cases used for above plots can be found in CSIT git repository: -- cgit 1.2.3-korg