From e01470ec9038338409a494a2652eecabf4394578 Mon Sep 17 00:00:00 2001 From: Tibor Frank Date: Tue, 29 May 2018 10:45:47 +0200 Subject: CSIT-1105: Prepare and generate 18.01.2 report Change-Id: Iebda4fd10701c27512b443c14b2aeef314003d58 Signed-off-by: Tibor Frank --- .../packet_latency_graphs/srv6.rst | 48 ++++++++++++++++++++++ 1 file changed, 48 insertions(+) create mode 100644 docs/report/vpp_performance_tests/packet_latency_graphs/srv6.rst (limited to 'docs/report/vpp_performance_tests/packet_latency_graphs/srv6.rst') diff --git a/docs/report/vpp_performance_tests/packet_latency_graphs/srv6.rst b/docs/report/vpp_performance_tests/packet_latency_graphs/srv6.rst new file mode 100644 index 0000000000..163d892cde --- /dev/null +++ b/docs/report/vpp_performance_tests/packet_latency_graphs/srv6.rst @@ -0,0 +1,48 @@ +SRv6 +==== + +This section includes summary graphs of VPP Phy-to-Phy packet latency +with SRv6 measured at 50% of discovered NDR throughput +rate. Latency is reported for VPP running in multiple configurations of +VPP worker thread(s), a.k.a. VPP data plane thread(s), and their +physical CPU core(s) placement. + +VPP packet latency in 1t1c setup (1thread, 1core) is presented in the graph below. + +.. raw:: html + + + +.. raw:: latex + + \begin{figure}[H] + \centering + \graphicspath{{../_build/_static/vpp/}} + \includegraphics[clip, trim=0cm 8cm 5cm 0cm, width=0.70\textwidth]{78B-1t1c-ethip6-srv6-ndrdisc-lat50} + \label{fig:78B-1t1c-ethip6-srv6-ndrdisc-lat50} + \end{figure} + +*Figure 1. VPP 1thread 1core - packet latency for Phy-to-Phy SRv6.* + +CSIT source code for the test cases used for above plots can be found in +`CSIT git repository `_. + +VPP packet latency in 2t2c setup (2thread, 2core) is presented in the graph below. + +.. raw:: html + + + +.. raw:: latex + + \begin{figure}[H] + \centering + \graphicspath{{../_build/_static/vpp/}} + \includegraphics[clip, trim=0cm 8cm 5cm 0cm, width=0.70\textwidth]{78B-2t2c-ethip6-srv6-ndrdisc-lat50} + \label{fig:78B-2t2c-ethip6-srv6-ndrdisc-lat50} + \end{figure} + +*Figure 2. VPP 2threads 2cores - packet latency for Phy-to-Phy SRv6.* + +CSIT source code for the test cases used for above plots can be found in +`CSIT git repository `_. -- cgit 1.2.3-korg