From 7bd81f76b9c5b9dc3ab6a1df6156dac3fca16240 Mon Sep 17 00:00:00 2001
From: Tibor Frank <tifrank@cisco.com>
Date: Thu, 9 Feb 2023 14:05:25 +0100
Subject: Report: Set rls2302 in links

Signed-off-by: Tibor Frank <tifrank@cisco.com>
Change-Id: I1fadafd89108c832e933e98632aad4de567de11e
---
 .../vpp_performance_tests/throughput_speedup_multi_core/ip4_tunnels.rst | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'docs/report/vpp_performance_tests/throughput_speedup_multi_core/ip4_tunnels.rst')

diff --git a/docs/report/vpp_performance_tests/throughput_speedup_multi_core/ip4_tunnels.rst b/docs/report/vpp_performance_tests/throughput_speedup_multi_core/ip4_tunnels.rst
index 30eb89f583..091660ecfa 100644
--- a/docs/report/vpp_performance_tests/throughput_speedup_multi_core/ip4_tunnels.rst
+++ b/docs/report/vpp_performance_tests/throughput_speedup_multi_core/ip4_tunnels.rst
@@ -15,7 +15,7 @@ running in multiple configurations of VPP worker thread(s), a.k.a. VPP
 data plane thread(s), and their physical CPU core(s) placement.
 
 CSIT source code for the test cases used for plots can be found in
-`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/ip4_tunnels?h=rls2210>`_.
+`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/ip4_tunnels?h=rls2302>`_.
 
 .. toctree::
 
-- 
cgit 1.2.3-korg