From e01470ec9038338409a494a2652eecabf4394578 Mon Sep 17 00:00:00 2001 From: Tibor Frank Date: Tue, 29 May 2018 10:45:47 +0200 Subject: CSIT-1105: Prepare and generate 18.01.2 report Change-Id: Iebda4fd10701c27512b443c14b2aeef314003d58 Signed-off-by: Tibor Frank --- .../throughput_speedup_multi_core/ipsec.rst | 71 ++++++++++++++++++++++ 1 file changed, 71 insertions(+) create mode 100644 docs/report/vpp_performance_tests/throughput_speedup_multi_core/ipsec.rst (limited to 'docs/report/vpp_performance_tests/throughput_speedup_multi_core/ipsec.rst') diff --git a/docs/report/vpp_performance_tests/throughput_speedup_multi_core/ipsec.rst b/docs/report/vpp_performance_tests/throughput_speedup_multi_core/ipsec.rst new file mode 100644 index 0000000000..a5a4d7d1bc --- /dev/null +++ b/docs/report/vpp_performance_tests/throughput_speedup_multi_core/ipsec.rst @@ -0,0 +1,71 @@ +IPSec Crypto HW: IP4 Routed-Forwarding +====================================== + +Following sections include Throughput Speedup Analysis for VPP multi- +core multi-thread configurations with no Hyper-Threading, specifically +for tested 2t2c (2threads, 2cores) and 4t4c scenarios. 1t1c throughput +results are used as a reference for reported speedup ratio. +VPP IPSec encryption is accelerated using DPDK cryptodev +library driving Intel Quick Assist (QAT) crypto PCIe hardware cards. +Performance is reported for VPP running in multiple configurations of +VPP worker thread(s), a.k.a. VPP data plane thread(s), and their +physical CPU core(s) placement. + +NDR Throughput +-------------- + +VPP NDR 64B packet throughput speedup ratio is presented in the graphs +below for 40ge2p1xl710 network interface card. + +NIC 40ge2p1xl710 +~~~~~~~~~~~~~~~~ + +.. raw:: html + + + +.. raw:: latex + + \begin{figure}[H] + \centering + \graphicspath{{../_build/_static/vpp/}} + \includegraphics[clip, trim=0cm 8cm 5cm 0cm, width=0.70\textwidth]{40ge2p1xl710-64B-ipsechw-tsa-ndrdisc} + \label{fig:40ge2p1xl710-64B-ipsechw-tsa-ndrdisc} + \end{figure} + +*Figure 1. Throughput Speedup Analysis - Multi-Core Speedup Ratio - Normalized +NDR Throughput for Phy-to-Phy IPSEC HW.* + +CSIT source code for the test cases used for above plots can be found in +`CSIT git repository `_. + +PDR Throughput +-------------- + +VPP PDR 64B packet throughput speedup ratio is presented in the graphs +below for 40ge2p1xl710 network interface card. + +NIC 40ge2p1xl710 +~~~~~~~~~~~~~~~~ + +VPP PDR 64B packet throughput in 1t1c setup (1thread, 1core) is presented +in the graph below. PDR measured for 0.5% packet loss ratio. + +.. raw:: html + + + +.. raw:: latex + + \begin{figure}[H] + \centering + \graphicspath{{../_build/_static/vpp/}} + \includegraphics[clip, trim=0cm 8cm 5cm 0cm, width=0.70\textwidth]{40ge2p1xl710-64B-ipsechw-tsa-pdrdisc} + \label{fig:40ge2p1xl710-64B-ipsechw-tsa-pdrdisc} + \end{figure} + +*Figure 2. Throughput Speedup Analysis - Multi-Core Speedup Ratio - Normalized +PDR Throughput for Phy-to-Phy IPSEC HW.* + +CSIT source code for the test cases used for above plots can be found in +`CSIT git repository `_. -- cgit 1.2.3-korg