From 25a8fe0aa594ca010b7f1aad449a2af2b6625bd7 Mon Sep 17 00:00:00 2001 From: Tibor Frank Date: Wed, 22 Jan 2020 15:27:29 +0100 Subject: Report: Add diagrams for testbeds - Diagrams for testbeds: - 3n-dnv - 3n-tsh - 2n-clx - Replace s/Cascadelake/Cascade Lake Change-Id: I77e7659a0aba4766a28577f940b7e44e60cbd82d Signed-off-by: Tibor Frank --- docs/report/introduction/physical_testbeds.rst | 10 +- .../report/introduction/test_environment_intro.rst | 4 +- .../test_environment_sut_calib_clx.rst | 8 +- docs/report/introduction/testbed-2n-clx.svg | 1864 ++++++++++++++++++++ docs/report/introduction/testbed-3n-dnv.svg | 1220 +++++++++++++ docs/report/introduction/testbed-3n-tsh.svg | 1316 ++++++++++++++ 6 files changed, 4411 insertions(+), 11 deletions(-) create mode 100644 docs/report/introduction/testbed-2n-clx.svg create mode 100644 docs/report/introduction/testbed-3n-dnv.svg create mode 100644 docs/report/introduction/testbed-3n-tsh.svg (limited to 'docs/report') diff --git a/docs/report/introduction/physical_testbeds.rst b/docs/report/introduction/physical_testbeds.rst index 8860638d43..159728d8ee 100644 --- a/docs/report/introduction/physical_testbeds.rst +++ b/docs/report/introduction/physical_testbeds.rst @@ -27,7 +27,7 @@ Current FD.io production testbeds are built with SUT servers based on the following processor architectures: - Intel Xeon: Skylake Platinum 8180, Haswell-SP E5-2699v3, - Cascadelake Platinum 8280, Cascadelake 6252N. + Cascade Lake Platinum 8280, Cascade Lake 6252N. - Intel Atom: Denverton C3858. - ARM: TaiShan 2280, hip07-d05. @@ -41,13 +41,13 @@ https://git.fd.io/csit/tree/docs/lab/testbed_specifications.md. Following is the description of existing production testbeds. -2-Node Xeon Cascadelake (2n-clx) --------------------------------- +2-Node Xeon Cascade Lake (2n-clx) +--------------------------------- Three 2n-clx testbeds are in operation in FD.io labs. Each 2n-clx testbed is built with two SuperMicro SYS-7049GP-TRT servers, SUTs are equipped with two Intel Xeon Gold 6252N processors (35.75 MB Cache, 2.30 GHz, 24 cores). -TGs are equiped with Intel Xeon Cascadelake Platinum 8280 processors (38.5 MB +TGs are equiped with Intel Xeon Cascade Lake Platinum 8280 processors (38.5 MB Cache, 2.70 GHz, 28 cores). 2n-clx physical topology is shown below. .. only:: latex @@ -86,7 +86,7 @@ NIC models: #. NIC-5: empty, future expansion. #. NIC-6: x710-DA4 4p10GE Intel. (For self-tests.) -All Intel Xeon Cascadelake servers run with Intel Hyper-Threading enabled, +All Intel Xeon Cascade Lake servers run with Intel Hyper-Threading enabled, doubling the number of logical cores exposed to Linux. 2-Node Xeon Skylake (2n-skx) diff --git a/docs/report/introduction/test_environment_intro.rst b/docs/report/introduction/test_environment_intro.rst index b02520b99d..0d35acee72 100644 --- a/docs/report/introduction/test_environment_intro.rst +++ b/docs/report/introduction/test_environment_intro.rst @@ -15,7 +15,7 @@ topology types are used: server as TG both connected in ring topology. Tested SUT servers are based on a range of processors including Intel -Xeon Haswell-SP, Intel Xeon Skylake-SP, Intel Xeon Cascadelake-SP, Arm, Intel +Xeon Haswell-SP, Intel Xeon Skylake-SP, Intel Xeon Cascade Lake-SP, Arm, Intel Atom. More detailed description is provided in :ref:`tested_physical_topologies`. Tested logical topologies are described in :ref:`tested_logical_topologies`. @@ -25,7 +25,7 @@ Server Specifications Complete technical specifications of compute servers used in CSIT physical testbeds are maintained in FD.io CSIT repository: -`FD.io CSIT testbeds - Xeon Cascadelake`_, +`FD.io CSIT testbeds - Xeon Cascade Lake`_, `FD.io CSIT testbeds - Xeon Skylake, Arm, Atom`_ and `FD.io CSIT Testbeds - Xeon Haswell`_. diff --git a/docs/report/introduction/test_environment_sut_calib_clx.rst b/docs/report/introduction/test_environment_sut_calib_clx.rst index 823346f079..e12b0af693 100644 --- a/docs/report/introduction/test_environment_sut_calib_clx.rst +++ b/docs/report/introduction/test_environment_sut_calib_clx.rst @@ -1,11 +1,11 @@ -Calibration Data - Cascadelake ------------------------------- +Calibration Data - Cascade Lake +------------------------------- Following sections include sample calibration data measured on s32-t27-sut1 server running in one of the Intel Xeon Skylake testbeds as -specified in `FD.io CSIT testbeds - Xeon Cascadelake`_. +specified in `FD.io CSIT testbeds - Xeon Cascade Lake`_. -Calibration data obtained from all other servers in Cascadelake testbeds +Calibration data obtained from all other servers in Cascade Lake testbeds shows the same or similar values. diff --git a/docs/report/introduction/testbed-2n-clx.svg b/docs/report/introduction/testbed-2n-clx.svg new file mode 100644 index 0000000000..326d66ed48 --- /dev/null +++ b/docs/report/introduction/testbed-2n-clx.svg @@ -0,0 +1,1864 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + NIC6 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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