From 8b25d1ad5d2264bdfc2818c7bda74ee2697df6db Mon Sep 17 00:00:00 2001 From: Christian Ehrhardt Date: Wed, 6 Jul 2016 09:22:35 +0200 Subject: Imported Upstream version 16.07-rc1 Change-Id: I40a523e52f12e8496fdd69e902824b0226c303de Signed-off-by: Christian Ehrhardt --- .../ip_pipeline/config/edge_router_upstream.cfg | 36 +++++++++++++++------- 1 file changed, 25 insertions(+), 11 deletions(-) (limited to 'examples/ip_pipeline/config/edge_router_upstream.cfg') diff --git a/examples/ip_pipeline/config/edge_router_upstream.cfg b/examples/ip_pipeline/config/edge_router_upstream.cfg index a08c5cce..dea42b95 100644 --- a/examples/ip_pipeline/config/edge_router_upstream.cfg +++ b/examples/ip_pipeline/config/edge_router_upstream.cfg @@ -1,6 +1,6 @@ ; BSD LICENSE ; -; Copyright(c) 2015 Intel Corporation. All rights reserved. +; Copyright(c) 2015-2016 Intel Corporation. All rights reserved. ; All rights reserved. ; ; Redistribution and use in source and binary forms, with or without @@ -29,6 +29,7 @@ ; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ; An edge router typically sits between two networks such as the provider ; core network and the provider access network. A typical packet processing ; pipeline for the upstream traffic (i.e. traffic from access to core @@ -36,10 +37,10 @@ ; Flow classification, Metering, Routing and Packet TX. The input packets ; are assumed to be Q-in-Q IPv4, while the output packets are MPLS IPv4 ; (with variable number of labels per route). - +; ; A simple implementation for this functional pipeline is presented below. - -; Packet Rx & Pass-Through Flow-Classification Flow-Actions Routing +; +; Packet RX & Pass-Through Flow Classification Flow Actions Routing : Firewall ; __________ SWQ0 __________ SWQ4 __________ SWQ8 __________ SWQ12 __________ ; RXQ0.0 --->| |------>| |------>| |------>| |------>| |------> TXQ0.0 @@ -51,8 +52,21 @@ ; RXQ3.0 --->| |------>| |------>| |------>| |------>| |------> TXQ3.0 ; |__________| |__________| |__________| |__________| |__________| ; | | | -; +--> SINK0 (Default) +--> SINK1 (Default) +--> SINK2 (Route Miss) +; +--> SINK0 (Default) +--> SINK1 (Default) +--> SINK2 (Default) +; +; Input packet: Ethernet/QinQ/IPv4 +; Output packet: Ethernet/MPLS/IPv4 +; +; Packet buffer layout: +; # Field Name Offset (Bytes) Size (Bytes) +; 0 Mbuf 0 128 +; 1 Headroom 128 128 +; 2 Ethernet header 256 14 +; 3 QinQ header 270 8 +; 4 IPv4 header 278 20 +[EAL] +log_level = 0 [PIPELINE0] type = MASTER @@ -72,10 +86,10 @@ core = 2 pktq_in = SWQ0 SWQ1 SWQ2 SWQ3 pktq_out = SWQ4 SWQ5 SWQ6 SWQ7 dma_size = 8 -dma_dst_offset = 128; mbuf (128) -dma_src_offset = 268; mbuf (128) + headroom (128) + 1st ethertype offset (12) = 268 +dma_dst_offset = 128 +dma_src_offset = 268; 1st Ethertype offset dma_src_mask = 00000FFF00000FFF; qinq -dma_hash_offset = 136; dma_dst_offset + dma_size = 136 +dma_hash_offset = 136; dma_dst_offset + dma_size [PIPELINE3] type = FLOW_CLASSIFICATION @@ -86,7 +100,7 @@ n_flows = 65536 key_size = 8; dma_size key_offset = 128; dma_dst_offset hash_offset = 136; dma_hash_offset -flowid_offset = 192; mbuf (128) + 64 +flowid_offset = 192 [PIPELINE4] type = FLOW_ACTIONS @@ -96,7 +110,7 @@ pktq_out = SWQ12 SWQ13 SWQ14 SWQ15 n_flows = 65536 n_meters_per_flow = 1 flow_id_offset = 192; flowid_offset -ip_hdr_offset = 278; mbuf (128) + headroom (128) + ethernet (14) + qinq (8) = 278 +ip_hdr_offset = 278 color_offset = 196; flowid_offset + sizeof(flow_id) [PIPELINE5] @@ -106,5 +120,5 @@ pktq_in = SWQ12 SWQ13 SWQ14 SWQ15 pktq_out = TXQ0.0 TXQ1.0 TXQ2.0 TXQ3.0 SINK2 encap = ethernet_mpls mpls_color_mark = yes -ip_hdr_offset = 278; mbuf (128) + headroom (128) + ethernet (14) + qinq (8) = 278 +ip_hdr_offset = 278 color_offset = 196; flowid_offset + sizeof(flow_id) -- cgit 1.2.3-korg