;   BSD LICENSE
;
;   Copyright(c) 2015-2016 Intel Corporation. All rights reserved.
;   All rights reserved.
;
;   Redistribution and use in source and binary forms, with or without
;   modification, are permitted provided that the following conditions
;   are met:
;
;     * Redistributions of source code must retain the above copyright
;       notice, this list of conditions and the following disclaimer.
;     * Redistributions in binary form must reproduce the above copyright
;       notice, this list of conditions and the following disclaimer in
;       the documentation and/or other materials provided with the
;       distribution.
;     * Neither the name of Intel Corporation nor the names of its
;       contributors may be used to endorse or promote products derived
;       from this software without specific prior written permission.
;
;   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
;   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
;   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
;   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
;   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
;   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
;   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
;   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
;   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
;   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
;   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.


;   An edge router typically sits between two networks such as the provider
;   core network and the provider access network. A typical packet processing
;   pipeline for the upstream traffic (i.e. traffic from access to core
;   network) contains the following functional blocks: Packet RX & Firewall,
;   Flow classification, Metering, Routing and Packet TX. The input packets
;   are assumed to be Q-in-Q IPv4, while the output packets are MPLS IPv4
;  (with variable number of labels per route).
;
;   A simple implementation for this functional pipeline is presented below.
;
;             Packet RX &       Pass-Through    Flow Classification   Flow Actions         Routing
:              Firewall
;             __________  SWQ0   __________  SWQ4   __________  SWQ8   __________  SWQ12  __________
; RXQ0.0 --->|          |------>|          |------>|          |------>|          |------>|          |------> TXQ0.0
;            |          | SWQ1  |          | SWQ5  |          | SWQ9  |          | SWQ13 |          |
; RXQ1.0 --->|          |------>|          |------>|          |------>|          |------>|          |------> TXQ1.0
;            |   (P1)   | SWQ2  |  (P2)    | SWQ6  |   (P3)   | SWQ10 |   (P4)   | SWQ14 |   (P5)   |
; RXQ2.0 --->|          |------>|          |------>|          |------>|          |------>|          |------> TXQ2.0
;            |          | SWQ3  |          | SWQ7  |          | SWQ11 |          | SWQ15 |          |
; RXQ3.0 --->|          |------>|          |------>|          |------>|          |------>|          |------> TXQ3.0
;            |__________|       |__________|       |__________|       |__________|       |__________|
;                 |                                     |                                     |
;                 +--> SINK0 (Default)                  +--> SINK1 (Default)                  +--> SINK2 (Default)
;
; Input packet: Ethernet/QinQ/IPv4
; Output packet: Ethernet/MPLS/IPv4
;
; Packet buffer layout:
; #	Field Name		Offset (Bytes)	Size (Bytes)
; 0	Mbuf			0 		128
; 1	Headroom		128 		128
; 2	Ethernet header		256 		14
; 3     QinQ header             270             8
; 4	IPv4 header		278 		20

[EAL]
log_level = 0

[PIPELINE0]
type = MASTER
core = 0

[PIPELINE1]
type = FIREWALL
core = 1
pktq_in = RXQ0.0 RXQ1.0 RXQ2.0 RXQ3.0
pktq_out = SWQ0 SWQ1 SWQ2 SWQ3 SINK0
n_rules = 4096
pkt_type = qinq_ipv4

[PIPELINE2]
type = PASS-THROUGH
core = 2
pktq_in = SWQ0 SWQ1 SWQ2 SWQ3
pktq_out = SWQ4 SWQ5 SWQ6 SWQ7
dma_size = 8
dma_dst_offset = 128
dma_src_offset = 268; 1st Ethertype offset
dma_src_mask = 00000FFF00000FFF; qinq
dma_hash_offset = 136; dma_dst_offset + dma_size

[PIPELINE3]
type = FLOW_CLASSIFICATION
core = 2
pktq_in = SWQ4 SWQ5 SWQ6 SWQ7
pktq_out = SWQ8 SWQ9 SWQ10 SWQ11 SINK1
n_flows = 65536
key_size = 8; dma_size
key_offset = 128; dma_dst_offset
hash_offset = 136; dma_hash_offset
flowid_offset = 192

[PIPELINE4]
type = FLOW_ACTIONS
core = 3
pktq_in = SWQ8 SWQ9 SWQ10 SWQ11
pktq_out = SWQ12 SWQ13 SWQ14 SWQ15
n_flows = 65536
n_meters_per_flow = 1
flow_id_offset = 192; flowid_offset
ip_hdr_offset = 278
color_offset = 196; flowid_offset + sizeof(flow_id)

[PIPELINE5]
type = ROUTING
core = 4
pktq_in = SWQ12 SWQ13 SWQ14 SWQ15
pktq_out = TXQ0.0 TXQ1.0 TXQ2.0 TXQ3.0 SINK2
encap = ethernet_mpls
mpls_color_mark = yes
ip_hdr_offset = 278
color_offset = 196; flowid_offset + sizeof(flow_id)