From 021f0d49b2607baa05d13f8badfc8f8e51edc43b Mon Sep 17 00:00:00 2001 From: Hanoh Haim Date: Thu, 23 Jun 2016 17:23:45 +0300 Subject: enable fcs test --- scripts/automation/regression/stateless_tests/stl_rx_test.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'scripts/automation/regression/stateless_tests') diff --git a/scripts/automation/regression/stateless_tests/stl_rx_test.py b/scripts/automation/regression/stateless_tests/stl_rx_test.py index 0dbc7f31..2b6684fd 100644 --- a/scripts/automation/regression/stateless_tests/stl_rx_test.py +++ b/scripts/automation/regression/stateless_tests/stl_rx_test.py @@ -441,13 +441,13 @@ class STLRX_Test(CStlGeneral_Test): def test_fcs_stream(self): """ this test send 1 64 byte packet with latency and check that all counters are reported as 64 bytes""" - self.skip('Skip due to bug trex-213') + #self.skip('Skip due to bug trex-213') all_ports=list(CTRexScenario.stl_ports_map['map'].keys()); for port in all_ports: for l in [True,False]: print(" test port {0} latency : {1} ".format(port,l)) - self.send_1_burst(port,l,100) + self.send_1_burst(port,False,100) # this test adds more and more latency streams and re-test with incremental -- cgit 1.2.3-korg