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author | Zhiyong Yang <zhiyong.yang@intel.com> | 2018-09-04 22:45:17 -0400 |
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committer | John Lo <loj@cisco.com> | 2018-09-06 22:08:45 +0000 |
commit | 70fda4c443be1c7893e88c68f36b57f8168f4e54 (patch) | |
tree | 8e7eb1e8d61d38c8da611c7b1ce135fb182d8948 /src/vnet/lisp-cp/lisp_msg_serdes.h | |
parent | ecdfb2cbee547a113d3700da07c8920924bfb62d (diff) |
vxlan: improve encap performance
1. For vxlan, prefetching one cacheline is enough.
2. Reduce vlib_increment_combined_counter functtion calling
if possible.
Change-Id: If3a72ac40c8988caaf0d5915b695f86d799f15a9
Signed-off-by: Zhiyong Yang <zhiyong.yang@intel.com>
Diffstat (limited to 'src/vnet/lisp-cp/lisp_msg_serdes.h')
0 files changed, 0 insertions, 0 deletions