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authorDamjan Marion <damjan.marion@gmail.com>2020-02-16 13:07:13 +0100
committerNeale Ranns <nranns@cisco.com>2020-02-17 10:40:01 +0000
commit627fb6a16d8e7430e84aa664cb2b8f89a5688fab (patch)
tree76a05a6c79302f3ab0601425ada1d56663209a79 /src/vppinfra/vector_avx512.h
parent4fbb9daa90b53e0abaa060cf6db7762e708ce5b6 (diff)
crypto-native: calculate ghash using vpclmulqdq instructions
vpclmulqdq is introduced on intel icelake architecture and allows computing 4 carry-less multiplications in paralled by using 512-bit SIMD registers Type: feature Change-Id: Idb09d6f51ba6f116bba11649b2d99f649356d449 Signed-off-by: Damjan Marion <damjan.marion@gmail.com>
Diffstat (limited to 'src/vppinfra/vector_avx512.h')
-rw-r--r--src/vppinfra/vector_avx512.h15
1 files changed, 15 insertions, 0 deletions
diff --git a/src/vppinfra/vector_avx512.h b/src/vppinfra/vector_avx512.h
index e27c7c041e4..efdc78bdc02 100644
--- a/src/vppinfra/vector_avx512.h
+++ b/src/vppinfra/vector_avx512.h
@@ -113,6 +113,18 @@ u32x16_extract_hi (u32x16 v)
return (u32x8) _mm512_extracti64x4_epi64 ((__m512i) v, 1);
}
+static_always_inline u8x32
+u8x64_extract_lo (u8x64 v)
+{
+ return (u8x32) _mm512_extracti64x4_epi64 ((__m512i) v, 0);
+}
+
+static_always_inline u8x32
+u8x64_extract_hi (u8x64 v)
+{
+ return (u8x32) _mm512_extracti64x4_epi64 ((__m512i) v, 1);
+}
+
static_always_inline u32
u32x16_min_scalar (u32x16 v)
{
@@ -149,6 +161,9 @@ u64x8_permute (u64x8 a, u64x8 b, u64x8 mask)
#define u8x64_extract_u8x16(a, n) \
(u8x16) _mm512_extracti64x2_epi64 ((__m512i) (a), n)
+#define u8x64_word_shift_left(a,n) (u8x64) _mm512_bslli_epi128((__m512i) a, n)
+#define u8x64_word_shift_right(a,n) (u8x64) _mm512_bsrli_epi128((__m512i) a, n)
+
static_always_inline u8x64
u8x64_xor3 (u8x64 a, u8x64 b, u8x64 c)
{