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authorZhiyong Yang <zhiyong.yang@intel.com>2019-07-24 22:06:55 -0400
committerDamjan Marion <dmarion@me.com>2019-07-25 09:01:12 +0000
commit8a4f6dadfd56b96a65010d77ed28522c51d0cfa9 (patch)
tree71b32d0d8084f632a4a842985bcb37ea884dde18 /test/debug_internal.py
parent0dbaa59e075f9ac44b0bd23ed2c9adbd85215e8f (diff)
misc: leverage vlib_buffer_get_current in srp
Type: style Change-Id: I6c57ab3e71c693de5ecfbdfee118d521a8c9a4c2 Signed-off-by: Zhiyong Yang <zhiyong.yang@intel.com>
Diffstat (limited to 'test/debug_internal.py')
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