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2021-03-16perfmon: fixes for cache hierarchyRay Kinsella1-8/+12
Account for occasional instances with the misses rates between caches are inconsistent. Type: fix Signed-off-by: Ray Kinsella <mdr@ashroe.eu> Change-Id: Idfb8bb7543401405cfe04291ad201c28be030cc9
2021-03-16perfmon: add support for raw and timestampsRay Kinsella3-1/+24
Add perfmon plugin support to output raw counter and timestamps, both are useful for debug. Type: improvement Signed-off-by: Ray Kinsella <mdr@ashroe.eu> Change-Id: Ia5a73d1f05e3464c18991c2346f0ed8b7ef63099
2021-01-21perfmon: added cache hits and missesRay Kinsella2-0/+70
Added basic support for counting cache hits and misses per node. Type: improvement Signed-off-by: Ray Kinsella <mdr@ashroe.eu> Change-Id: Ic566611fd3d4246ccaa2117d8f74a569a6862e80
2020-12-18perfmon: new perfmon pluginDamjan Marion15-0/+2246
Type: feature Change-Id: I2c14f82393d11fc05c6d229f5c58603ab5c0f14d Signed-off-by: Damjan Marion <damarion@cisco.com>
2020-12-18misc: deprecate old perfmonDamjan Marion25-25549/+0
Type: refactor Change-Id: I1303219f9f2a25d821737665903b0264edd3de32 Signed-off-by: Damjan Marion <damarion@cisco.com>
2020-12-14misc: move to new pool_foreach macrosDamjan Marion1-3/+3
Type: refactor Change-Id: Ie67dc579e88132ddb1ee4a34cb69f96920101772 Signed-off-by: Damjan Marion <damarion@cisco.com>
2020-07-16misc: add callback hooks and refactor pmcTom Seidenberg8-155/+313
Callbacks for monitoring and performance measurement: - Add new callback list type, with context - Add callbacks for API, CLI, and barrier sync - Modify node dispatch callback to pass plugin-specific context - Modify perfmon plugin to keep PMC samples local to the plugin - Include process nodes in dispatch callback - Pass dispatch function return value to callback Type: refactor Signed-off-by: Tom Seidenberg <tseidenb@cisco.com> Change-Id: I28b06c58490611e08d76ff5b01b2347ba2109b22
2020-04-22misc: asan: do not poison memory after munmap()Benoît Ganne1-2/+0
It is a bad idea to poison memory after munmap because the address space can be reused (eg. for global data of dlopen()ed object) and ASan model allows access by default. Moreover, access to a stale address space will fault. Type: fix Change-Id: I356de422f255447d9d50a3a71fb0c2eaa790d731 Signed-off-by: Benoît Ganne <bganne@cisco.com>
2019-12-17perfmon: fix per-worker data initializationBenoît Ganne2-9/+14
When perfmon_init is called at initialization time worker threads are not created yet and vec_len(vlib_mains) returns 1. Initialize per-worker data when the number of workers is known, when enabling data collection instead. Type: fix Change-Id: I36887cc7b2a3e88d9728d3cd7262d9b1c968dd3c Signed-off-by: Benoît Ganne <bganne@cisco.com>
2019-05-24Add callback multiplex supportDave Barach1-15/+47
Change-Id: Iddeb3a1b0e20706e72ec8f74dabc60b342f003ba Signed-off-by: Dave Barach <dave@barachs.net>
2019-05-03plugins: clean up plugin descriptionsDave Wallace1-1/+1
- Make plugin descriptions more consistent so the output of "show plugin" can be used in the wiki. Change-Id: I4c6feb11e7dcc5a4cf0848eed37f1d3b035c7dda Signed-off-by: Dave Wallace <dwallacelf@gmail.com>
2019-05-01Add node, frame to vlib main loop perf analysis callback argumentsDave Barach1-1/+3
Change-Id: Iaa5cd89791b0dfdb56a75009c564581d10696d83 Signed-off-by: Dave Barach <dave@barachs.net>
2019-03-26perfmon: fix pmc hw indices out-dated when multiple pmcSu Wang1-3/+15
When adding two or more events using a single "set pmc", the pmc hardware indices might be out-dated due to kernel reschdeduling the perf_event hardware counters. E.g. set pmc cpu-cycles cache-misses Solution: Open and enable all the events first, then aquire the indices from the kernel. Change-Id: I6913a871ab169e3b2855ac6159f527a1fca343e9 Signed-off-by: Su Wang <su.z.wang@ericsson.com>
2019-03-20perfmon: python to C parser for intel CPUsDamjan Marion24-445/+23854
EXAMPLE: src/plugins/perfmon/intel_json_to_c.py \ -i skylakex_core_v1.12.json \ -o src/plugins/perfmon/perfmon_intel_skx.c \ -m 0x55,0 \ -m 0x55,1 \ -m 0x55,2 \ -m 0x55,3 Change-Id: I16ce059e231d340ecfcb6f6638e29c5b46304683 Signed-off-by: Damjan Marion <damarion@cisco.com>
2019-01-27Fix issue with cpu_id and numa_code captured too earlyDamjan Marion1-1/+1
Change-Id: I79b213b34c6071d14acf1922f89037a4a5a36c45 Signed-off-by: Damjan Marion <damarion@cisco.com>
2019-01-27perfmon: collect data on selected thread(s)Dave Barach3-18/+86
Add missing pre-input node runtime fork and refork code. unix-epoll-input runs on all threads; each instance needs its own runtime stats. Change-Id: I16b02e42d0c95f863161176c4bb9f9917bef809d Signed-off-by: Dave Barach <dave@barachs.net>
2019-01-24perfmon: enable pmc event before reading rdpmc indexDamjan Marion1-6/+6
Change-Id: I9b0a101e5d78c10257e3c5d8f5573c3eb29bfdef Signed-off-by: Damjan Marion <damarion@cisco.com>
2019-01-24perfmon plugin: 2-way parallel stat collectionDave Barach3-143/+228
As a FUD reduction measure, this patch implements 2-way parallel counter collection. Synthetic stat component counter pairs run at the same time. Running two counters (of any kind) at the same time naturally reduces the aggregate time required by an approximate factor-of-2, depending on whether an even or odd number of stats have been requested. I don't completely buy the argument that computing synthetic stats such as instructions-per-clock will be inaccurate if component counter values are collected sequentially. Given uniform traffic pattern, it must make no difference. As the collection interval increases, the difference between serial and parallel component counter collection will approach zero, see also the Central Limit theorem. Change-Id: I36ebdcf125e8882cca8a1929ec58f17fba1ad8f1 Signed-off-by: Dave Barach <dave@barachs.net>
2018-12-17Improve perfmon json table pickerDave Barach4-23/+341
Built a tool to chew up https://download.01.org/perfmon/mapfile.csv, and output a table in this format: typedef struct { u8 model; u8 stepping; u8 has_stepping; char *filename; } file_by_model_and_stepping_t; static const file_by_model_and_stepping_t fms_table [] = { /* model, stepping, stepping valid, file */ { 0x2E, 0x0, 0, "NehalemEX_core_V2.json" }, { 0x1E, 0x0, 0, "NehalemEP_core_V2.json" }, <snip> { 0x55, 0x5, 1, "cascadelakex_core_v1.00.json" }, { 0x55, 0x6, 1, "cascadelakex_core_v1.00.json" }, { 0x55, 0x7, 1, "cascadelakex_core_v1.00.json" }, <snip> Change-Id: Ie0e8a7e851799e9d060b966047745039c066ec7b Signed-off-by: Dave Barach <dave@barachs.net>
2018-11-14Remove c-11 memcpy checks from perf-critical codeDave Barach1-1/+1
Change-Id: Id4f37f5d4a03160572954a416efa1ef9b3d79ad1 Signed-off-by: Dave Barach <dave@barachs.net>
2018-10-25Add x86_64 perfmon tablesDave Barach3-20/+10
The license issue is resolved, so we can package the .json files. Added to the vpp-dev package in .tar.xz form, which saves a lot of space. Updated the perfmon error log entry: tell folks where to find the compressed tarball, and how to extract it. Change-Id: I3ed351fbf154cc3ba22d5f9c666acff77a2a14cf Signed-off-by: Dave Barach <dave@barachs.net>
2018-10-23VPP-1474: fix coverity warningDave Barach1-0/+3
Change-Id: I20f2fb14e00f3e7e96774959a4bf1a159ab9030f Signed-off-by: Dave Barach <dave@barachs.net>
2018-10-23perfmon.c: Register additional cpuids.Paul Vinciguerra1-4/+7
Added/tested additional cpuids from our testbed. Change-Id: Ifd3ea9e8e8231a8901966903bf5eceb635b82482 Signed-off-by: Paul Vinciguerra <pvinci@vinciconsulting.com>
2018-10-22X86_64 perf counter pluginDave Barach5-0/+1466
Change-Id: Ie5a00c15ee9536cc61afab57f6cadc1aa1972f3c Signed-off-by: Dave Barach <dave@barachs.net>