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2021-11-10vppinfra: new memcpy for x86_64Damjan Marion1-2/+3
Change-Id: I5a5055580479960ac53e3f989aa188faf57fb05d Type: improvement Signed-off-by: Damjan Marion <damarion@cisco.com>
2021-07-14vppinfra: remove old and unused vector macros and inlinesDamjan Marion1-41/+0
Type: refactor Change-Id: Ic504bcfca6e7fbd85e858c3bc7a4f5e72d931789 Signed-off-by: Damjan Marion <damarion@cisco.com>
2021-04-27vlib: improve enqueue_to_next buffer indices extractionDamjan Marion1-4/+0
Type: improvement Change-Id: Ib7b2fa7d821f6d2708f6dc378a0f36f68c843f57 Signed-off-by: Damjan Marion <damarion@cisco.com>
2021-04-21vppinfra: more avx512 inlines (compress, expand, from, is_equal_mask)Damjan Marion1-4/+1
Type: improvement Change-Id: I4cb86cafba92ae70cea160b9bf45f28a916ab6db Signed-off-by: Damjan Marion <damarion@cisco.com>
2020-07-23vppinfra: add *_zero() vector inlinesDamjan Marion1-0/+9
Type: improvement Change-Id: Ia63d1d7de273967ab7725d83634c0b6dd481c6c0 Signed-off-by: Damjan Marion <damarion@cisco.com>
2020-04-30build: rework x86 CPU variantsDamjan Marion1-2/+5
Type: improvement Change-Id: Ief243f88e654e578ef9b8060fcf535b364aececb Signed-off-by: Damjan Marion <damarion@cisco.com>
2019-09-26classify: use vector code even when data is not alignedDamjan Marion1-0/+2
Type: feature Change-Id: I8f5f4841965beb13ebc8c2a37ce0dc331c920109 Signed-off-by: Damjan Marion <damarion@cisco.com>
2018-08-2832/64 shmem bihash interoperabilityDave Barach1-2/+3
Move the binary api segment above 4gb Change-Id: I40e8aa7a97722a32397f5a538b5ff8344c50d408 Signed-off-by: Dave Barach <dave@barachs.net>
2018-05-20vector functions cleanup and improvementsDamjan Marion1-41/+18
Remove functions which have native C equivalent (i.e. _is_equal can be replaced with ==, _add with +) Add SSE4.2, AVX-512 implementations of splat, load_unaligned, store_unaligned, is_all_zero, is_equal, is_all_equal Change-Id: Ie80b0e482e7a76248ad79399c2576468532354cd Signed-off-by: Damjan Marion <damarion@cisco.com>
2018-04-25dpdk: complete rework of the dpdk-input nodeDamjan Marion1-3/+14
Change-Id: If174d189de40e6f9ffae99997bba93a2519d9fda Signed-off-by: Damjan Marion <damarion@cisco.com>
2018-02-21vppinfra: remove vector_iwmmxt.hDamjan Marion1-4/+0
Change-Id: I71fac34b071a07b4331cb5c900c3b8667c1fc114 Signed-off-by: Damjan Marion <damarion@cisco.com>
2018-02-20vppinfra: autogerate vector typedefs and basic inline functionsDamjan Marion1-139/+83
Change-Id: Ie9f611fa6a962b0937245f5cc949571ba11c5604 Signed-off-by: Damjan Marion <damarion@cisco.com>
2018-02-20vppinfra: CLIB_HAVE_VEC128 mandates SSE4.2Damjan Marion1-9/+3
Change-Id: I6511110d0472203498a4f8741781eeeeb4f90844 Signed-off-by: Damjan Marion <damarion@cisco.com>
2018-02-08add CLIB_HAVE_VEC128 with NEON intrinsics (VPP-1127)Gabriel Ganne1-8/+4
Enable CLIB_HAVE_VEC128 if both aarch64 and __ARM_NEON ie. armv8 only, not armv7 Add more neon compare intrinsics wrappers. I only add simple intrinsics wrappers. More complex ones can be added later as they are needed, with performance tests on the corresponding feature to back them up. Remove wrongly added 128bits definitions defined on both armv7 and armv8 without concern for NEON instructions presence. Notable correspondinf code activations: * MHEAP_FLAG_SMALL_OBJECT_CACHE in mheap.c * ip4 fib mtrie leaves access * enable ixge plugin compilation for aarch64 (conf still disables it by default) Change-Id: I99953823627bdff6f222d232c78aa7b655aaf77a Signed-off-by: Gabriel Ganne <gabriel.ganne@enea.com>
2017-11-10vppinfra: add 512-bit vector definitions and typesDamjan Marion1-0/+25
Change-Id: I245c034684ba8585c8f5bb5353027aba13f8a53e Signed-off-by: Damjan Marion <damarion@cisco.com>
2016-12-28Reorganize source tree to use single autotools instanceDamjan Marion1-0/+268
Change-Id: I7b51f88292e057c6443b12224486f2d0c9f8ae23 Signed-off-by: Damjan Marion <damarion@cisco.com>