From 473f46135c3fd77dad5614215cc279b1164e9a74 Mon Sep 17 00:00:00 2001 From: Dave Barach Date: Tue, 29 May 2018 17:06:45 -0400 Subject: Configure or deduce CLIB_LOG2_CACHE_LINE_BYTES (VPP-1064) Added configure argument "--with-log2-cache-line-bytes=5|6|7|auto" AKA 32, 64, or 128 bytes, or use the inferred value from the build host. produces build-xxx/vpp/vppinfra/config.h, which .../src/vppinfra/cache.h Kernels which implement the following pseudo-file (aka x86_64) are easy: /sys/devices/system/cpu/cpu0/cache/index0/coherency_line_size Otherwise, extract the cpuid from /proc/cpuinfo and map it to the cache line size. Change-Id: I7ff861e042faf82c3901fa1db98864fbdea95b74 Signed-off-by: Dave Barach Signed-off-by: Nitin Saxena --- dpdk/Makefile | 1 + 1 file changed, 1 insertion(+) (limited to 'dpdk/Makefile') diff --git a/dpdk/Makefile b/dpdk/Makefile index 331e1c34886..7b70346260c 100644 --- a/dpdk/Makefile +++ b/dpdk/Makefile @@ -124,6 +124,7 @@ ifneq (,$(findstring $(MIDR_PARTNUM),$(CPU_PART_CAVIUM_THUNDERX) \ $(CPU_PART_CAVIUM_THUNDERX_81XX) $(CPU_PART_CAVIUM_THUNDERX_83XX))) DPDK_TARGET = arm64-thunderx-linuxapp-$(DPDK_CC) DPDK_MACHINE = thunderx +DPDK_CACHE_LINE_SIZE := 128 else $(warning Unknown Cavium CPU) endif -- cgit 1.2.3-korg