From 473f46135c3fd77dad5614215cc279b1164e9a74 Mon Sep 17 00:00:00 2001 From: Dave Barach Date: Tue, 29 May 2018 17:06:45 -0400 Subject: Configure or deduce CLIB_LOG2_CACHE_LINE_BYTES (VPP-1064) Added configure argument "--with-log2-cache-line-bytes=5|6|7|auto" AKA 32, 64, or 128 bytes, or use the inferred value from the build host. produces build-xxx/vpp/vppinfra/config.h, which .../src/vppinfra/cache.h Kernels which implement the following pseudo-file (aka x86_64) are easy: /sys/devices/system/cpu/cpu0/cache/index0/coherency_line_size Otherwise, extract the cpuid from /proc/cpuinfo and map it to the cache line size. Change-Id: I7ff861e042faf82c3901fa1db98864fbdea95b74 Signed-off-by: Dave Barach Signed-off-by: Nitin Saxena --- src/plugins/dpdk/device/init.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/plugins') diff --git a/src/plugins/dpdk/device/init.c b/src/plugins/dpdk/device/init.c index b5a8e3bcd4b..ceaa5bb61e9 100644 --- a/src/plugins/dpdk/device/init.c +++ b/src/plugins/dpdk/device/init.c @@ -1691,6 +1691,8 @@ dpdk_init (vlib_main_t * vm) "Data in cache line 0 is bigger than cache line size"); STATIC_ASSERT (offsetof (frame_queue_trace_t, cacheline0) == 0, "Cache line marker must be 1st element in frame_queue_trace_t"); + STATIC_ASSERT (RTE_CACHE_LINE_SIZE == 1 << CLIB_LOG2_CACHE_LINE_BYTES, + "DPDK RTE CACHE LINE SIZE does not match with 1<vlib_main = vm; dm->vnet_main = vnet_get_main (); -- cgit 1.2.3-korg