From 162330f25aeec09694fffaaa31ba9b318620eb9c Mon Sep 17 00:00:00 2001
From: Damjan Marion <damarion@cisco.com>
Date: Wed, 29 Apr 2020 21:28:15 +0200
Subject: build: rework x86 CPU variants

Type: improvement
Change-Id: Ief243f88e654e578ef9b8060fcf535b364aececb
Signed-off-by: Damjan Marion <damarion@cisco.com>
---
 src/vppinfra/vector.h | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

(limited to 'src/vppinfra/vector.h')

diff --git a/src/vppinfra/vector.h b/src/vppinfra/vector.h
index 906d8d8fbfd..8b08db22124 100644
--- a/src/vppinfra/vector.h
+++ b/src/vppinfra/vector.h
@@ -66,7 +66,7 @@
 #endif
 #endif
 
-#if defined (__AVX512F__)
+#if defined (__AVX512BITALG__)
 #define CLIB_HAVE_VEC512
 #endif
 
@@ -168,7 +168,10 @@ typedef u64 u64x _vector_size (8);
 #include <vppinfra/vector_avx2.h>
 #endif
 
-#if defined (__AVX512F__)
+#if defined (__AVX512BITALG__)
+/* Due to power level transition issues, we don't preffer AVX-512 on
+   Skylake X and CascadeLake CPUs, AVX512BITALG is introduced on
+   icelake CPUs  */
 #include <vppinfra/vector_avx512.h>
 #endif
 
-- 
cgit 1.2.3-korg