From f75defa7676759fa81ae75e7edd492572c6b8fd6 Mon Sep 17 00:00:00 2001 From: Damjan Marion Date: Thu, 13 Feb 2020 18:14:06 +0100 Subject: vppinfra: add 128-bit and 512-bit a ^ b ^ c shortcut This allows us to combine 2 XOR operations into signle instruction which makes difference in crypto op: - in x86, by using ternary logic instruction - on ARM, by using EOR3 instruction (available with sha3 feature) Type: refactor Change-Id: Ibdf9001840399d2f838d491ca81b57cbd8430433 Signed-off-by: Damjan Marion --- src/vppinfra/vector_neon.h | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'src/vppinfra/vector_neon.h') diff --git a/src/vppinfra/vector_neon.h b/src/vppinfra/vector_neon.h index 81d99a64f05..3855f55ad41 100644 --- a/src/vppinfra/vector_neon.h +++ b/src/vppinfra/vector_neon.h @@ -203,6 +203,17 @@ u8x16_reflect (u8x16 v) return (u8x16) vqtbl1q_u8 (v, mask); } +static_always_inline u8x16 +u8x16_xor3 (u8x16 a, u8x16 b, u8x16 c) +{ +#if __GNUC__ == 8 && __ARM_FEATURE_SHA3 == 1 + u8x16 r; +__asm__ ("eor3 %0.16b,%1.16b,%2.16b,%3.16b": "=w" (r): "0" (a), "w" (b), "w" (c):); + return r; +#endif + return a ^ b ^ c; +} + #define CLIB_HAVE_VEC128_MSB_MASK #define CLIB_HAVE_VEC128_UNALIGNED_LOAD_STORE -- cgit 1.2.3-korg