From dc812d9a71f2f5105e4aaba50fd98ea3b0b50a9b Mon Sep 17 00:00:00 2001 From: Benoît Ganne Date: Mon, 16 Dec 2019 10:42:25 +0100 Subject: rdma: introduce direct verb for Cx4/5 tx MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Direct Verb allows for direct access to NIC HW rx/tx rings. This patch introduce TX direct verb support for Mellanox ConnectX-4/5 adapters. 'dv' mode must be explicitely selected at interface creation to benefit from this. Type: feature Change-Id: If830ba9f33db73299acdbddc68b5c09eaf6add98 Signed-off-by: Benoît Ganne --- src/vppinfra/clib.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'src/vppinfra') diff --git a/src/vppinfra/clib.h b/src/vppinfra/clib.h index 8aec1f16beb..dac41adb165 100644 --- a/src/vppinfra/clib.h +++ b/src/vppinfra/clib.h @@ -111,6 +111,14 @@ #define PREDICT_FALSE(x) __builtin_expect((x),0) #define PREDICT_TRUE(x) __builtin_expect((x),1) +/* + * Compiler barrier + * prevent compiler to reorder memory access accross this boundary + * prevent compiler to cache values in register (force reload) + * Not to be confused with CPU memory barrier below + */ +#define CLIB_COMPILER_BARRIER() asm volatile ("":::"memory") + /* Full memory barrier (read and write). */ #define CLIB_MEMORY_BARRIER() __sync_synchronize () -- cgit 1.2.3-korg