From 30230dd7f854e77008b257c8be1de648e473338e Mon Sep 17 00:00:00 2001 From: Damjan Marion Date: Thu, 24 Nov 2016 22:20:05 +0100 Subject: l2: fix latency issue casued by unnecesary read of previous cacheline In majority of cases ethernet header sits at the beggining of cacheline. Reading (dst_mac - 2) into 64 bit register is much more expensive than doing simple bitwise shift, specially if previous cacheline is not prefetched. Change-Id: I35e53eae735098fb917a87c307e60a87e76e460f Signed-off-by: Damjan Marion --- vnet/vnet/l2/l2_fib.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'vnet') diff --git a/vnet/vnet/l2/l2_fib.h b/vnet/vnet/l2/l2_fib.h index 8e7a52e4d02..63f394cfd44 100644 --- a/vnet/vnet/l2/l2_fib.h +++ b/vnet/vnet/l2/l2_fib.h @@ -105,7 +105,7 @@ l2fib_make_key (u8 * mac_address, u16 bd_index) * Create the in-register key as F:E:D:C:B:A:H:L * In memory the key is L:H:A:B:C:D:E:F */ - temp = *((u64 *) (mac_address - 2)); + temp = *((u64 *) (mac_address)) << 16; temp = (temp & ~0xffff) | (u64) (bd_index); #else /* -- cgit 1.2.3-korg