/* * Copyright (c) 2018 Cisco and/or its affiliates. * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef __included_vmnet_vmnet_h__ #define __included_vmnet_vmnet_h__ #define foreach_vmxnet3_tx_func_error \ _(ERROR_PACKETS, "error packets") \ _(LINK_DOWN, "link down") \ _(NO_FREE_SLOTS, "no free tx slots") typedef enum { #define _(f,s) VMXNET3_TX_ERROR_##f, foreach_vmxnet3_tx_func_error #undef _ VMXNET3_TX_N_ERROR, } vmxnet3_tx_func_error_t; #define foreach_vmxnet3_rxmode_flags \ _(0, UCAST, "unicast") \ _(1, MCAST, "multicast") \ _(2, BCAST, "broadcast") \ _(3, ALL_MULTI, "all multicast") \ _(4, PROMISC, "promiscuous") enum { #define _(a, b, c) VMXNET3_RXMODE_##b = (1 << a), foreach_vmxnet3_rxmode_flags #undef _ }; #define foreach_vmxnet3_show_entry \ _(RX_COMP, "rx comp") \ _(RX_DESC0, "rx desc 0") \ _(RX_DESC1, "rx desc 1") \ _(TX_COMP, "tx comp") \ _(TX_DESC, "tx desc") enum { #define _(a, b) VMXNET3_SHOW_##a, foreach_vmxnet3_show_entry #undef _ }; #define foreach_vmxnet3_feature_flags \ _(0, RXCSUM, "rx checksum") \ _(1, RSS, "RSS") \ _(2, RXVLAN, "rx VLAN") \ _(3, LRO, "LRO") enum { #define _(a, b, c) VMXNET3_F_##b = (1 << a), foreach_vmxnet3_feature_flags #undef _ }; #define foreach_vmxnet3_rss_hash_type \ _(0, IPV4, "ipv4") \ _(1, TCP_IPV4, "tcp ipv4") \ _(2, IPV6, "ipv6") \ _(3, TCP_IPV6, "tcp ipv6") enum { #define _(a, b, c) VMXNET3_RSS_HASH_TYPE_##b = (1 << a), foreach_vmxnet3_rss_hash_type #undef _ }; #define VMXNET3_RSS_HASH_FUNC_TOEPLITZ 1 #define VMXNET3_RSS_MAX_KEY_SZ 40 #define VMXNET3_RSS_MAX_IND_TABLE_SZ 128 #define VMXNET3_TXQ_MAX 8 #define VMXNET3_RXQ_MAX 16 #define VMXNET3_TX_START(vd) ((vd)->queues) #define VMXNET3_RX_START(vd) \ ((vd)->queues + (vd)->num_tx_queues * sizeof (vmxnet3_tx_queue)) /* BAR 0 */ #define VMXNET3_REG_IMR 0x0000 /* Interrupt Mask Register */ #define VMXNET3_REG_TXPROD 0x0600 /* Tx Producer Index */ #define VMXNET3_REG_RXPROD 0x0800 /* Rx Producer Index for ring 1 */ #define VMXNET3_REG_RXPROD2 0x0A00 /* Rx Producer Index for ring 2 */ /* BAR 1 */ #define VMXNET3_REG_VRRS 0x0000 /* VMXNET3 Revision Report Selection */ #define VMXNET3_REG_UVRS 0x0008 /* UPT Version Report Selection */ #define VMXNET3_REG_DSAL 0x0010 /* Driver Shared Address Low */ #define VMXNET3_REG_DSAH 0x0018 /* Driver Shared Address High */ #define VMXNET3_REG_CMD 0x0020 /* Command */ #define VMXNET3_REG_MACL 0x0028 /* MAC Address Low */ #define VMXNET3_REG_MACH 0x0030 /* MAC Address High */ #define VMXNET3_REG_ICR 0x0038 /* Interrupt Cause Register */ #define VMXNET3_REG_ECR 0x0040 /* Event Cause Register */ #define VMXNET3_VLAN_LEN 4 #define VMXNET3_FCS_LEN 4 #define VMXNET3_MTU (1514 + VMXNET3_VLAN_LEN + VMXNET3_FCS_LEN) #define VMXNET3_RXF_BTYPE (1 << 14) /* rx body buffer type */ #define VMXNET3_RXF_GEN (1 << 31) /* rx generation */ #define VMXNET3_RXCF_CKSUM_MASK (0xFFFF) /* rx checksum mask */ #define VMXNET3_RXCF_TUC (1 << 16) /* rx udp/tcp checksum correct */ #define VMXNET3_RXCF_UDP (1 << 17) /* rx udp packet */ #define VMXNET3_RXCF_TCP (1 << 18) /* rx tcp packet */ #define VMXNET3_RXCF_IPC (1 << 19) /* rx ip checksum correct */ #define VMXNET3_RXCF_IP6 (1 << 20) /* rx ip6 packet */ #define VMXNET3_RXCF_IP4 (1 << 21) /* rx ip4 packet */ #define VMXNET3_RXCF_CT (0x7F << 24) /* rx completion type 24-30, 7 bits */ #define VMXNET3_RXCF_GEN (1 << 31) /* rx completion generation */ #define VMXNET3_RXC_INDEX (0xFFF) /* rx completion index mask */ #define foreach_vmxnet3_offload \ _(0, NONE, "none") \ _(2, CSUM, "checksum") \ _(3, TSO, "tso") enum { #define _(a, b, c) VMXNET3_OM_##b = (a), foreach_vmxnet3_offload #undef _ }; /* tx desc flag 0 */ #define VMXNET3_TXF_GEN (1 << 14) /* tx generation */ /* tx desc flag 1 */ #define VMXNET3_TXF_OM(x) ((x) << 10) /* tx offload mode */ #define VMXNET3_TXF_MSSCOF(x) ((x) << 18) /* tx MSS checksum offset, flags */ #define VMXNET3_TXF_EOP (1 << 12) /* tx end of packet */ #define VMXNET3_TXF_CQ (1 << 13) /* tx completion request */ /* tx completion flag */ #define VMXNET3_TXCF_GEN (1 << 31) /* tx completion generation */ #define VMXNET3_TXC_INDEX (0xFFF) /* tx completion index mask */ #define VMXNET3_RX_RING_SIZE 2 #define VMXNET3_INPUT_REFILL_THRESHOLD 32 #define VMXNET3_NUM_TX_DESC 1024 #define VMXNET3_NUM_TX_COMP VMXNET3_NUM_TX_DESC #define VMXNET3_NUM_RX_DESC 1024 #define VMXNET3_NUM_RX_COMP VMXNET3_NUM_RX_DESC #define VMXNET3_VERSION_MAGIC 0x69505845 #define VMXNET3_SHARED_MAGIC 0xbabefee1 #define VMXNET3_VERSION_SELECT 1 #define VMXNET3_UPT_VERSION_SELECT 1 #define VMXNET3_MAX_INTRS 25 #define VMXNET3_IC_DISABLE_ALL 0x1 #define VMXNET3_GOS_BITS_32 (1 << 0) #define VMXNET3_GOS_BITS_64 (2 << 0) #define VMXNET3_GOS_TYPE_LINUX (1 << 2) #define VMXNET3_RXCL_LEN_MASK (0x3FFF) // 14 bits #define VMXNET3_RXCL_ERROR (1 << 14) #define VMXNET3_RXCI_EOP (1 << 14) /* end of packet */ #define VMXNET3_RXCI_SOP (1 << 15) /* start of packet */ #define VMXNET3_RXCI_CNC (1 << 30) /* Checksum not calculated */ #define VMXNET3_RXCOMP_TYPE (3 << 24) /* RX completion descriptor */ #define VMXNET3_RXCOMP_TYPE_LRO (4 << 24) /* RX completion descriptor for LRO */ #define VMXNET3_RXECF_MSS_MASK (0xFFFF) // 16 bits #define foreach_vmxnet3_device_
from trex_stl_lib.api import *

class STLS1(object):

    def create_stream (self):
        base_pkt = Ether()/IP(src="2.2.0.1")/UDP(sport=12)

        pad = Padding()
        if len(base_pkt) < 64:
            pad_len = 64 - len(base_pkt)
            pad.load = '\x00' * pad_len

        vm = STLVM()

        vm.tuple_var(name="tuple", ip_min="173.16.1.3", ip_max="173.16.1.102", port_min=1025, port_max=1124, limit_flows = 100000)

        vm.write(fv_name="tuple.ip", pkt_offset="IP.dst")
        vm.fix_chksum()

        vm.write(fv_name="tuple.port", pkt_offset="UDP.dport")

        pkt = STLPktBuilder(pkt=base_pkt/pad, vm=vm)

        return STLStream(packet=pkt, mode=STLTXCont())

    def get_streams (self, direction = 0, **kwargs):
        return [self.create_stream()]


# dynamic load - used for trex console or simulator
def register():
    return STLS1()
->rx_desc[1][ring->produce]; rxd->address = vlib_buffer_get_pa (vm, b); rxd->flags = ring->gen | vlib_buffer_get_default_data_size (vm) | VMXNET3_RXF_BTYPE; vmxnet3_rx_ring_advance_produce (rxq, ring); ring->fill++; n_alloc--; } rx = VMXNET3_RX_START (vd); if (PREDICT_FALSE (rx->ctrl.update_prod)) vmxnet3_reg_write_inline (vd, 0, VMXNET3_REG_RXPROD2, ring->produce); return 0; } #endif /* __included_vmnet_vmnet_h__ */ /* * fd.io coding-style-patch-verification: ON * * Local Variables: * eval: (c-set-style "gnu") * End: */