/* * Copyright (c) 2016 Cisco and/or its affiliates. * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ /* * pci.h: PCI definitions. * * Copyright (c) 2008 Eliot Dresselhaus * * Permission is hereby granted, free of charge, to any person obtaining * a copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sublicense, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice shall be * included in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef included_vlib_pci_config_h #define included_vlib_pci_config_h #include #include typedef enum { PCI_CLASS_NOT_DEFINED = 0x0000, PCI_CLASS_NOT_DEFINED_VGA = 0x0001, PCI_CLASS_STORAGE_SCSI = 0x0100, PCI_CLASS_STORAGE_IDE = 0x0101, PCI_CLASS_STORAGE_FLOPPY = 0x0102, PCI_CLASS_STORAGE_IPI = 0x0103, PCI_CLASS_STORAGE_RAID = 0x0104, PCI_CLASS_STORAGE_OTHER = 0x0180, PCI_CLASS_STORAGE = 0x0100, PCI_CLASS_NETWORK_ETHERNET = 0x0200, PCI_CLASS_NETWORK_TOKEN_RING = 0x0201, PCI_CLASS_NETWORK_FDDI = 0x0202, PCI_CLASS_NETWORK_ATM = 0x0203, PCI_CLASS_NETWORK_OTHER = 0x0280, PCI_CLASS_NETWORK = 0x0200, PCI_CLASS_DISPLAY_VGA = 0x0300, PCI_CLASS_DISPLAY_XGA = 0x0301, PCI_CLASS_DISPLAY_3D = 0x0302, PCI_CLASS_DISPLAY_OTHER = 0x0380, PCI_CLASS_DISPLAY = 0x0300, PCI_CLASS_MULTIMEDIA_VIDEO = 0x0400, PCI_CLASS_MULTIMEDIA_AUDIO = 0x0401, PCI_CLASS_MULTIMEDIA_PHONE = 0x0402, PCI_CLASS_MULTIMEDIA_OTHER = 0x0480, PCI_CLASS_MULTIMEDIA = 0x0400, PCI_CLASS_MEMORY_RAM = 0x0500, PCI_CLASS_MEMORY_FLASH = 0x0501, PCI_CLASS_MEMORY_OTHER = 0x0580, PCI_CLASS_MEMORY = 0x0500, PCI_CLASS_BRIDGE_HOST = 0x0600, PCI_CLASS_BRIDGE_ISA = 0x0601, PCI_CLASS_BRIDGE_EISA = 0x0602, PCI_CLASS_BRIDGE_MC = 0x0603, PCI_CLASS_BRIDGE_PCI = 0x0604, PCI_CLASS_BRIDGE_PCMCIA = 0x0605, PCI_CLASS_BRIDGE_NUBUS = 0x0606, PCI_CLASS_BRIDGE_CARDBUS = 0x0607, PCI_CLASS_BRIDGE_RACEWAY = 0x0608, PCI_CLASS_BRIDGE_OTHER = 0x0680, PCI_CLASS_BRIDGE = 0x0600, PCI_CLASS_COMMUNICATION_SERIAL = 0x0700, PCI_CLASS_COMMUNICATION_PARALLEL = 0x0701, PCI_CLASS_COMMUNICATION_MULTISERIAL = 0x0702, PCI_CLASS_COMMUNICATION_MODEM = 0x0703, PCI_CLASS_COMMUNICATION_OTHER = 0x0780, PCI_CLASS_COMMUNICATION = 0x0700, PCI_CLASS_SYSTEM_PIC = 0x0800, PCI_CLASS_SYSTEM_DMA = 0x0801, PCI_CLASS_SYSTEM_TIMER = 0x0802, PCI_CLASS_SYSTEM_RTC = 0x0803, PCI_CLASS_SYSTEM_PCI_HOTPLUG = 0x0804, PCI_CLASS_SYSTEM_OTHER = 0x0880, PCI_CLASS_SYSTEM = 0x0800, PCI_CLASS_INPUT_KEYBOARD = 0x0900, PCI_CLASS_INPUT_PEN = 0x0901, PCI_CLASS_INPUT_MOUSE = 0x0902, PCI_CLASS_INPUT_SCANNER = 0x0903, PCI_CLASS_INPUT_GAMEPORT = 0x0904, PCI_CLASS_INPUT_OTHER = 0x0980, PCI_CLASS_INPUT = 0x0900, PCI_CLASS_DOCKING_GENERIC = 0x0a00, PCI_CLASS_DOCKING_OTHER = 0x0a80, PCI_CLASS_DOCKING = 0x0a00, PCI_CLASS_PROCESSOR_386 = 0x0b00, PCI_CLASS_PROCESSOR_486 = 0x0b01, PCI_CLASS_PROCESSOR_PENTIUM = 0x0b02, PCI_CLASS_PROCESSOR_ALPHA = 0x0b10, PCI_CLASS_PROCESSOR_POWERPC = 0x0b20, PCI_CLASS_PROCESSOR_MIPS = 0x0b30, PCI_CLASS_PROCESSOR_CO = 0x0b40, PCI_CLASS_PROCESSOR = 0x0b00, PCI_CLASS_SERIAL_FIREWIRE = 0x0c00, PCI_CLASS_SERIAL_ACCESS = 0x0c01, PCI_CLASS_SERIAL_SSA = 0x0c02, PCI_CLASS_SERIAL_USB = 0x0c03, PCI_CLASS_SERIAL_FIBER = 0x0c04, PCI_CLASS_SERIAL_SMBUS = 0x0c05, PCI_CLASS_SERIAL = 0x0c00, PCI_CLASS_INTELLIGENT_I2O = 0x0e00, PCI_CLASS_INTELLIGENT = 0x0e00, PCI_CLASS_SATELLITE_TV = 0x0f00, PCI_CLASS_SATELLITE_AUDIO = 0x0f01, PCI_CLASS_SATELLITE_VOICE = 0x0f03, PCI_CLASS_SATELLITE_DATA = 0x0f04, PCI_CLASS_SATELLITE = 0x0f00, PCI_CLASS_CRYPT_NETWORK = 0x1000, PCI_CLASS_CRYPT_ENTERTAINMENT = 0x1001, PCI_CLASS_CRYPT_OTHER = 0x1080, PCI_CLASS_CRYPT = 0x1000, PCI_CLASS_SP_DPIO = 0x1100, PCI_CLASS_SP_OTHER = 0x1180, PCI_CLASS_SP = 0x1100, } pci_device_class_t; static inline pci_device_class_t pci_device_class_base (pci_device_class_t c) { return c & ~0xff; } /* * 0x1000 is the legacy device-id value * 0x1041 is (0x1040 + 1), 1 being the Virtio Device ID */ #define VIRTIO_PCI_LEGACY_DEVICEID_NET 0x1000 #define VIRTIO_PCI_MODERN_DEVICEID_NET 0x1041 /* * Under PCI, each device has 256 bytes of configuration address space, * of which the first 64 bytes are standardized as follows: */ typedef struct { u16 vendor_id; u16 device_id; u16 command; #define PCI_COMMAND_IO (1 << 0) /* Enable response in I/O space */ #define PCI_COMMAND_MEMORY (1 << 1) /* Enable response in Memory space */ #define PCI_COMMAND_BUS_MASTER (1 << 2) /* Enable bus mastering */ #define PCI_COMMAND_SPECIAL (1 << 3) /* Enable response to special cycles */ #define PCI_COMMAND_WRITE_INVALIDATE (1 << 4) /* Use memory write and invalidate */ #define PCI_COMMAND_VGA_PALETTE_SNOOP (1 << 5) #define PCI_COMMAND_PARITY (1 << 6) #define PCI_COMMAND_WAIT (1 << 7) /* Enable address/data stepping */ #define PCI_COMMAND_SERR (1 << 8) /* Enable SERR */ #define PCI_COMMAND_BACK_TO_BACK_WRITE (1 << 9) #define PCI_COMMAND_INTX_DISABLE (1 << 10) /* INTx Emulation Disable */ u16 status; #define PCI_STATUS_INTX_PENDING (1 << 3) #define PCI_STATUS_CAPABILITY_LIST (1 << 4) #define PCI_STATUS_66MHZ (1 << 5) /* Support 66 Mhz PCI 2.1 bus */ #define PCI_STATUS_UDF (1 << 6) /* Support User Definable Features (obsolete) */ #define PCI_STATUS_BACK_TO_BACK_WRITE (1 << 7) /* Accept fast-back to back */ #define PCI_STATUS_PARITY_ERROR (1 << 8) /* Detected parity error */ #define PCI_STATUS_DEVSEL_GET(x) ((x >> 9) & 3) /* DEVSEL timing */ #define PCI_STATUS_DEVSEL_FAST (0 << 9) #define PCI_STATUS_DEVSEL_MEDIUM (1 << 9) #define PCI_STATUS_DEVSEL_SLOW (2 << 9) #define PCI_STATUS_SIG_TARGET_ABORT (1 << 11) /* Set on target abort */ #define PCI_STATUS_REC_TARGET_ABORT (1 << 12) /* Master ack of " */ #define PCI_STATUS_REC_MASTER_ABORT (1 << 13) /* Set on master abort */ #define PCI_STATUS_SIG_SYSTEM_ERROR (1 << 14) /* Set when we drive SERR */ #define PCI_STATUS_DETECTED_PARITY_ERROR (1 << 15) u8 revision_id; u8 programming_interface_class; /* Reg. Level Programming Interface */ pci_device_class_t device_class:16; u8 cache_size; u8 latency_timer; u8 header_type; #define PCI_HEADER_TYPE_NORMAL 0 #define PCI_HEADER_TYPE_BRIDGE 1 #define PCI_HEADER_TYPE_CARDBUS 2 u8 bist; #define PCI_BIST_CODE_MASK 0x0f /* Return result */ #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */ #define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */ } pci_config_header_t; /* Byte swap config header. */ always_inline void pci_config_header_little_to_host (pci_config_header_t * r) { if (!CLIB_ARCH_IS_BIG_ENDIAN) return; #define _(f,t) r->f = clib_byte_swap_##t (r->f) _(vendor_id, u16); _(device_id, u16); _(command, u16); _(status, u16); _(device_class, u16); #undef _ } /* Header type 0 (normal devices) */ typedef struct { pci_config_header_t header; /* * Base addresses specify locations in memory or I/O space. * Decoded size can be determined by writing a value of * 0xffffffff to the register, and reading it back. Only * 1 bits are decoded. */ u32 base_address[6]; u16 cardbus_cis; u16 subsystem_vendor_id; u16 subsystem_id; u32 rom_address; #define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */ #define PCI_ROM_ADDRESS_ENABLE 0x01 #define PCI_ROM_ADDRESS_MASK (~0x7ffUL) u8 first_capability_offset; CLIB_PAD_FROM_TO (0x35, 0x3c); u8 interrupt_line; u8 interrupt_pin; u8 min_grant; u8 max_latency; u8 capability_data[0]; } pci_config_type0_regs_t; always_inline void pci_config_type0_little_to_host (pci_config_type0_regs_t * r) { int i; if (!CLIB_ARCH_IS_BIG_ENDIAN) return; pci_config_header_little_to_host (&r->header); #define _(f,t) r->f = clib_byte_swap_##t (r->f) for (i = 0; i < ARRAY_LEN (r->base_address); i++) _(base_address[i], u32); _(cardbus_cis, u16); _(subsystem_vendor_id, u16); _(subsystem_id, u16); _(rom_address, u32); #undef _ } /* Header type 1 (PCI-to-PCI bridges) */ typedef struct { pci_config_header_t header; u32 base_address[2]; /* Primary/secondary bus number. */ u8 primary_bus; u8 secondary_bus; /* Highest bus number behind the bridge */ u8 subordinate_bus; u8 secondary_bus_latency_timer; /* I/O range behind bridge. */ u8 io_base, io_limit; /* Secondary status register, only bit 14 used */ u16 secondary_status; /* Memory range behind bridge in units of 64k bytes. */ u16 memory_base, memory_limit; #define PCI_MEMORY_RANGE_TYPE_MASK 0x0fUL #define PCI_MEMORY_RANGE_MASK (~0x0fUL) u16 prefetchable_memory_base, prefetchable_memory_limit; #define PCI_PREF_RANGE_TYPE_MASK 0x0fUL #define PCI_PREF_RANGE_TYPE_32 0x00 #define PCI_PREF_RANGE_TYPE_64 0x01 #define PCI_PREF_RANGE_MASK (~0x0fUL) u32 prefetchable_memory_base_upper_32bits; u32 prefetchable_memory_limit_upper_32bits; u16 io_base_upper_16bits; u16 io_limit_upper_16bits; /* Same as for type 0. */ u8 capability_list_offset; CLIB_PAD_FROM_TO (0x35, 0x37); u32 rom_address; CLIB_PAD_FROM_TO (0x3c, 0x3e); u16 bridge_control; #define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */ #define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */ #define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */ #define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */ #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */ #define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */ #define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */ u8 capability_data[0]; } pci_config_type1_regs_t; always_inline void pci_config_type1_little_to_host (pci_config_type1_regs_t * r) { int i; if (!CLIB_ARCH_IS_BIG_ENDIAN) return; pci_config_header_little_to_host (&r->header); #define _(f,t) r->f = clib_byte_swap_##t (r->f) for (i = 0; i < ARRAY_LEN (r->base_address); i++) _(base_address[i], u32); _(secondary_status, u16); _(memory_base, u16); _(memory_limit, u16); _(prefetchable_memory_base, u16); _(prefetchable_memory_limit, u16); _(prefetchable_memory_base_upper_32bits, u32); _(prefetchable_memory_limit_upper_32bits, u32); _(io_base_upper_16bits, u16); _(io_limit_upper_16bits, u16); _(rom_address, u32); _(bridge_control, u16); #undef _ } /* Capabilities. */ typedef enum pci_capability_type { /* Power Management */ PCI_CAP_ID_PM = 1, /* Accelerated Graphics Port */ PCI_CAP_ID_AGP = 2, /* Vital Product Data */ PCI_CAP_ID_VPD = 3, /* Slot Identification */ PCI_CAP_ID_SLOTID = 4, /* Message Signalled Interrupts */ PCI_CAP_ID_MSI = 5, /* CompactPCI HotSwap */ PCI_CAP_ID_CHSWP = 6, /* PCI-X */ PCI_CAP_ID_PCIX = 7, /* Hypertransport. */ PCI_CAP_ID_HYPERTRANSPORT = 8, /* PCI Standard Hot-Plug Controller */ PCI_CAP_ID_SHPC = 0xc, /* PCI Express */ PCI_CAP_ID_PCIE = 0x10, /* MSI-X */ PCI_CAP_ID_MSIX = 0x11, } pci_capability_type_t; /* Common header for capabilities. */ typedef struct { enum pci_capability_type type:8; u8 next_offset; } __clib_packed pci_capability_regs_t; always_inline void * pci_config_find_capability (pci_config_type0_regs_t * t, int cap_type) { pci_capability_regs_t *c; u32 next_offset; u32 ttl = 48; if (!(t->header.status & PCI_STATUS_CAPABILITY_LIST)) return 0; next_offset = t->first_capability_offset; while (ttl-- && next_offset >= 0x40) { c = (void *) t + (next_offset & ~3); if ((u8) c->type == 0xff) break; if (c->type == cap_type) return c; next_offset = c->next_offset; } return 0; } /* Power Management Registers */ typedef struct { pci_capability_regs_t header; u16 capabilities; #define PCI_PM_CAP_VER_MASK 0x0007 /* Version */ #define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */ #define PCI_PM_CAP_RESERVED 0x0010 /* Reserved field */ #define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */ #define PCI_PM_CAP_AUX_POWER 0x01C0 /* Auxilliary power support mask */ #define PCI_PM_CAP_D1 0x0200 /* D1 power state support */ #define PCI_PM_CAP_D2 0x0400 /* D2 power state support */ #define PCI_PM_CAP_PME 0x0800 /* PME pin supported */ #define PCI_PM_CAP_PME_MASK 0xF800 /* PME Mask of all supported states */ #define PCI_PM_CAP_PME_D0 0x0800 /* PME# from D0 */ #define PCI_PM_CAP_PME_D1 0x1000 /* PME# from D1 */ #define PCI_PM_CAP_PME_D2 0x2000 /* PME# from D2 */ #define PCI_PM_CAP_PME_D3 0x4000 /* PME# from D3 (hot) */ #define PCI_PM_CAP_PME_D3cold 0x8000 /* PME# from D3 (cold) */ u16 control; #define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */ #define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */ #define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */ #define PCI_PM_CTRL_DATA_SCALE_MASK 0x
/*
 *------------------------------------------------------------------
 * Copyright (c) 2018 Cisco and/or its affiliates.
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at:
 *
 *     http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 *------------------------------------------------------------------
 */

#include <vnet/qos/qos_egress_map.h>
#include <vnet/qos/qos_mark.h>

/**
 * Pool from which to allocate table
 */
qos_egress_map_t *qem_pool;

/**
 * DB to map user table-IDs to internal table indicies.
 */
uword *qem_db;

index_t
qos_egress_map_find (qos_egress_map_id_t mid)
{
  uword *p = NULL;

  p = hash_get (qem_db, mid);

  if (NULL != p)
    return p[0];

  return (INDEX_INVALID);
}

qos_egress_map_id_t
qos_egress_map_get_id (index_t qemi)
{
  qos_egress_map_id_t qid;
  index_t qmi;

  /* *INDENT-OFF* */
  hash_foreach(qid, qmi, qem_db,
  ({
    if (qmi == qemi)
      return (qid);
  }));
  /* *INDENT-OFF* */

  return (~0);
}

qos_egress_map_t *
qos_egress_map_find_i (qos_egress_map_id_t mid)
{
  index_t qemi;

  qemi = qos_egress_map_find (mid);

  if (INDEX_INVALID != qemi)
    {
      return (pool_elt_at_index (qem_pool, qemi));
    }

  return (NULL);
}

static