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-rw-r--r--docs/report/vpp_performance_tests/packet_latency_graphs/ip6.rst4
1 files changed, 3 insertions, 1 deletions
diff --git a/docs/report/vpp_performance_tests/packet_latency_graphs/ip6.rst b/docs/report/vpp_performance_tests/packet_latency_graphs/ip6.rst
index 3719bebfe7..a3be557ac7 100644
--- a/docs/report/vpp_performance_tests/packet_latency_graphs/ip6.rst
+++ b/docs/report/vpp_performance_tests/packet_latency_graphs/ip6.rst
@@ -13,7 +13,7 @@ VPP worker thread(s), a.k.a. VPP data plane thread(s), and their
physical CPU core(s) placement.
CSIT source code for the test cases used for plots can be found in
-`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/ip6?h=rls1908>`_.
+`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/ip6?h=rls2001>`_.
.. toctree::
@@ -21,5 +21,7 @@ CSIT source code for the test cases used for plots can be found in
ip6-2n-skx-x710
ip6-3n-skx-xxv710
ip6-3n-skx-x710
+ ip6-2n-clx-xxv710
+ ip6-2n-clx-x710
ip6-3n-hsw-xl710
ip6-3n-tsh-x520