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-rw-r--r--docs/report/vpp_performance_tests/throughput_speedup_multi_core/l2.rst6
1 files changed, 3 insertions, 3 deletions
diff --git a/docs/report/vpp_performance_tests/throughput_speedup_multi_core/l2.rst b/docs/report/vpp_performance_tests/throughput_speedup_multi_core/l2.rst
index ed4a287e01..612c1aeb9f 100644
--- a/docs/report/vpp_performance_tests/throughput_speedup_multi_core/l2.rst
+++ b/docs/report/vpp_performance_tests/throughput_speedup_multi_core/l2.rst
@@ -15,10 +15,12 @@ L2 Ethernet switching, including NDR throughput (zero packet loss) and
PDR throughput (<0.5% packet loss).
CSIT source code for the test cases used for plots can be found in
-`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/l2?h=rls2110>`_.
+`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/l2?h=rls2202>`_.
.. toctree::
+ l2-2n-icx-xxv710
+ l2-3n-icx-xxv710
l2-2n-skx-xxv710
l2-2n-skx-x710
l2-3n-skx-xxv710
@@ -26,8 +28,6 @@ CSIT source code for the test cases used for plots can be found in
l2-2n-clx-xxv710
l2-2n-clx-x710
l2-2n-clx-cx556a
- l2-2n-icx-xxv710
- l2-3n-icx-xxv710
l2-2n-zn2-xxv710
l2-2n-zn2-x710
l2-2n-zn2-cx556a