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| author |   Hanoh Haim <hhaim@cisco.com> | 2016-11-28 20:06:18 +0200 |
|---|---|---|
| committer | Hanoh Haim <hhaim@cisco.com> | 2016-11-28 21:16:09 +0200 |
| commit | 1a534a8806dffe730a966cbb77c5377efab2f514 (patch) | |
| tree | 3439eb6b1092b34d80ab304849fe19142a3f1e83 | |
| parent | f143a31a6e58dcc7d520a6d9f8a40bead32b52ef (diff) | |
cisco VIC - skip test with 9K packet len due to trex-282
Signed-off-by: Hanoh Haim <hhaim@cisco.com>
3 files changed, 20 insertions, 48 deletions
diff --git a/scripts/automation/regression/setups/trex11/benchmark.yaml b/scripts/automation/regression/setups/trex11/benchmark.yaml index ca5ea45e..eabbbb62 100644 --- a/scripts/automation/regression/setups/trex11/benchmark.yaml +++ b/scripts/automation/regression/setups/trex11/benchmark.yaml @@ -178,56 +178,9 @@ test_CPU_benchmark: # cpu_util : 1 # bw_per_core : 1 -test_performance_vm_single_cpu: - cfg: - mult : "90%" - mpps_per_core_golden : - min: 9.6 - max: 13.3 - - -test_performance_vm_single_cpu_cached: - cfg: - mult : "10%" - mpps_per_core_golden : - min: 16.0 - max: 25.0 - - - -test_performance_syn_attack_single_cpu: - cfg: - mult : "90%" - mpps_per_core_golden : - min: 9.0 - max: 14.0 - -test_performance_vm_multi_cpus: - cfg: - core_count : 7 - mult : "90%" - mpps_per_core_golden : - min: 8.5 - max: 12.0 - - -test_performance_vm_multi_cpus_cached: - cfg: - core_count : 7 - mult : "35%" - mpps_per_core_golden : - min: 9.0 - max: 15.0 - -test_performance_syn_attack_multi_cpus: - cfg: - core_count : 7 - mult : "90%" - mpps_per_core_golden : - min: 8.0 - max: 16.0 test_all_profiles : mult : "5%" + skip : ['udp_rand_len_9k.py','udp_inc_len_9k.py'] # due to VIC 9K defect trex-282 diff --git a/scripts/automation/regression/stateless_tests/stl_client_test.py b/scripts/automation/regression/stateless_tests/stl_client_test.py index acf5dc61..73dac734 100644 --- a/scripts/automation/regression/stateless_tests/stl_client_test.py +++ b/scripts/automation/regression/stateless_tests/stl_client_test.py @@ -241,6 +241,7 @@ class STLClient_Test(CStlGeneral_Test): return default_mult = self.get_benchmark_param('mult',default="30%") + skip_tests = self.get_benchmark_param('skip',default=[]) try: print("\n"); @@ -248,6 +249,17 @@ class STLClient_Test(CStlGeneral_Test): for profile in self.profiles: + skip=False + if skip_tests: + for skip_test in skip_tests: + if skip_test in profile: + skip=True; + break; + if skip: + print("skipping testing profile due to config file {0}...\n".format(profile)) + continue; + + print("now testing profile {0}...\n".format(profile)) p1 = STLProfile.load(profile, port_id = self.tx_port) diff --git a/scripts/automation/regression/stateless_tests/stl_rx_test.py b/scripts/automation/regression/stateless_tests/stl_rx_test.py index d28fca54..4dad712f 100644 --- a/scripts/automation/regression/stateless_tests/stl_rx_test.py +++ b/scripts/automation/regression/stateless_tests/stl_rx_test.py @@ -61,6 +61,13 @@ class STLRX_Test(CStlGeneral_Test): 'latency_9k_max_latency': 250, }, + 'rte_enic_pmd': { + 'rate_percent': 1, + 'total_pkts': 50, + 'rate_latency': 1, + 'latency_9k_enable': False, + }, + } |