diff options
| author |   imarom <imarom@cisco.com> | 2016-08-16 10:42:31 +0300 |
|---|---|---|
| committer | imarom <imarom@cisco.com> | 2016-08-16 10:47:54 +0300 |
| commit | c5a9a3c77658f04e9dac066443e3bf6aa7d32b67 (patch) | |
| tree | 79c4ec77d4c5a1a40295f385cdb068b5991a8dea | |
| parent | 7dbdcb10b440eb7c84aacec463da352a1ea6f7d4 (diff) | |
simulator breakage fix
4 files changed, 6 insertions, 4 deletions
diff --git a/scripts/automation/trex_control_plane/stl/console/trex_tui.py b/scripts/automation/trex_control_plane/stl/console/trex_tui.py index 0a3d1a6d..6dff0a6f 100644 --- a/scripts/automation/trex_control_plane/stl/console/trex_tui.py +++ b/scripts/automation/trex_control_plane/stl/console/trex_tui.py @@ -600,8 +600,6 @@ class TrexTUI(): if status == AsyncKeys.STATUS_NONE: time.sleep(0.001) - if self.tui_global_lock.locked(): - self.x += 1 with self.tui_global_lock: self.handle_state_machine() diff --git a/scripts/automation/trex_control_plane/stl/trex_stl_lib/trex_stl_port.py b/scripts/automation/trex_control_plane/stl/trex_stl_lib/trex_stl_port.py index 2074080a..890ce7de 100644 --- a/scripts/automation/trex_control_plane/stl/trex_stl_lib/trex_stl_port.py +++ b/scripts/automation/trex_control_plane/stl/trex_stl_lib/trex_stl_port.py @@ -710,7 +710,7 @@ class Port(object): ('L2 len', len(obj['pkt']) + 4), ('mode', obj['mode']), ('rate', obj['rate']), - ('next_stream', obj['next_id']) + ('next_stream', obj['next_id'] if not '-1' else 'None') ]) return {"streams" : OrderedDict(sorted(data.items())) } diff --git a/scripts/automation/trex_control_plane/stl/trex_stl_lib/trex_stl_sim.py b/scripts/automation/trex_control_plane/stl/trex_stl_lib/trex_stl_sim.py index 62724e64..3e63c4e2 100644 --- a/scripts/automation/trex_control_plane/stl/trex_stl_lib/trex_stl_sim.py +++ b/scripts/automation/trex_control_plane/stl/trex_stl_lib/trex_stl_sim.py @@ -40,6 +40,8 @@ class BpSimException(Exception): # stateless simulation class STLSim(object): + MASK_ALL = ((1 << 64) - 1) + def __init__ (self, bp_sim_path, handler = 0, port_id = 0, api_h = "dummy"): self.bp_sim_path = os.path.abspath(bp_sim_path) @@ -61,7 +63,8 @@ class STLSim(object): "force": force, "port_id": self.port_id, "mul": parsing_opts.decode_multiplier(mult), - "duration": duration} + "duration": duration, + "core_mask": self.MASK_ALL} } diff --git a/src/sim/trex_sim_stateless.cpp b/src/sim/trex_sim_stateless.cpp index 20041c2b..6d470704 100644 --- a/src/sim/trex_sim_stateless.cpp +++ b/src/sim/trex_sim_stateless.cpp @@ -246,6 +246,7 @@ void SimStateless::prepare_dataplane() { CGlobalInfo::m_options.m_expected_portd = m_port_count; + CGlobalInfo::m_options.m_run_mode = CParserOption::RUN_MODE_INTERACTIVE; assert(CMsgIns::Ins()->Create(m_dp_core_count)); m_fl.Create(); |