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authorChristophe Fontaine <christophe.fontaine@qosmos.com>2016-05-13 07:07:28 +0000
committerDamjan Marion <damarion@cisco.com>2016-05-17 18:20:10 +0000
commit9341a1f8500b8f6712b5dd671b976ecbf6803c2c (patch)
treefcb6efdbaf036092a4bd831c8ff480e25dcbc9d2
parent862623da6eb3dfb211f5ed03ce063137d3f2242e (diff)
vppinfra - ARM: cycle count 64bits register is only available on ARMv8
Change-Id: I7d622e591020a482af68667f4d1ed2056258d2c8 Signed-off-by: Christophe Fontaine <christophe.fontaine@qosmos.com>
-rw-r--r--vppinfra/vppinfra/time.h11
1 files changed, 9 insertions, 2 deletions
diff --git a/vppinfra/vppinfra/time.h b/vppinfra/vppinfra/time.h
index 29398f3baea..ffafaf70b21 100644
--- a/vppinfra/vppinfra/time.h
+++ b/vppinfra/vppinfra/time.h
@@ -113,13 +113,20 @@ always_inline u64 clib_cpu_time_now (void)
}
#elif defined (__arm__)
-#if defined(__ARM_ARCH_7A__)
-always_inline u64 clib_cpu_time_now (void)
+#if defined(__ARM_ARCH_8A__)
+always_inline u64 clib_cpu_time_now (void) /* We may run arm64 in aarch32 mode, to leverage 64bit counter */
{
u64 tsc;
asm volatile("mrrc p15, 0, %Q0, %R0, c9" : "=r" (tsc));
return tsc;
}
+#elif defined(__ARM_ARCH_7A__)
+always_inline u64 clib_cpu_time_now (void)
+{
+ u32 tsc;
+ asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (tsc));
+ return (u64)tsc;
+}
#else
always_inline u64 clib_cpu_time_now (void)
{