initial version of VSAP

Signed-off-by: Yu Ping <ping.yu@intel.com>
Change-Id: I04d9150f0c7607ba20de9096b452476eff1622fc

1 files changed, 82 insertions, 0 deletions

diff --git a/nginx/src/os/unix/ngx_gcc_atomic_amd64.h b/nginx/src/os/unix/ngx_gcc_atomic_amd64.h
new file mode 100644
index 0000000..159a297
--- /dev/null
+++ b/nginx/src/os/unix/ngx_gcc_atomic_amd64.h
@@ -0,0 +1,82 @@
+
+/*
+ * Copyright (C) Igor Sysoev
+ * Copyright (C) Nginx, Inc.
+ */
+
+
+#if (NGX_SMP)
+#define NGX_SMP_LOCK  "lock;"
+#else
+#define NGX_SMP_LOCK
+#endif
+
+
+/*
+ * "cmpxchgq  r, [m]":
+ *
+ *     if (rax == [m]) {
+ *         zf = 1;
+ *         [m] = r;
+ *     } else {
+ *         zf = 0;
+ *         rax = [m];
+ *     }
+ *
+ *
+ * The "r" is any register, %rax (%r0) - %r16.
+ * The "=a" and "a" are the %rax register.
+ * Although we can return result in any register, we use "a" because it is
+ * used in cmpxchgq anyway.  The result is actually in %al but not in $rax,
+ * however as the code is inlined gcc can test %al as well as %rax.
+ *
+ * The "cc" means that flags were changed.
+ */
+
+static ngx_inline ngx_atomic_uint_t
+ngx_atomic_cmp_set(ngx_atomic_t *lock, ngx_atomic_uint_t old,
+    ngx_atomic_uint_t set)
+{
+    u_char  res;
+
+    __asm__ volatile (
+
+         NGX_SMP_LOCK
+    "    cmpxchgq  %3, %1;   "
+    "    sete      %0;       "
+
+    : "=a" (res) : "m" (*lock), "a" (old), "r" (set) : "cc", "memory");
+
+    return res;
+}
+
+
+/*
+ * "xaddq  r, [m]":
+ *
+ *     temp = [m];
+ *     [m] += r;
+ *     r = temp;
+ *
+ *
+ * The "+r" is any register, %rax (%r0) - %r16.
+ * The "cc" means that flags were changed.
+ */
+
+static ngx_inline ngx_atomic_int_t
+ngx_atomic_fetch_add(ngx_atomic_t *value, ngx_atomic_int_t add)
+{
+    __asm__ volatile (
+
+         NGX_SMP_LOCK
+    "    xaddq  %0, %1;   "
+
+    : "+r" (add) : "m" (*value) : "cc", "memory");
+
+    return add;
+}
+
+
+#define ngx_memory_barrier()    __asm__ volatile ("" ::: "memory")
+
+#define ngx_cpu_pause()         __asm__ ("pause")