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authorChristian Ehrhardt <christian.ehrhardt@canonical.com>2017-05-16 14:51:32 +0200
committerChristian Ehrhardt <christian.ehrhardt@canonical.com>2017-05-16 16:20:45 +0200
commit7595afa4d30097c1177b69257118d8ad89a539be (patch)
tree4bfeadc905c977e45e54a90c42330553b8942e4e /doc/guides/cryptodevs
parentce3d555e43e3795b5d9507fcfc76b7a0a92fd0d6 (diff)
Imported Upstream version 17.05
Change-Id: Id1e419c5a214e4a18739663b91f0f9a549f1fdc6 Signed-off-by: Christian Ehrhardt <christian.ehrhardt@canonical.com>
Diffstat (limited to 'doc/guides/cryptodevs')
-rw-r--r--doc/guides/cryptodevs/aesni_gcm.rst30
-rw-r--r--doc/guides/cryptodevs/aesni_mb.rst45
-rw-r--r--doc/guides/cryptodevs/armv8.rst98
-rw-r--r--doc/guides/cryptodevs/dpaa2_sec.rst232
-rw-r--r--doc/guides/cryptodevs/features/aesni_gcm.ini27
-rw-r--r--doc/guides/cryptodevs/features/aesni_mb.ini41
-rw-r--r--doc/guides/cryptodevs/features/armv8.ini28
-rw-r--r--doc/guides/cryptodevs/features/default.ini70
-rw-r--r--doc/guides/cryptodevs/features/dpaa2_sec.ini34
-rw-r--r--doc/guides/cryptodevs/features/kasumi.ini24
-rw-r--r--doc/guides/cryptodevs/features/null.ini25
-rw-r--r--doc/guides/cryptodevs/features/openssl.ini47
-rw-r--r--doc/guides/cryptodevs/features/qat.ini53
-rw-r--r--doc/guides/cryptodevs/features/snow3g.ini24
-rw-r--r--doc/guides/cryptodevs/features/zuc.ini24
-rw-r--r--doc/guides/cryptodevs/img/scheduler-overview.svg277
-rw-r--r--doc/guides/cryptodevs/index.rst5
-rw-r--r--doc/guides/cryptodevs/kasumi.rst6
-rw-r--r--doc/guides/cryptodevs/null.rst6
-rw-r--r--doc/guides/cryptodevs/openssl.rst6
-rw-r--r--doc/guides/cryptodevs/overview.rst68
-rw-r--r--doc/guides/cryptodevs/qat.rst430
-rw-r--r--doc/guides/cryptodevs/scheduler.rst172
-rw-r--r--doc/guides/cryptodevs/snow3g.rst6
-rw-r--r--doc/guides/cryptodevs/zuc.rst6
25 files changed, 1448 insertions, 336 deletions
diff --git a/doc/guides/cryptodevs/aesni_gcm.rst b/doc/guides/cryptodevs/aesni_gcm.rst
index 04bf43c2..84cdc52a 100644
--- a/doc/guides/cryptodevs/aesni_gcm.rst
+++ b/doc/guides/cryptodevs/aesni_gcm.rst
@@ -32,10 +32,8 @@ AES-NI GCM Crypto Poll Mode Driver
The AES-NI GCM PMD (**librte_pmd_aesni_gcm**) provides poll mode crypto driver
-support for utilizing Intel multi buffer library (see AES-NI Multi-buffer PMD documentation
-to learn more about it, including installation).
-
-The AES-NI GCM PMD has current only been tested on Fedora 21 64-bit with gcc.
+support for utilizing Intel ISA-L crypto library, which provides operation acceleration
+through the AES-NI instruction sets for AES-GCM authenticated cipher algorithm.
Features
--------
@@ -49,24 +47,29 @@ Cipher algorithms:
Authentication algorithms:
* RTE_CRYPTO_AUTH_AES_GCM
+* RTE_CRYPTO_AUTH_AES_GMAC
+
+Installation
+------------
+
+To build DPDK with the AESNI_GCM_PMD the user is required to install
+the ``libisal_crypto`` library in the build environment.
+For download and more details please visit `<https://github.com/01org/isa-l_crypto>`_.
Initialization
--------------
In order to enable this virtual crypto PMD, user must:
-* Export the environmental variable AESNI_MULTI_BUFFER_LIB_PATH with the path where
- the library was extracted.
-
-* Build the multi buffer library (go to Installation section in AES-NI MB PMD documentation).
+* Install the ISA-L crypto library (explained in Installation section).
* Set CONFIG_RTE_LIBRTE_PMD_AESNI_GCM=y in config/common_base.
To use the PMD in an application, user must:
-* Call rte_eal_vdev_init("crypto_aesni_gcm") within the application.
+* Call rte_vdev_init("crypto_aesni_gcm") within the application.
-* Use --vdev="crypto_aesni_gcm" in the EAL options, which will call rte_eal_vdev_init() internally.
+* Use --vdev="crypto_aesni_gcm" in the EAL options, which will call rte_vdev_init() internally.
The following parameters (all optional) can be provided in the previous two calls:
@@ -81,14 +84,11 @@ Example:
.. code-block:: console
- ./l2fwd-crypto -c 40 -n 4 --vdev="crypto_aesni_gcm,socket_id=1,max_nb_sessions=128"
+ ./l2fwd-crypto -l 6 -n 4 --vdev="crypto_aesni_gcm,socket_id=1,max_nb_sessions=128"
Limitations
-----------
-* Chained mbufs are not supported.
+* Chained mbufs are supported but only out-of-place (destination mbuf must be contiguous).
* Hash only is not supported.
* Cipher only is not supported.
-* Only in-place is currently supported (destination address is the same as source address).
-* Only supports session-oriented API implementation (session-less APIs are not supported).
-* Not performance tuned.
diff --git a/doc/guides/cryptodevs/aesni_mb.rst b/doc/guides/cryptodevs/aesni_mb.rst
index e812e957..ecb52a10 100644
--- a/doc/guides/cryptodevs/aesni_mb.rst
+++ b/doc/guides/cryptodevs/aesni_mb.rst
@@ -27,7 +27,7 @@
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-AESN-NI Multi Buffer Crytpo Poll Mode Driver
+AESN-NI Multi Buffer Crypto Poll Mode Driver
============================================
@@ -51,36 +51,53 @@ Cipher algorithms:
* RTE_CRYPTO_CIPHER_AES128_CTR
* RTE_CRYPTO_CIPHER_AES192_CTR
* RTE_CRYPTO_CIPHER_AES256_CTR
+* RTE_CRYPTO_CIPHER_AES_DOCSISBPI
Hash algorithms:
+* RTE_CRYPTO_HASH_MD5_HMAC
* RTE_CRYPTO_HASH_SHA1_HMAC
+* RTE_CRYPTO_HASH_SHA224_HMAC
* RTE_CRYPTO_HASH_SHA256_HMAC
+* RTE_CRYPTO_HASH_SHA384_HMAC
* RTE_CRYPTO_HASH_SHA512_HMAC
+* RTE_CRYPTO_HASH_AES_XCBC_HMAC
Limitations
-----------
* Chained mbufs are not supported.
-* Hash only is not supported.
-* Cipher only is not supported.
* Only in-place is currently supported (destination address is the same as source address).
* Only supports session-oriented API implementation (session-less APIs are not supported).
-* Not performance tuned.
Installation
------------
-To build DPDK with the AESNI_MB_PMD the user is required to download the mult-
-buffer library from `here <https://downloadcenter.intel.com/download/22972>`_
-and compile it on their user system before building DPDK. When building the
-multi-buffer library it is necessary to have YASM package installed and also
-requires the overriding of YASM path when building, as a path is hard coded in
-the Makefile of the release package.
+To build DPDK with the AESNI_MB_PMD the user is required to download the multi-buffer
+library from `here <https://github.com/01org/intel-ipsec-mb>`_
+and compile it on their user system before building DPDK.
+The latest version of the library supported by this PMD is v0.45, which
+can be downloaded in `<https://github.com/01org/intel-ipsec-mb/archive/v0.45.zip>`_.
.. code-block:: console
- make YASM=/usr/bin/yasm
+ make
+
+As a reference, the following table shows a mapping between the past DPDK versions
+and the Multi-Buffer library version supported by them:
+
+.. _table_aesni_mb_versions:
+
+.. table:: DPDK and Multi-Buffer library version compatibility
+
+ ============= ============================
+ DPDK version Multi-buffer library version
+ ============= ============================
+ 2.2 - 16.11 0.43 - 0.44
+ 17.02 0.44
+ 17.05 0.45
+ ============= ============================
+
Initialization
--------------
@@ -96,9 +113,9 @@ In order to enable this virtual crypto PMD, user must:
To use the PMD in an application, user must:
-* Call rte_eal_vdev_init("crypto_aesni_mb") within the application.
+* Call rte_vdev_init("crypto_aesni_mb") within the application.
-* Use --vdev="crypto_aesni_mb" in the EAL options, which will call rte_eal_vdev_init() internally.
+* Use --vdev="crypto_aesni_mb" in the EAL options, which will call rte_vdev_init() internally.
The following parameters (all optional) can be provided in the previous two calls:
@@ -113,4 +130,4 @@ Example:
.. code-block:: console
- ./l2fwd-crypto -c 40 -n 4 --vdev="crypto_aesni_mb,socket_id=1,max_nb_sessions=128"
+ ./l2fwd-crypto -l 6 -n 4 --vdev="crypto_aesni_mb,socket_id=1,max_nb_sessions=128"
diff --git a/doc/guides/cryptodevs/armv8.rst b/doc/guides/cryptodevs/armv8.rst
new file mode 100644
index 00000000..de63793f
--- /dev/null
+++ b/doc/guides/cryptodevs/armv8.rst
@@ -0,0 +1,98 @@
+.. BSD LICENSE
+ Copyright (C) Cavium networks Ltd. 2017.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions
+ are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+ * Neither the name of Cavium networks nor the names of its
+ contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+
+ARMv8 Crypto Poll Mode Driver
+=============================
+
+This code provides the initial implementation of the ARMv8 crypto PMD.
+The driver uses ARMv8 cryptographic extensions to process chained crypto
+operations in an optimized way. The core functionality is provided by
+a low-level library, written in the assembly code.
+
+Features
+--------
+
+ARMv8 Crypto PMD has support for the following algorithm pairs:
+
+Supported cipher algorithms:
+
+* ``RTE_CRYPTO_CIPHER_AES_CBC``
+
+Supported authentication algorithms:
+
+* ``RTE_CRYPTO_AUTH_SHA1_HMAC``
+* ``RTE_CRYPTO_AUTH_SHA256_HMAC``
+
+Installation
+------------
+
+In order to enable this virtual crypto PMD, user must:
+
+* Download ARMv8 crypto library source code from
+ `here <https://github.com/caviumnetworks/armv8_crypto>`_
+
+* Export the environmental variable ARMV8_CRYPTO_LIB_PATH with
+ the path where the ``armv8_crypto`` library was downloaded
+ or cloned.
+
+* Build the library by invoking:
+
+.. code-block:: console
+
+ make -C $ARMV8_CRYPTO_LIB_PATH/
+
+* Set CONFIG_RTE_LIBRTE_PMD_ARMV8_CRYPTO=y in
+ config/defconfig_arm64-armv8a-linuxapp-gcc
+
+The corresponding device can be created only if the following features
+are supported by the CPU:
+
+* ``RTE_CPUFLAG_AES``
+* ``RTE_CPUFLAG_SHA1``
+* ``RTE_CPUFLAG_SHA2``
+* ``RTE_CPUFLAG_NEON``
+
+Initialization
+--------------
+
+User can use app/test application to check how to use this PMD and to verify
+crypto processing.
+
+Test name is cryptodev_sw_armv8_autotest.
+For performance test cryptodev_sw_armv8_perftest can be used.
+
+Limitations
+-----------
+
+* Maximum number of sessions is 2048.
+* Only chained operations are supported.
+* AES-128-CBC is the only supported cipher variant.
+* Cipher input data has to be a multiple of 16 bytes.
+* Digest input data has to be a multiple of 8 bytes.
diff --git a/doc/guides/cryptodevs/dpaa2_sec.rst b/doc/guides/cryptodevs/dpaa2_sec.rst
new file mode 100644
index 00000000..becb910e
--- /dev/null
+++ b/doc/guides/cryptodevs/dpaa2_sec.rst
@@ -0,0 +1,232 @@
+.. BSD LICENSE
+ Copyright(c) 2016 NXP. All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions
+ are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+ * Neither the name of NXP nor the names of its
+ contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+
+NXP DPAA2 CAAM (DPAA2_SEC)
+==========================
+
+The DPAA2_SEC PMD provides poll mode crypto driver support for NXP DPAA2 CAAM
+hardware accelerator.
+
+Architecture
+------------
+
+SEC is the SOC's security engine, which serves as NXP's latest cryptographic
+acceleration and offloading hardware. It combines functions previously
+implemented in separate modules to create a modular and scalable acceleration
+and assurance engine. It also implements block encryption algorithms, stream
+cipher algorithms, hashing algorithms, public key algorithms, run-time
+integrity checking, and a hardware random number generator. SEC performs
+higher-level cryptographic operations than previous NXP cryptographic
+accelerators. This provides significant improvement to system level performance.
+
+DPAA2_SEC is one of the hardware resource in DPAA2 Architecture. More information
+on DPAA2 Architecture is described in :ref:`dpaa2_overview`.
+
+DPAA2_SEC PMD is one of DPAA2 drivers which interacts with Management Complex (MC)
+portal to access the hardware object - DPSECI. The MC provides access to create,
+discover, connect, configure and destroy dpseci objects in DPAA2_SEC PMD.
+
+DPAA2_SEC PMD also uses some of the other hardware resources like buffer pools,
+queues, queue portals to store and to enqueue/dequeue data to the hardware SEC.
+
+DPSECI objects are detected by PMD using a resource container called DPRC (like
+in :ref:`dpaa2_overview`).
+
+For example:
+
+.. code-block:: console
+
+ DPRC.1 (bus)
+ |
+ +--+--------+-------+-------+-------+---------+
+ | | | | | |
+ DPMCP.1 DPIO.1 DPBP.1 DPNI.1 DPMAC.1 DPSECI.1
+ DPMCP.2 DPIO.2 DPNI.2 DPMAC.2 DPSECI.2
+ DPMCP.3
+
+Implementation
+--------------
+
+SEC provides platform assurance by working with SecMon, which is a companion
+logic block that tracks the security state of the SOC. SEC is programmed by
+means of descriptors (not to be confused with frame descriptors (FDs)) that
+indicate the operations to be performed and link to the message and
+associated data. SEC incorporates two DMA engines to fetch the descriptors,
+read the message data, and write the results of the operations. The DMA
+engine provides a scatter/gather capability so that SEC can read and write
+data scattered in memory. SEC may be configured by means of software for
+dynamic changes in byte ordering. The default configuration for this version
+of SEC is little-endian mode.
+
+A block diagram similar to dpaa2 NIC is shown below to show where DPAA2_SEC
+fits in the DPAA2 Bus model
+
+.. code-block:: console
+
+
+ +----------------+
+ | DPDK DPAA2_SEC |
+ | PMD |
+ +----------------+ +------------+
+ | MC SEC object |.......| Mempool |
+ . . . . . . . . . | (DPSECI) | | (DPBP) |
+ . +---+---+--------+ +-----+------+
+ . ^ | .
+ . | |<enqueue, .
+ . | | dequeue> .
+ . | | .
+ . +---+---V----+ .
+ . . . . . . . . . . .| DPIO driver| .
+ . . | (DPIO) | .
+ . . +-----+------+ .
+ . . | QBMAN | .
+ . . | Driver | .
+ +----+------+-------+ +-----+----- | .
+ | dpaa2 bus | | .
+ | VFIO fslmc-bus |....................|.........................
+ | | |
+ | /bus/fslmc | |
+ +-------------------+ |
+ |
+ ========================== HARDWARE =====|=======================
+ DPIO
+ |
+ DPSECI---DPBP
+ =========================================|========================
+
+
+
+Features
+--------
+
+The DPAA2 PMD has support for:
+
+Cipher algorithms:
+
+* ``RTE_CRYPTO_CIPHER_3DES_CBC``
+* ``RTE_CRYPTO_CIPHER_AES128_CBC``
+* ``RTE_CRYPTO_CIPHER_AES192_CBC``
+* ``RTE_CRYPTO_CIPHER_AES256_CBC``
+
+Hash algorithms:
+
+* ``RTE_CRYPTO_AUTH_SHA1_HMAC``
+* ``RTE_CRYPTO_AUTH_SHA224_HMAC``
+* ``RTE_CRYPTO_AUTH_SHA256_HMAC``
+* ``RTE_CRYPTO_AUTH_SHA384_HMAC``
+* ``RTE_CRYPTO_AUTH_SHA512_HMAC``
+* ``RTE_CRYPTO_AUTH_MD5_HMAC``
+
+Supported DPAA2 SoCs
+--------------------
+
+* LS2080A/LS2040A
+* LS2084A/LS2044A
+* LS2088A/LS2048A
+* LS1088A/LS1048A
+
+Limitations
+-----------
+
+* Chained mbufs are not supported.
+* Hash followed by Cipher mode is not supported
+* Only supports the session-oriented API implementation (session-less APIs are not supported).
+
+Prerequisites
+-------------
+
+DPAA2_SEC driver has similar pre-requisites as described in :ref:`dpaa2_overview`.
+The following dependencies are not part of DPDK and must be installed separately:
+
+* **NXP Linux SDK**
+
+ NXP Linux software development kit (SDK) includes support for the family
+ of QorIQ® ARM-Architecture-based system on chip (SoC) processors
+ and corresponding boards.
+
+ It includes the Linux board support packages (BSPs) for NXP SoCs,
+ a fully operational tool chain, kernel and board specific modules.
+
+ SDK and related information can be obtained from: `NXP QorIQ SDK <http://www.nxp.com/products/software-and-tools/run-time-software/linux-sdk/linux-sdk-for-qoriq-processors:SDKLINUX>`_.
+
+* **DPDK Helper Scripts**
+
+ DPAA2 based resources can be configured easily with the help of ready scripts
+ as provided in the DPDK helper repository.
+
+ `DPDK Helper Scripts <https://github.com/qoriq-open-source/dpdk-helper>`_.
+
+Currently supported by DPDK:
+
+* NXP SDK **2.0+**.
+* MC Firmware version **10.0.0** and higher.
+* Supported architectures: **arm64 LE**.
+
+* Follow the DPDK :ref:`Getting Started Guide for Linux <linux_gsg>` to setup the basic DPDK environment.
+
+Pre-Installation Configuration
+------------------------------
+
+Config File Options
+~~~~~~~~~~~~~~~~~~~
+
+Basic DPAA2 config file options are described in :ref:`dpaa2_overview`.
+In addition to those, the following options can be modified in the ``config`` file
+to enable DPAA2_SEC PMD.
+
+Please note that enabling debugging options may affect system performance.
+
+* ``CONFIG_RTE_LIBRTE_PMD_DPAA2_SEC`` (default ``n``)
+ By default it is only enabled in defconfig_arm64-dpaa2-* config.
+ Toggle compilation of the ``librte_pmd_dpaa2_sec`` driver.
+
+* ``CONFIG_RTE_LIBRTE_DPAA2_SEC_DEBUG_INIT`` (default ``n``)
+ Toggle display of initialization related driver messages
+
+* ``CONFIG_RTE_LIBRTE_DPAA2_SEC_DEBUG_DRIVER`` (default ``n``)
+ Toggle display of driver runtime messages
+
+* ``CONFIG_RTE_LIBRTE_DPAA2_SEC_DEBUG_RX`` (default ``n``)
+ Toggle display of receive fast path run-time message
+
+* ``CONFIG_RTE_DPAA2_SEC_PMD_MAX_NB_SESSIONS``
+ By default it is set as 2048 in defconfig_arm64-dpaa2-* config.
+ It indicates Number of sessions to create in the session memory pool
+ on a single DPAA2 SEC device.
+
+Installations
+-------------
+To compile the DPAA2_SEC PMD for Linux arm64 gcc target, run the
+following ``make`` command:
+
+.. code-block:: console
+
+ cd <DPDK-source-directory>
+ make config T=arm64-dpaa2-linuxapp-gcc install
diff --git a/doc/guides/cryptodevs/features/aesni_gcm.ini b/doc/guides/cryptodevs/features/aesni_gcm.ini
new file mode 100644
index 00000000..5d9e119d
--- /dev/null
+++ b/doc/guides/cryptodevs/features/aesni_gcm.ini
@@ -0,0 +1,27 @@
+;
+; Supported features of the 'aesni_gcm' crypto driver.
+;
+; Refer to default.ini for the full list of available PMD features.
+;
+[Features]
+Symmetric crypto = Y
+Sym operation chaining = Y
+CPU AESNI = Y
+
+;
+; Supported crypto algorithms of the 'aesni_gcm' crypto driver.
+;
+[Cipher]
+
+;
+; Supported authentication algorithms of the 'aesni_gcm' crypto driver.
+;
+[Auth]
+AES GMAC = Y
+
+;
+; Supported AEAD algorithms of the 'aesni_gcm' crypto driver.
+;
+[AEAD]
+AES GCM (128) = Y
+AES GCM (256) = Y
diff --git a/doc/guides/cryptodevs/features/aesni_mb.ini b/doc/guides/cryptodevs/features/aesni_mb.ini
new file mode 100644
index 00000000..03d8485d
--- /dev/null
+++ b/doc/guides/cryptodevs/features/aesni_mb.ini
@@ -0,0 +1,41 @@
+;
+; Supported features of the 'aesni_mb' crypto driver.
+;
+; Refer to default.ini for the full list of available PMD features.
+;
+[Features]
+Symmetric crypto = Y
+Sym operation chaining = Y
+CPU SSE = Y
+CPU AVX = Y
+CPU AVX2 = Y
+CPU AVX512 = Y
+CPU AESNI = Y
+
+;
+; Supported crypto algorithms of the 'aesni_mb' crypto driver.
+;
+[Cipher]
+AES CBC (128) = Y
+AES CBC (192) = Y
+AES CBC (256) = Y
+AES CTR (128) = Y
+AES CTR (192) = Y
+AES CTR (256) = Y
+AES DOCSIS BPI = Y
+;
+; Supported authentication algorithms of the 'aesni_mb' crypto driver.
+;
+[Auth]
+MD5 HMAC = Y
+SHA1 HMAC = Y
+SHA224 HMAC = Y
+SHA256 HMAC = Y
+SHA384 HMAC = Y
+SHA512 HMAC = Y
+AES XCBC MAC = Y
+
+;
+; Supported AEAD algorithms of the 'aesni_mb' crypto driver.
+;
+[AEAD]
diff --git a/doc/guides/cryptodevs/features/armv8.ini b/doc/guides/cryptodevs/features/armv8.ini
new file mode 100644
index 00000000..1e104771
--- /dev/null
+++ b/doc/guides/cryptodevs/features/armv8.ini
@@ -0,0 +1,28 @@
+;
+; Supported features of the 'armv8' crypto driver.
+;
+; Refer to default.ini for the full list of available PMD features.
+;
+[Features]
+Symmetric crypto = Y
+Sym operation chaining = Y
+CPU NEON = Y
+CPU ARM CE = Y
+
+;
+; Supported crypto algorithms of the 'armv8' crypto driver.
+;
+[Cipher]
+AES CBC (128) = Y
+
+;
+; Supported authentication algorithms of the 'armv8' crypto driver.
+;
+[Auth]
+SHA1 HMAC = Y
+SHA256 HMAC = Y
+
+;
+; Supported AEAD algorithms of the 'armv8' crypto driver.
+;
+[AEAD]
diff --git a/doc/guides/cryptodevs/features/default.ini b/doc/guides/cryptodevs/features/default.ini
new file mode 100644
index 00000000..0926887b
--- /dev/null
+++ b/doc/guides/cryptodevs/features/default.ini
@@ -0,0 +1,70 @@
+;
+; Features of a default crypto driver.
+;
+; This file defines the features that are valid for inclusion in
+; the other driver files and also the order that they appear in
+; the features table in the documentation.
+;
+[Features]
+Symmetric crypto =
+Asymmetric crypto =
+Sym operation chaining =
+HW Accelerated =
+CPU SSE =
+CPU AVX =
+CPU AVX2 =
+CPU AVX512 =
+CPU AESNI =
+CPU NEON =
+CPU ARM CE =
+
+;
+; Supported crypto algorithms of a default crypto driver.
+;
+[Cipher]
+NULL =
+AES CBC (128) =
+AES CBC (192) =
+AES CBC (256) =
+AES CTR (128) =
+AES CTR (192) =
+AES CTR (256) =
+AES DOCSIS BPI =
+3DES CBC =
+3DES CTR =
+DES CBC =
+DES DOCSIS BPI =
+SNOW3G UEA2 =
+KASUMI F8 =
+ZUC EEA3 =
+
+;
+; Supported authentication algorithms of a default crypto driver.
+;
+[Auth]
+NULL =
+MD5 =
+MD5 HMAC =
+SHA1 =
+SHA1 HMAC =
+SHA224 =
+SHA224 HMAC =
+SHA256 =
+SHA256 HMAC =
+SHA384 =
+SHA384 HMAC =
+SHA512 =
+SHA512 HMAC =
+AES XCBC MAC =
+AES GMAC =
+SNOW3G UIA2 =
+KASUMI F9 =
+ZUC EIA3 =
+
+;
+; Supported AEAD algorithms of a default crypto driver.
+;
+[AEAD]
+AES GCM (128) =
+AES GCM (192) =
+AES GCM (256) =
diff --git a/doc/guides/cryptodevs/features/dpaa2_sec.ini b/doc/guides/cryptodevs/features/dpaa2_sec.ini
new file mode 100644
index 00000000..db0ea4f9
--- /dev/null
+++ b/doc/guides/cryptodevs/features/dpaa2_sec.ini
@@ -0,0 +1,34 @@
+;
+; Supported features of the 'dpaa2_sec' crypto driver.
+;
+; Refer to default.ini for the full list of available PMD features.
+;
+[Features]
+Symmetric crypto = Y
+Sym operation chaining = Y
+HW Accelerated = Y
+
+;
+; Supported crypto algorithms of the 'dpaa2_sec' crypto driver.
+;
+[Cipher]
+AES CBC (128) = Y
+AES CBC (192) = Y
+AES CBC (256) = Y
+3DES CBC = Y
+
+;
+; Supported authentication algorithms of the 'dpaa2_sec' crypto driver.
+;
+[Auth]
+MD5 HMAC = Y
+SHA1 HMAC = Y
+SHA224 HMAC = Y
+SHA256 HMAC = Y
+SHA384 HMAC = Y
+SHA512 HMAC = Y
+
+;
+; Supported AEAD algorithms of the 'openssl' crypto driver.
+;
+[AEAD]
diff --git a/doc/guides/cryptodevs/features/kasumi.ini b/doc/guides/cryptodevs/features/kasumi.ini
new file mode 100644
index 00000000..0e138f5a
--- /dev/null
+++ b/doc/guides/cryptodevs/features/kasumi.ini
@@ -0,0 +1,24 @@
+;
+; Supported features of the 'kasumi' crypto driver.
+;
+; Refer to default.ini for the full list of available PMD features.
+;
+[Features]
+Symmetric crypto = Y
+Sym operation chaining = Y
+
+;
+; Supported crypto algorithms of the 'kasumi' crypto driver.
+;
+[Cipher]
+KASUMI F8 = Y
+;
+; Supported authentication algorithms of the 'kasumi' crypto driver.
+;
+[Auth]
+KASUMI F9 = Y
+
+;
+; Supported AEAD algorithms of the 'kasumi' crypto driver.
+;
+[AEAD]
diff --git a/doc/guides/cryptodevs/features/null.ini b/doc/guides/cryptodevs/features/null.ini
new file mode 100644
index 00000000..523c453c
--- /dev/null
+++ b/doc/guides/cryptodevs/features/null.ini
@@ -0,0 +1,25 @@
+;
+; Supported features of the 'null' crypto driver.
+;
+; Refer to default.ini for the full list of available PMD features.
+;
+[Features]
+Symmetric crypto = Y
+Sym operation chaining = Y
+
+;
+; Supported crypto algorithms of the 'null' crypto driver.
+;
+[Cipher]
+NULL = Y
+
+;
+; Supported authentication algorithms of the 'null' crypto driver.
+;
+[Auth]
+NULL = Y
+
+;
+; Supported AEAD algorithms of the 'null' crypto driver.
+;
+[AEAD]
diff --git a/doc/guides/cryptodevs/features/openssl.ini b/doc/guides/cryptodevs/features/openssl.ini
new file mode 100644
index 00000000..aeb2a500
--- /dev/null
+++ b/doc/guides/cryptodevs/features/openssl.ini
@@ -0,0 +1,47 @@
+;
+; Supported features of the 'openssl' crypto driver.
+;
+; Refer to default.ini for the full list of available PMD features.
+;
+[Features]
+Symmetric crypto = Y
+Sym operation chaining = Y
+
+;
+; Supported crypto algorithms of the 'openssl' crypto driver.
+;
+[Cipher]
+AES CBC (128) = Y
+AES CBC (192) = Y
+AES CBC (256) = Y
+AES CTR (128) = Y
+AES CTR (192) = Y
+AES CTR (256) = Y
+3DES CBC = Y
+3DES CTR = Y
+DES DOCSIS BPI = Y
+;
+; Supported authentication algorithms of the 'openssl' crypto driver.
+;
+[Auth]
+MD5 = Y
+MD5 HMAC = Y
+SHA1 = Y
+SHA1 HMAC = Y
+SHA224 = Y
+SHA224 HMAC = Y
+SHA256 = Y
+SHA256 HMAC = Y
+SHA384 = Y
+SHA384 HMAC = Y
+SHA512 = Y
+SHA512 HMAC = Y
+AES GMAC = Y
+
+;
+; Supported AEAD algorithms of the 'openssl' crypto driver.
+;
+[AEAD]
+AES GCM (128) = Y
+AES GCM (192) = Y
+AES GCM (256) = Y
diff --git a/doc/guides/cryptodevs/features/qat.ini b/doc/guides/cryptodevs/features/qat.ini
new file mode 100644
index 00000000..40da8985
--- /dev/null
+++ b/doc/guides/cryptodevs/features/qat.ini
@@ -0,0 +1,53 @@
+;
+; Supported features of the 'qat' crypto driver.
+;
+; Refer to default.ini for the full list of available PMD features.
+;
+[Features]
+Symmetric crypto = Y
+Sym operation chaining = Y
+HW Accelerated = Y
+
+;
+; Supported crypto algorithms of the 'qat' crypto driver.
+;
+[Cipher]
+NULL = Y
+AES CBC (128) = Y
+AES CBC (192) = Y
+AES CBC (256) = Y
+AES CTR (128) = Y
+AES CTR (192) = Y
+AES CTR (256) = Y
+3DES CBC = Y
+3DES CTR = Y
+DES CBC = Y
+SNOW3G UEA2 = Y
+KASUMI F8 = Y
+AES DOCSIS BPI = Y
+DES DOCSIS BPI = Y
+ZUC EEA3 = Y
+;
+; Supported authentication algorithms of the 'qat' crypto driver.
+;
+[Auth]
+NULL = Y
+MD5 HMAC = Y
+SHA1 HMAC = Y
+SHA224 HMAC = Y
+SHA256 HMAC = Y
+SHA384 HMAC = Y
+SHA512 HMAC = Y
+AES GMAC = Y
+SNOW3G UIA2 = Y
+KASUMI F9 = Y
+AES XCBC MAC = Y
+ZUC EIA3 = Y
+
+;
+; Supported AEAD algorithms of the 'qat' crypto driver.
+;
+[AEAD]
+AES GCM (128) = Y
+AES GCM (192) = Y
+AES GCM (256) = Y
diff --git a/doc/guides/cryptodevs/features/snow3g.ini b/doc/guides/cryptodevs/features/snow3g.ini
new file mode 100644
index 00000000..27713617
--- /dev/null
+++ b/doc/guides/cryptodevs/features/snow3g.ini
@@ -0,0 +1,24 @@
+;
+; Supported features of the 'snow3g' crypto driver.
+;
+; Refer to default.ini for the full list of available PMD features.
+;
+[Features]
+Symmetric crypto = Y
+Sym operation chaining = Y
+
+;
+; Supported crypto algorithms of the 'snow3g' crypto driver.
+;
+[Cipher]
+SNOW3G UEA2 = Y
+;
+; Supported authentication algorithms of the 'snow3g' crypto driver.
+;
+[Auth]
+SNOW3G UIA2 = Y
+
+;
+; Supported AEAD algorithms of the 'snow3g' crypto driver.
+;
+[AEAD]
diff --git a/doc/guides/cryptodevs/features/zuc.ini b/doc/guides/cryptodevs/features/zuc.ini
new file mode 100644
index 00000000..5bb02afd
--- /dev/null
+++ b/doc/guides/cryptodevs/features/zuc.ini
@@ -0,0 +1,24 @@
+;
+; Supported features of the 'zuc' crypto driver.
+;
+; Refer to default.ini for the full list of available PMD features.
+;
+[Features]
+Symmetric crypto = Y
+Sym operation chaining = Y
+
+;
+; Supported crypto algorithms of the 'zuc' crypto driver.
+;
+[Cipher]
+ZUC EEA3 = Y
+;
+; Supported authentication algorithms of the 'zuc' crypto driver.
+;
+[Auth]
+ZUC EIA3 = Y
+
+;
+; Supported AEAD algorithms of the 'zuc' crypto driver.
+;
+[AEAD]
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new file mode 100644
index 00000000..82bb775b
--- /dev/null
+++ b/doc/guides/cryptodevs/img/scheduler-overview.svg
@@ -0,0 +1,277 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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+ <title>Sheet.139</title>
+ <g id="shape33-26" v:mID="33" v:groupContext="shape">
+ <title>Rounded Rectangle.40</title>
+ <desc>Cryptodev Scheduler</desc>
+ <v:userDefs>
+ <v:ud v:nameU="CTypeTopLeftSnip" v:prompt="" v:val="VT0(0):5"/>
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+ <v:ud v:nameU="CornerLockVert" v:prompt="" v:val="VT0(1):5"/>
+ <v:ud v:nameU="CornerLockDiag" v:prompt="" v:val="VT0(0):5"/>
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+ <text x="171.72" y="181" class="st6" v:langID="1033"><v:paragraph v:horizAlign="1"/><v:tabList/>Cryptodev Scheduler</text> </g>
+ <g id="shape138-32" v:mID="138" v:groupContext="shape" transform="translate(24.6009,-12.5889)">
+ <title>Rounded Rectangle.138</title>
+ <desc>Crypto Op Distribution Mechanism</desc>
+ <v:userDefs>
+ <v:ud v:nameU="CTypeTopLeftSnip" v:prompt="" v:val="VT0(0):5"/>
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+ <v:ud v:nameU="CornerLockDiag" v:prompt="" v:val="VT0(0):5"/>
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+ <text x="103.11" y="235.35" class="st4" v:langID="1033"><v:paragraph v:horizAlign="1"/><v:tabList/>Crypto Op Distribution Mechanism</text> </g>
+ </g>
+ <g id="shape140-35" v:mID="140" v:groupContext="shape" v:layerMember="0" transform="translate(234.378,-149.789)">
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+ <path d="M7.09 245.51 L7.09 267.39" class="st8"/>
+ </g>
+ </g>
+</svg>
diff --git a/doc/guides/cryptodevs/index.rst b/doc/guides/cryptodevs/index.rst
index a6a9f23c..361b82dd 100644
--- a/doc/guides/cryptodevs/index.rst
+++ b/doc/guides/cryptodevs/index.rst
@@ -1,5 +1,5 @@
.. BSD LICENSE
- Copyright(c) 2015 - 2016 Intel Corporation. All rights reserved.
+ Copyright(c) 2015 - 2017 Intel Corporation. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
@@ -38,9 +38,12 @@ Crypto Device Drivers
overview
aesni_mb
aesni_gcm
+ armv8
+ dpaa2_sec
kasumi
openssl
null
+ scheduler
snow3g
qat
zuc
diff --git a/doc/guides/cryptodevs/kasumi.rst b/doc/guides/cryptodevs/kasumi.rst
index 90d8e7b3..bff9321e 100644
--- a/doc/guides/cryptodevs/kasumi.rst
+++ b/doc/guides/cryptodevs/kasumi.rst
@@ -90,9 +90,9 @@ In order to enable this virtual crypto PMD, user must:
To use the PMD in an application, user must:
-* Call rte_eal_vdev_init("crypto_kasumi") within the application.
+* Call rte_vdev_init("crypto_kasumi") within the application.
-* Use --vdev="crypto_kasumi" in the EAL options, which will call rte_eal_vdev_init() internally.
+* Use --vdev="crypto_kasumi" in the EAL options, which will call rte_vdev_init() internally.
The following parameters (all optional) can be provided in the previous two calls:
@@ -107,4 +107,4 @@ Example:
.. code-block:: console
- ./l2fwd-crypto -c 40 -n 4 --vdev="crypto_kasumi,socket_id=1,max_nb_sessions=128"
+ ./l2fwd-crypto -l 6 -n 4 --vdev="crypto_kasumi,socket_id=1,max_nb_sessions=128"
diff --git a/doc/guides/cryptodevs/null.rst b/doc/guides/cryptodevs/null.rst
index ec5bc70d..4a3bfdfd 100644
--- a/doc/guides/cryptodevs/null.rst
+++ b/doc/guides/cryptodevs/null.rst
@@ -76,9 +76,9 @@ Initialization
To use the PMD in an application, user must:
-* Call rte_eal_vdev_init("crypto_null") within the application.
+* Call rte_vdev_init("crypto_null") within the application.
-* Use --vdev="crypto_null" in the EAL options, which will call rte_eal_vdev_init() internally.
+* Use --vdev="crypto_null" in the EAL options, which will call rte_vdev_init() internally.
The following parameters (all optional) can be provided in the previous two calls:
@@ -93,4 +93,4 @@ Example:
.. code-block:: console
- ./l2fwd-crypto -c 40 -n 4 --vdev="crypto_null,socket_id=1,max_nb_sessions=128"
+ ./l2fwd-crypto -l 6 -n 4 --vdev="crypto_null,socket_id=1,max_nb_sessions=128"
diff --git a/doc/guides/cryptodevs/openssl.rst b/doc/guides/cryptodevs/openssl.rst
index f1c39bac..e3419151 100644
--- a/doc/guides/cryptodevs/openssl.rst
+++ b/doc/guides/cryptodevs/openssl.rst
@@ -49,6 +49,7 @@ Supported cipher algorithms:
* ``RTE_CRYPTO_CIPHER_AES_CTR``
* ``RTE_CRYPTO_CIPHER_3DES_CTR``
* ``RTE_CRYPTO_CIPHER_AES_GCM``
+* ``RTE_CRYPTO_CIPHER_DES_DOCSISBPI``
Supported authentication algorithms:
* ``RTE_CRYPTO_AUTH_AES_GMAC``
@@ -98,7 +99,7 @@ To verify real traffic l2fwd-crypto example can be used with this command:
.. code-block:: console
- sudo ./build/l2fwd-crypto -c 0x3 -n 4 --vdev "crypto_openssl"
+ sudo ./build/l2fwd-crypto -l 0-1 -n 4 --vdev "crypto_openssl"
--vdev "crypto_openssl"-- -p 0x3 --chain CIPHER_HASH
--cipher_op ENCRYPT --cipher_algo AES_CBC
--cipher_key 00:01:02:03:04:05:06:07:08:09:0a:0b:0c:0d:0e:0f
@@ -112,6 +113,7 @@ Limitations
-----------
* Maximum number of sessions is 2048.
-* Chained mbufs are not supported.
+* Chained mbufs are supported only for source mbuf (destination must be
+ contiguous).
* Hash only is not supported for GCM and GMAC.
* Cipher only is not supported for GCM and GMAC.
diff --git a/doc/guides/cryptodevs/overview.rst b/doc/guides/cryptodevs/overview.rst
index d612f71b..6764d0d9 100644
--- a/doc/guides/cryptodevs/overview.rst
+++ b/doc/guides/cryptodevs/overview.rst
@@ -1,5 +1,5 @@
.. BSD LICENSE
- Copyright(c) 2016 Intel Corporation. All rights reserved.
+ Copyright(c) 2016-2017 Intel Corporation. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
@@ -11,7 +11,7 @@
notice, this list of conditions and the following disclaimer in
the documentation and/or other materials provided with the
distribution.
- * Neither the name of Intel Corporation nor the names of its
+ * Neither the name of 6WIND S.A. nor the names of its
contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
@@ -28,68 +28,32 @@
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Crypto Device Supported Functionality Matrices
-----------------------------------------------
+==============================================
Supported Feature Flags
+-----------------------
-.. csv-table::
- :header: "Feature Flags", "qat", "null", "aesni_mb", "aesni_gcm", "snow3g", "kasumi"
- :stub-columns: 1
+.. _table_crypto_pmd_features:
- "RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO",x,x,x,x,x,x
- "RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO",,,,,,
- "RTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING",x,x,x,x,x,x
- "RTE_CRYPTODEV_FF_CPU_SSE",,,x,x,x,x
- "RTE_CRYPTODEV_FF_CPU_AVX",,,x,x,x,x
- "RTE_CRYPTODEV_FF_CPU_AVX2",,,x,x,,
- "RTE_CRYPTODEV_FF_CPU_AESNI",,,x,x,,
- "RTE_CRYPTODEV_FF_HW_ACCELERATED",x,,,,,
+.. include:: overview_feature_table.txt
Supported Cipher Algorithms
+---------------------------
-.. csv-table::
- :header: "Cipher Algorithms", "qat", "null", "aesni_mb", "aesni_gcm", "snow3g", "kasumi"
- :stub-columns: 1
+.. _table_crypto_pmd_cipher_algos:
- "NULL",,x,,,,
- "AES_CBC_128",x,,x,,,
- "AES_CBC_192",x,,x,,,
- "AES_CBC_256",x,,x,,,
- "AES_CTR_128",x,,x,,,
- "AES_CTR_192",x,,x,,,
- "AES_CTR_256",x,,x,,,
- "SNOW3G_UEA2",x,,,,x,
- "KASUMI_F8",,,,,,x
+.. include:: overview_cipher_table.txt
Supported Authentication Algorithms
+-----------------------------------
-.. csv-table::
- :header: "Cipher Algorithms", "qat", "null", "aesni_mb", "aesni_gcm", "snow3g", "kasumi"
- :stub-columns: 1
-
- "NONE",,x,,,,
- "MD5",,,,,,
- "MD5_HMAC",,,x,,,
- "SHA1",,,,,,
- "SHA1_HMAC",x,,x,,,
- "SHA224",,,,,,
- "SHA224_HMAC",,,x,,,
- "SHA256",,,,,,
- "SHA256_HMAC",x,,x,,,
- "SHA384",,,,,,
- "SHA384_HMAC",,,x,,,
- "SHA512",,,,,,
- "SHA512_HMAC",x,,x,,,
- "AES_XCBC",x,,x,,,
- "SNOW3G_UIA2",x,,,,x,
- "KASUMI_F9",,,,,,x
+.. _table_crypto_pmd_auth_algos:
+
+.. include:: overview_auth_table.txt
Supported AEAD Algorithms
+-------------------------
-.. csv-table::
- :header: "AEAD Algorithms", "qat", "null", "aesni_mb", "aesni_gcm", "snow3g", "kasumi"
- :stub-columns: 1
+.. _table_crypto_pmd_aead_algos:
- "AES_GCM_128",x,,x,,,
- "AES_GCM_192",x,,,,,
- "AES_GCM_256",x,,,,,
+.. include:: overview_aead_table.txt
diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst
index 52a9ae35..21b56fc6 100644
--- a/doc/guides/cryptodevs/qat.rst
+++ b/doc/guides/cryptodevs/qat.rst
@@ -30,9 +30,13 @@
Intel(R) QuickAssist (QAT) Crypto Poll Mode Driver
==================================================
-The QAT PMD provides poll mode crypto driver support for **Intel QuickAssist
-Technology DH895xxC**, **Intel QuickAssist Technology C62x** and
-**Intel QuickAssist Technology C3xxx** hardware accelerator.
+The QAT PMD provides poll mode crypto driver support for the following
+hardware accelerator devices:
+
+* ``Intel QuickAssist Technology DH895xCC``
+* ``Intel QuickAssist Technology C62x``
+* ``Intel QuickAssist Technology C3xxx``
+* ``Intel QuickAssist Technology D15xx``
Features
@@ -54,6 +58,10 @@ Cipher algorithms:
* ``RTE_CRYPTO_CIPHER_AES_GCM``
* ``RTE_CRYPTO_CIPHER_NULL``
* ``RTE_CRYPTO_CIPHER_KASUMI_F8``
+* ``RTE_CRYPTO_CIPHER_DES_CBC``
+* ``RTE_CRYPTO_CIPHER_AES_DOCSISBPI``
+* ``RTE_CRYPTO_CIPHER_DES_DOCSISBPI``
+* ``RTE_CRYPTO_CIPHER_ZUC_EEA3``
Hash algorithms:
@@ -68,349 +76,291 @@ Hash algorithms:
* ``RTE_CRYPTO_AUTH_NULL``
* ``RTE_CRYPTO_AUTH_KASUMI_F9``
* ``RTE_CRYPTO_AUTH_AES_GMAC``
+* ``RTE_CRYPTO_AUTH_ZUC_EIA3``
Limitations
-----------
-* Chained mbufs are not supported.
* Hash only is not supported except SNOW 3G UIA2 and KASUMI F9.
-* Cipher only is not supported except SNOW 3G UEA2, KASUMI F8 and 3DES.
* Only supports the session-oriented API implementation (session-less APIs are not supported).
* SNOW 3G (UEA2) and KASUMI (F8) supported only if cipher length, cipher offset fields are byte-aligned.
* SNOW 3G (UIA2) and KASUMI (F9) supported only if hash length, hash offset fields are byte-aligned.
* No BSD support as BSD QAT kernel driver not available.
+* ZUC EEA3/EIA3 is not supported by dh895xcc devices
+* Maximum additional authenticated data (AAD) for GCM is 240 bytes long.
Installation
------------
-To use the DPDK QAT PMD an SRIOV-enabled QAT kernel driver is required. The
-VF devices exposed by this driver will be used by QAT PMD.
-
-To enable QAT in DPDK, follow the instructions mentioned in
-http://dpdk.org/doc/guides/linux_gsg/build_dpdk.html
+To enable QAT in DPDK, follow the instructions for modifying the compile-time
+configuration file as described `here <http://dpdk.org/doc/guides/linux_gsg/build_dpdk.html>`_.
-Quick instructions as follows:
+Quick instructions are as follows:
.. code-block:: console
+ cd to the top-level DPDK directory
make config T=x86_64-native-linuxapp-gcc
sed -i 's,\(CONFIG_RTE_LIBRTE_PMD_QAT\)=n,\1=y,' build/.config
make
-If you are running on kernel 4.4 or greater, see instructions for
-`Installation using kernel.org driver`_ below. If you are on a kernel earlier
-than 4.4, see `Installation using 01.org QAT driver`_.
-
-For **Intel QuickAssist Technology C62x** and **Intel QuickAssist Technology C3xxx**
-device, kernel 4.5 or greater is needed.
-See instructions for `Installation using kernel.org driver`_ below.
-
-
-Installation using 01.org QAT driver
-------------------------------------
-
-NOTE: There is no driver available for **Intel QuickAssist Technology C62x** and
-**Intel QuickAssist Technology C3xxx** devices on 01.org.
-
-Download the latest QuickAssist Technology Driver from `01.org
-<https://01.org/packet-processing/intel%C2%AE-quickassist-technology-drivers-and-patches>`_
-Consult the *Getting Started Guide* at the same URL for further information.
+To use the DPDK QAT PMD an SRIOV-enabled QAT kernel driver is required. The VF
+devices exposed by this driver will be used by the QAT PMD. The devices and
+available kernel drivers and device ids are :
-The steps below assume you are:
+.. _table_qat_pmds_drivers:
-* Building on a platform with one ``DH895xCC`` device.
-* Using package ``qatmux.l.2.3.0-34.tgz``.
-* On Fedora21 kernel ``3.17.4-301.fc21.x86_64``.
+.. table:: QAT devices and drivers
-In the BIOS ensure that SRIOV is enabled and VT-d is disabled.
+ +----------+--------+---------------+------------+--------+---------+--------+------------+
+ | Device | Driver | Kernel Module | Pci Driver | PF Did | Num PFs | Vf Did | VFs per PF |
+ +==========+========+===============+============+========+=========+========+============+
+ | DH895xCC | 01.org | icp_qa_al | n/a | 435 | 1 | 443 | 32 |
+ +----------+--------+---------------+------------+--------+---------+--------+------------+
+ | DH895xCC | 4.4+ | qat_dh895xcc | dh895xcc | 435 | 1 | 443 | 32 |
+ +----------+--------+---------------+------------+--------+---------+--------+------------+
+ | C62x | 4.5+ | qat_c62x | c6xx | 37c8 | 3 | 37c9 | 16 |
+ +----------+--------+---------------+------------+--------+---------+--------+------------+
+ | C3xxx | 4.5+ | qat_c3xxx | c3xxx | 19e2 | 1 | 19e3 | 16 |
+ +----------+--------+---------------+------------+--------+---------+--------+------------+
+ | D15xx | p | qat_d15xx | d15xx | 6f54 | 1 | 6f55 | 16 |
+ +----------+--------+---------------+------------+--------+---------+--------+------------+
-Uninstall any existing QAT driver, for example by running:
-* ``./installer.sh uninstall`` in the directory where originally installed.
+The ``Driver`` column indicates either the Linux kernel version in which
+support for this device was introduced or a driver available on Intel's 01.org
+website. There are both linux and 01.org kernel drivers available for some
+devices. p = release pending.
-* or ``rmmod qat_dh895xcc; rmmod intel_qat``.
-
-Build and install the SRIOV-enabled QAT driver::
-
- mkdir /QAT
- cd /QAT
- # copy qatmux.l.2.3.0-34.tgz to this location
- tar zxof qatmux.l.2.3.0-34.tgz
-
- export ICP_WITHOUT_IOMMU=1
- ./installer.sh install QAT1.6 host
-
-You can use ``cat /proc/icp_dh895xcc_dev0/version`` to confirm the driver is correctly installed.
-You can use ``lspci -d:443`` to confirm the bdf of the 32 VF devices are available per ``DH895xCC`` device.
-
-To complete the installation - follow instructions in `Binding the available VFs to the DPDK UIO driver`_.
-
-**Note**: If using a later kernel and the build fails with an error relating to ``strict_stroul`` not being available apply the following patch:
-
-.. code-block:: diff
-
- /QAT/QAT1.6/quickassist/utilities/downloader/Target_CoreLibs/uclo/include/linux/uclo_platform.h
- + #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,18,5)
- + #define STR_TO_64(str, base, num, endPtr) {endPtr=NULL; if (kstrtoul((str), (base), (num))) printk("Error strtoull convert %s\n", str); }
- + #else
- #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38)
- #define STR_TO_64(str, base, num, endPtr) {endPtr=NULL; if (strict_strtoull((str), (base), (num))) printk("Error strtoull convert %s\n", str); }
- #else
- #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,25)
- #define STR_TO_64(str, base, num, endPtr) {endPtr=NULL; strict_strtoll((str), (base), (num));}
- #else
- #define STR_TO_64(str, base, num, endPtr) \
- do { \
- if (str[0] == '-') \
- { \
- *(num) = -(simple_strtoull((str+1), &(endPtr), (base))); \
- }else { \
- *(num) = simple_strtoull((str), &(endPtr), (base)); \
- } \
- } while(0)
- + #endif
- #endif
- #endif
-
-
-If the build fails due to missing header files you may need to do following:
-
-* ``sudo yum install zlib-devel``
-* ``sudo yum install openssl-devel``
-
-If the build or install fails due to mismatching kernel sources you may need to do the following:
-
-* ``sudo yum install kernel-headers-`uname -r```
-* ``sudo yum install kernel-src-`uname -r```
-* ``sudo yum install kernel-devel-`uname -r```
+If you are running on a kernel which includes a driver for your device, see
+`Installation using kernel.org driver`_ below. Otherwise see
+`Installation using 01.org QAT driver`_.
Installation using kernel.org driver
------------------------------------
-For **Intel QuickAssist Technology DH895xxC**:
-
-Assuming you are running on at least a 4.4 kernel, you can use the stock kernel.org QAT
-driver to start the QAT hardware.
-
-The steps below assume you are:
+The examples below are based on the C62x device, if you have a different device
+use the corresponding values in the above table.
-* Running DPDK on a platform with one ``DH895xCC`` device.
-* On a kernel at least version 4.4.
+In BIOS ensure that SRIOV is enabled and either:
-In BIOS ensure that SRIOV is enabled and either
-a) disable VT-d or
-b) enable VT-d and set ``"intel_iommu=on iommu=pt"`` in the grub file.
+* Disable VT-d or
+* Enable VT-d and set ``"intel_iommu=on iommu=pt"`` in the grub file.
-Ensure the QAT driver is loaded on your system, by executing::
+Check that the QAT driver is loaded on your system, by executing::
- lsmod | grep qat
+ lsmod | grep qa
-You should see the following output::
+You should see the kernel module for your device listed, e.g.::
- qat_dh895xcc 5626 0
- intel_qat 82336 1 qat_dh895xcc
+ qat_c62x 5626 0
+ intel_qat 82336 1 qat_c62x
Next, you need to expose the Virtual Functions (VFs) using the sysfs file system.
-First find the bdf of the physical function (PF) of the DH895xCC device::
+First find the BDFs (Bus-Device-Function) of the physical functions (PFs) of
+your device, e.g.::
- lspci -d : 435
+ lspci -d : 37c8
You should see output similar to::
- 03:00.0 Co-processor: Intel Corporation Coleto Creek PCIe Endpoint
-
-Using the sysfs, enable the VFs::
-
- echo 32 > /sys/bus/pci/drivers/dh895xcc/0000\:03\:00.0/sriov_numvfs
-
-If you get an error, it's likely you're using a QAT kernel driver earlier than kernel 4.4.
-
-To verify that the VFs are available for use - use ``lspci -d:443`` to confirm
-the bdf of the 32 VF devices are available per ``DH895xCC`` device.
+ 1a:00.0 Co-processor: Intel Corporation Device 37c8
+ 3d:00.0 Co-processor: Intel Corporation Device 37c8
+ 3f:00.0 Co-processor: Intel Corporation Device 37c8
-To complete the installation - follow instructions in `Binding the available VFs to the DPDK UIO driver`_.
+Enable the VFs for each PF by echoing the number of VFs per PF to the pci driver::
-**Note**: If the QAT kernel modules are not loaded and you see an error like
- ``Failed to load MMP firmware qat_895xcc_mmp.bin`` this may be as a
- result of not using a distribution, but just updating the kernel directly.
+ echo 16 > /sys/bus/pci/drivers/c6xx/0000:1a:00.0/sriov_numvfs
+ echo 16 > /sys/bus/pci/drivers/c6xx/0000:3d:00.0/sriov_numvfs
+ echo 16 > /sys/bus/pci/drivers/c6xx/0000:3f:00.0/sriov_numvfs
-Download firmware from the kernel firmware repo at:
-http://git.kernel.org/cgit/linux/kernel/git/firmware/linux-firmware.git/tree/
+Check that the VFs are available for use. For example ``lspci -d:37c9`` should
+list 48 VF devices available for a ``C62x`` device.
-Copy qat binaries to /lib/firmware:
-* ``cp qat_895xcc.bin /lib/firmware``
-* ``cp qat_895xcc_mmp.bin /lib/firmware``
+To complete the installation follow the instructions in
+`Binding the available VFs to the DPDK UIO driver`_.
-cd to your linux source root directory and start the qat kernel modules:
-* ``insmod ./drivers/crypto/qat/qat_common/intel_qat.ko``
-* ``insmod ./drivers/crypto/qat/qat_dh895xcc/qat_dh895xcc.ko``
+.. Note::
-**Note**:The following warning in /var/log/messages can be ignored:
- ``IOMMU should be enabled for SR-IOV to work correctly``
+ If the QAT kernel modules are not loaded and you see an error like ``Failed
+ to load MMP firmware qat_895xcc_mmp.bin`` in kernel logs, this may be as a
+ result of not using a distribution, but just updating the kernel directly.
-For **Intel QuickAssist Technology C62x**:
-Assuming you are running on at least a 4.5 kernel, you can use the stock kernel.org QAT
-driver to start the QAT hardware.
+ Download firmware from the `kernel firmware repo
+ <http://git.kernel.org/cgit/linux/kernel/git/firmware/linux-firmware.git/tree/>`_.
-The steps below assume you are:
+ Copy qat binaries to ``/lib/firmware``::
-* Running DPDK on a platform with one ``C62x`` device.
-* On a kernel at least version 4.5.
+ cp qat_895xcc.bin /lib/firmware
+ cp qat_895xcc_mmp.bin /lib/firmware
-In BIOS ensure that SRIOV is enabled and either
-a) disable VT-d or
-b) enable VT-d and set ``"intel_iommu=on iommu=pt"`` in the grub file.
+ Change to your linux source root directory and start the qat kernel modules::
-Ensure the QAT driver is loaded on your system, by executing::
+ insmod ./drivers/crypto/qat/qat_common/intel_qat.ko
+ insmod ./drivers/crypto/qat/qat_dh895xcc/qat_dh895xcc.ko
- lsmod | grep qat
-You should see the following output::
+.. Note::
- qat_c62x 16384 0
- intel_qat 122880 1 qat_c62x
+ If you see the following warning in ``/var/log/messages`` it can be ignored:
+ ``IOMMU should be enabled for SR-IOV to work correctly``.
-Next, you need to expose the VFs using the sysfs file system.
-First find the bdf of the C62x device::
+Installation using 01.org QAT driver
+------------------------------------
- lspci -d:37c8
+Download the latest QuickAssist Technology Driver from `01.org
+<https://01.org/packet-processing/intel%C2%AE-quickassist-technology-drivers-and-patches>`_.
+Consult the *Getting Started Guide* at the same URL for further information.
-You should see output similar to::
+The steps below assume you are:
- 1a:00.0 Co-processor: Intel Corporation Device 37c8
- 3d:00.0 Co-processor: Intel Corporation Device 37c8
- 3f:00.0 Co-processor: Intel Corporation Device 37c8
+* Building on a platform with one ``DH895xCC`` device.
+* Using package ``qatmux.l.2.3.0-34.tgz``.
+* On Fedora21 kernel ``3.17.4-301.fc21.x86_64``.
-For each c62x device there are 3 PFs.
-Using the sysfs, for each PF, enable the 16 VFs::
+In the BIOS ensure that SRIOV is enabled and VT-d is disabled.
- echo 16 > /sys/bus/pci/drivers/c6xx/0000\:1a\:00.0/sriov_numvfs
+Uninstall any existing QAT driver, for example by running:
-If you get an error, it's likely you're using a QAT kernel driver earlier than kernel 4.5.
+* ``./installer.sh uninstall`` in the directory where originally installed.
-To verify that the VFs are available for use - use ``lspci -d:37c9`` to confirm
-the bdf of the 48 VF devices are available per ``C62x`` device.
+* or ``rmmod qat_dh895xcc; rmmod intel_qat``.
-To complete the installation - follow instructions in `Binding the available VFs to the DPDK UIO driver`_.
+Build and install the SRIOV-enabled QAT driver::
-For **Intel QuickAssist Technology C3xxx**:
-Assuming you are running on at least a 4.5 kernel, you can use the stock kernel.org QAT
-driver to start the QAT hardware.
+ mkdir /QAT
+ cd /QAT
-The steps below assume you are:
+ # Copy qatmux.l.2.3.0-34.tgz to this location
+ tar zxof qatmux.l.2.3.0-34.tgz
-* Running DPDK on a platform with one ``C3xxx`` device.
-* On a kernel at least version 4.5.
+ export ICP_WITHOUT_IOMMU=1
+ ./installer.sh install QAT1.6 host
-In BIOS ensure that SRIOV is enabled and either
-a) disable VT-d or
-b) enable VT-d and set ``"intel_iommu=on iommu=pt"`` in the grub file.
+You can use ``cat /proc/icp_dh895xcc_dev0/version`` to confirm the driver is correctly installed.
+You can use ``lspci -d:443`` to confirm the of the 32 VF devices available per ``DH895xCC`` device.
-Ensure the QAT driver is loaded on your system, by executing::
+To complete the installation - follow instructions in `Binding the available VFs to the DPDK UIO driver`_.
- lsmod | grep qat
+.. Note::
-You should see the following output::
+ If using a later kernel and the build fails with an error relating to
+ ``strict_stroul`` not being available apply the following patch:
- qat_c3xxx 16384 0
- intel_qat 122880 1 qat_c3xxx
+ .. code-block:: diff
-Next, you need to expose the Virtual Functions (VFs) using the sysfs file system.
+ /QAT/QAT1.6/quickassist/utilities/downloader/Target_CoreLibs/uclo/include/linux/uclo_platform.h
+ + #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,18,5)
+ + #define STR_TO_64(str, base, num, endPtr) {endPtr=NULL; if (kstrtoul((str), (base), (num))) printk("Error strtoull convert %s\n", str); }
+ + #else
+ #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38)
+ #define STR_TO_64(str, base, num, endPtr) {endPtr=NULL; if (strict_strtoull((str), (base), (num))) printk("Error strtoull convert %s\n", str); }
+ #else
+ #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,25)
+ #define STR_TO_64(str, base, num, endPtr) {endPtr=NULL; strict_strtoll((str), (base), (num));}
+ #else
+ #define STR_TO_64(str, base, num, endPtr) \
+ do { \
+ if (str[0] == '-') \
+ { \
+ *(num) = -(simple_strtoull((str+1), &(endPtr), (base))); \
+ }else { \
+ *(num) = simple_strtoull((str), &(endPtr), (base)); \
+ } \
+ } while(0)
+ + #endif
+ #endif
+ #endif
-First find the bdf of the physical function (PF) of the C3xxx device
- lspci -d:19e2
+.. Note::
-You should see output similar to::
+ If the build fails due to missing header files you may need to do following::
- 01:00.0 Co-processor: Intel Corporation Device 19e2
+ sudo yum install zlib-devel
+ sudo yum install openssl-devel
-For c3xxx device there is 1 PFs.
-Using the sysfs, enable the 16 VFs::
+.. Note::
- echo 16 > /sys/bus/pci/drivers/c3xxx/0000\:01\:00.0/sriov_numvfs
+ If the build or install fails due to mismatching kernel sources you may need to do the following::
-If you get an error, it's likely you're using a QAT kernel driver earlier than kernel 4.5.
+ sudo yum install kernel-headers-`uname -r`
+ sudo yum install kernel-src-`uname -r`
+ sudo yum install kernel-devel-`uname -r`
-To verify that the VFs are available for use - use ``lspci -d:19e3`` to confirm
-the bdf of the 16 VF devices are available per ``C3xxx`` device.
-To complete the installation - follow instructions in `Binding the available VFs to the DPDK UIO driver`_.
Binding the available VFs to the DPDK UIO driver
------------------------------------------------
-For **Intel(R) QuickAssist Technology DH895xcc** device:
-The unbind command below assumes ``bdfs`` of ``03:01.00-03:04.07``, if yours are different adjust the unbind command below::
+Unbind the VFs from the stock driver so they can be bound to the uio driver.
- cd $RTE_SDK
- modprobe uio
- insmod ./build/kmod/igb_uio.ko
+For an Intel(R) QuickAssist Technology DH895xCC device
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
- for device in $(seq 1 4); do \
- for fn in $(seq 0 7); do \
- echo -n 0000:03:0${device}.${fn} > \
- /sys/bus/pci/devices/0000\:03\:0${device}.${fn}/driver/unbind; \
- done; \
- done
+The unbind command below assumes ``BDFs`` of ``03:01.00-03:04.07``, if your
+VFs are different adjust the unbind command below::
- echo "8086 0443" > /sys/bus/pci/drivers/igb_uio/new_id
+ for device in $(seq 1 4); do \
+ for fn in $(seq 0 7); do \
+ echo -n 0000:03:0${device}.${fn} > \
+ /sys/bus/pci/devices/0000\:03\:0${device}.${fn}/driver/unbind; \
+ done; \
+ done
-You can use ``lspci -vvd:443`` to confirm that all devices are now in use by igb_uio kernel driver.
+For an Intel(R) QuickAssist Technology C62x device
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-For **Intel(R) QuickAssist Technology C62x** device:
-The unbind command below assumes ``bdfs`` of ``1a:01.00-1a:02.07``, ``3d:01.00-3d:02.07`` and ``3f:01.00-3f:02.07``,
-if yours are different adjust the unbind command below::
+The unbind command below assumes ``BDFs`` of ``1a:01.00-1a:02.07``,
+``3d:01.00-3d:02.07`` and ``3f:01.00-3f:02.07``, if your VFs are different
+adjust the unbind command below::
- cd $RTE_SDK
- modprobe uio
- insmod ./build/kmod/igb_uio.ko
+ for device in $(seq 1 2); do \
+ for fn in $(seq 0 7); do \
+ echo -n 0000:1a:0${device}.${fn} > \
+ /sys/bus/pci/devices/0000\:1a\:0${device}.${fn}/driver/unbind; \
- for device in $(seq 1 2); do \
- for fn in $(seq 0 7); do \
- echo -n 0000:1a:0${device}.${fn} > \
- /sys/bus/pci/devices/0000\:1a\:0${device}.${fn}/driver/unbind; \
+ echo -n 0000:3d:0${device}.${fn} > \
+ /sys/bus/pci/devices/0000\:3d\:0${device}.${fn}/driver/unbind; \
- echo -n 0000:3d:0${device}.${fn} > \
- /sys/bus/pci/devices/0000\:3d\:0${device}.${fn}/driver/unbind; \
+ echo -n 0000:3f:0${device}.${fn} > \
+ /sys/bus/pci/devices/0000\:3f\:0${device}.${fn}/driver/unbind; \
+ done; \
+ done
- echo -n 0000:3f:0${device}.${fn} > \
- /sys/bus/pci/devices/0000\:3f\:0${device}.${fn}/driver/unbind; \
- done; \
- done
+For Intel(R) QuickAssist Technology C3xxx or D15xx device
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
- echo "8086 37c9" > /sys/bus/pci/drivers/igb_uio/new_id
+The unbind command below assumes ``BDFs`` of ``01:01.00-01:02.07``, if your
+VFs are different adjust the unbind command below::
-You can use ``lspci -vvd:37c9`` to confirm that all devices are now in use by igb_uio kernel driver.
+ for device in $(seq 1 2); do \
+ for fn in $(seq 0 7); do \
+ echo -n 0000:01:0${device}.${fn} > \
+ /sys/bus/pci/devices/0000\:01\:0${device}.${fn}/driver/unbind; \
+ done; \
+ done
-For **Intel(R) QuickAssist Technology C3xxx** device:
-The unbind command below assumes ``bdfs`` of ``01:01.00-01:02.07``,
-if yours are different adjust the unbind command below::
+Bind to the DPDK uio driver
+~~~~~~~~~~~~~~~~~~~~~~~~~~~
- cd $RTE_SDK
- modprobe uio
- insmod ./build/kmod/igb_uio.ko
+Install the DPDK igb_uio driver, bind the VF PCI Device id to it and use lspci
+to confirm the VF devices are now in use by igb_uio kernel driver,
+e.g. for the C62x device::
- for device in $(seq 1 2); do \
- for fn in $(seq 0 7); do \
- echo -n 0000:01:0${device}.${fn} > \
- /sys/bus/pci/devices/0000\:01\:0${device}.${fn}/driver/unbind; \
+ cd to the top-level DPDK directory
+ modprobe uio
+ insmod ./build/kmod/igb_uio.ko
+ echo "8086 37c9" > /sys/bus/pci/drivers/igb_uio/new_id
+ lspci -vvd:37c9
- done; \
- done
- echo "8086 19e3" > /sys/bus/pci/drivers/igb_uio/new_id
-
-You can use ``lspci -vvd:19e3`` to confirm that all devices are now in use by igb_uio kernel driver.
-
-
-The other way to bind the VFs to the DPDK UIO driver is by using the ``dpdk-devbind.py`` script:
-
-.. code-block:: console
+Another way to bind the VFs to the DPDK UIO driver is by using the
+``dpdk-devbind.py`` script::
- cd $RTE_SDK
- ./tools/dpdk-devbind.py -b igb_uio 0000:03:01.1
+ cd to the top-level DPDK directory
+ ./usertools/dpdk-devbind.py -b igb_uio 0000:03:01.1
diff --git a/doc/guides/cryptodevs/scheduler.rst b/doc/guides/cryptodevs/scheduler.rst
new file mode 100644
index 00000000..32e56537
--- /dev/null
+++ b/doc/guides/cryptodevs/scheduler.rst
@@ -0,0 +1,172 @@
+.. BSD LICENSE
+ Copyright(c) 2017 Intel Corporation. All rights reserved.
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions
+ are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+ * Neither the name of Intel Corporation nor the names of its
+ contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+Cryptodev Scheduler Poll Mode Driver Library
+============================================
+
+Scheduler PMD is a software crypto PMD, which has the capabilities of
+attaching hardware and/or software cryptodevs, and distributes ingress
+crypto ops among them in a certain manner.
+
+.. figure:: img/scheduler-overview.*
+
+ Cryptodev Scheduler Overview
+
+
+The Cryptodev Scheduler PMD library (**librte_pmd_crypto_scheduler**) acts as
+a software crypto PMD and shares the same API provided by librte_cryptodev.
+The PMD supports attaching multiple crypto PMDs, software or hardware, as
+slaves, and distributes the crypto workload to them with certain behavior.
+The behaviors are categorizes as different "modes". Basically, a scheduling
+mode defines certain actions for scheduling crypto ops to its slaves.
+
+The librte_pmd_crypto_scheduler library exports a C API which provides an API
+for attaching/detaching slaves, set/get scheduling modes, and enable/disable
+crypto ops reordering.
+
+Limitations
+-----------
+
+* Sessionless crypto operation is not supported
+* OOP crypto operation is not supported when the crypto op reordering feature
+ is enabled.
+
+
+Installation
+------------
+
+To build DPDK with CRYTPO_SCHEDULER_PMD the user is required to set
+CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER=y in config/common_base, and
+recompile DPDK
+
+
+Initialization
+--------------
+
+To use the PMD in an application, user must:
+
+* Call rte_vdev_init("crpyto_scheduler") within the application.
+
+* Use --vdev="crpyto_scheduler" in the EAL options, which will call
+ rte_vdev_init() internally.
+
+
+The following parameters (all optional) can be provided in the previous
+two calls:
+
+* socket_id: Specify the socket where the memory for the device is going
+ to be allocated (by default, socket_id will be the socket where the core
+ that is creating the PMD is running on).
+
+* max_nb_sessions: Specify the maximum number of sessions that can be
+ created. This value may be overwritten internally if there are too
+ many devices are attached.
+
+* slave: If a cryptodev has been initialized with specific name, it can be
+ attached to the scheduler using this parameter, simply filling the name
+ here. Multiple cryptodevs can be attached initially by presenting this
+ parameter multiple times.
+
+* mode: Specify the scheduling mode of the PMD. The supported scheduling
+ mode parameter values are specified in the "Cryptodev Scheduler Modes
+ Overview" section.
+
+* ordering: Specify the status of the crypto operations ordering feature.
+ The value of this parameter can be "enable" or "disable". This feature
+ is disabled by default.
+
+Example:
+
+.. code-block:: console
+
+ ... --vdev "crypto_aesni_mb_pmd,name=aesni_mb_1" --vdev "crypto_aesni_mb_pmd,name=aesni_mb_2" --vdev "crypto_scheduler_pmd,slave=aesni_mb_1,slave=aesni_mb_2" ...
+
+.. note::
+
+ * The scheduler cryptodev cannot be started unless the scheduling mode
+ is set and at least one slave is attached. Also, to configure the
+ scheduler in the run-time, like attach/detach slave(s), change
+ scheduling mode, or enable/disable crypto op ordering, one should stop
+ the scheduler first, otherwise an error will be returned.
+
+ * The crypto op reordering feature requires using the userdata field of
+ every mbuf to be processed to store temporary data. By the end of
+ processing, the field is set to pointing to NULL, any previously
+ stored value of this field will be lost.
+
+
+Cryptodev Scheduler Modes Overview
+----------------------------------
+
+Currently the Crypto Scheduler PMD library supports following modes of
+operation:
+
+* **CDEV_SCHED_MODE_ROUNDROBIN:**
+
+ *Initialization mode parameter*: **round-robin**
+
+ Round-robin mode, which distributes the enqueued burst of crypto ops
+ among its slaves in a round-robin manner. This mode may help to fill
+ the throughput gap between the physical core and the existing cryptodevs
+ to increase the overall performance.
+
+* **CDEV_SCHED_MODE_PKT_SIZE_DISTR:**
+
+ *Initialization mode parameter*: **packet-size-distr**
+
+ Packet-size based distribution mode, which works with 2 slaves, the primary
+ slave and the secondary slave, and distributes the enqueued crypto
+ operations to them based on their data lengths. A crypto operation will be
+ distributed to the primary slave if its data length is equal to or bigger
+ than the designated threshold, otherwise it will be handled by the secondary
+ slave.
+
+ A typical usecase in this mode is with the QAT cryptodev as the primary and
+ a software cryptodev as the secondary slave. This may help applications to
+ process additional crypto workload than what the QAT cryptodev can handle on
+ its own, by making use of the available CPU cycles to deal with smaller
+ crypto workloads.
+
+ The threshold is set to 128 bytes by default. It can be updated by calling
+ function **rte_cryptodev_scheduler_option_set**. The parameter of
+ **option_type** must be **CDEV_SCHED_OPTION_THRESHOLD** and **option** should
+ point to a rte_cryptodev_scheduler_threshold_option structure filled with
+ appropriate threshold value. Please NOTE this threshold has be a power-of-2
+ unsigned integer.
+
+* **CDEV_SCHED_MODE_FAILOVER:**
+
+ *Initialization mode parameter*: **fail-over**
+
+ Fail-over mode, which works with 2 slaves, the primary slave and the
+ secondary slave. In this mode, the scheduler will enqueue the incoming
+ crypto operation burst to the primary slave. When one or more crypto
+ operations fail to be enqueued, then they will be enqueued to the secondary
+ slave.
diff --git a/doc/guides/cryptodevs/snow3g.rst b/doc/guides/cryptodevs/snow3g.rst
index 75a08aab..12b6c4af 100644
--- a/doc/guides/cryptodevs/snow3g.rst
+++ b/doc/guides/cryptodevs/snow3g.rst
@@ -83,9 +83,9 @@ In order to enable this virtual crypto PMD, user must:
To use the PMD in an application, user must:
-* Call rte_eal_vdev_init("crypto_snow3g") within the application.
+* Call rte_vdev_init("crypto_snow3g") within the application.
-* Use --vdev="crypto_snow3g" in the EAL options, which will call rte_eal_vdev_init() internally.
+* Use --vdev="crypto_snow3g" in the EAL options, which will call rte_vdev_init() internally.
The following parameters (all optional) can be provided in the previous two calls:
@@ -100,4 +100,4 @@ Example:
.. code-block:: console
- ./l2fwd-crypto -c 40 -n 4 --vdev="crypto_snow3g,socket_id=1,max_nb_sessions=128"
+ ./l2fwd-crypto -l 6 -n 4 --vdev="crypto_snow3g,socket_id=1,max_nb_sessions=128"
diff --git a/doc/guides/cryptodevs/zuc.rst b/doc/guides/cryptodevs/zuc.rst
index 38d5068a..6deb11ab 100644
--- a/doc/guides/cryptodevs/zuc.rst
+++ b/doc/guides/cryptodevs/zuc.rst
@@ -91,9 +91,9 @@ In order to enable this virtual crypto PMD, user must:
To use the PMD in an application, user must:
-* Call rte_eal_vdev_init("crypto_zuc") within the application.
+* Call rte_vdev_init("crypto_zuc") within the application.
-* Use --vdev="crypto_zuc" in the EAL options, which will call rte_eal_vdev_init() internally.
+* Use --vdev="crypto_zuc" in the EAL options, which will call rte_vdev_init() internally.
The following parameters (all optional) can be provided in the previous two calls:
@@ -108,4 +108,4 @@ Example:
.. code-block:: console
- ./l2fwd-crypto -c 40 -n 4 --vdev="crypto_zuc,socket_id=1,max_nb_sessions=128"
+ ./l2fwd-crypto -l 6 -n 4 --vdev="crypto_zuc,socket_id=1,max_nb_sessions=128"