New upstream version 18.11.1

Change-Id: Ic52e74a9ed6f3ae06acea4a27357bd7153efc2a3
Signed-off-by: Christian Ehrhardt <christian.ehrhardt@canonical.com>

3 files changed, 21 insertions, 16 deletions

diff --git a/doc/guides/nics/i40e.rst b/doc/guides/nics/i40e.rst
index bfacbd11..40bf0f14 100644
--- a/doc/guides/nics/i40e.rst
+++ b/doc/guides/nics/i40e.rst
@@ -695,3 +695,9 @@ See :numref:`figure_intel_perf_test_setup` for the performance test setup.
    * Start creating a stream on packet generator.
 
    * Set the Ethernet II type to 0x0800.
+
+Tx bytes affected by the link status change
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+For firmware versions prior to 6.01 for X710 series and 3.33 for X722 series, the tx_bytes statistics data is affected by
+the link down event. Each time the link status changes to down, the tx_bytes decreases 110 bytes.
diff --git a/doc/guides/nics/ifc.rst b/doc/guides/nics/ifc.rst
index 48f9adf1..08fe1d23 100644
--- a/doc/guides/nics/ifc.rst
+++ b/doc/guides/nics/ifc.rst
@@ -19,9 +19,9 @@ Config File Options
 
 The following option can be modified in the ``config`` file.
 
-- ``CONFIG_RTE_LIBRTE_IFCVF_VDPA_PMD`` (default ``y`` for linux)
+- ``CONFIG_RTE_LIBRTE_IFC_PMD`` (default ``y`` for linux)
 
-  Toggle compilation of the ``librte_ifcvf_vdpa`` driver.
+  Toggle compilation of the ``librte_pmd_ifc`` driver.
 
 
 IFCVF vDPA Implementation
diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst
index 23f0f570..436898ac 100644
--- a/doc/guides/nics/mlx5.rst
+++ b/doc/guides/nics/mlx5.rst
@@ -227,20 +227,6 @@ Environment variables
   enabled and most useful when ``CONFIG_RTE_EAL_PMD_PATH`` is also set,
   since ``LD_LIBRARY_PATH`` has no effect in this case.
 
-- ``MLX5_PMD_ENABLE_PADDING``
-
-  Enables HW packet padding in PCI bus transactions.
-
-  When packet size is cache aligned and CRC stripping is enabled, 4 fewer
-  bytes are written to the PCI bus. Enabling padding makes such packets
-  aligned again.
-
-  In cases where PCI bandwidth is the bottleneck, padding can improve
-  performance by 10%.
-
-  This is disabled by default since this can also decrease performance for
-  unaligned packet sizes.
-
 - ``MLX5_SHUT_UP_BF``
 
   Configures HW Tx doorbell register as IO-mapped.
@@ -295,6 +281,19 @@ Run-time configuration
 
   - CPU having 128B cacheline with ConnectX-5 and Bluefield.
 
+- ``rxq_pkt_pad_en`` parameter [int]
+
+  A nonzero value enables padding Rx packet to the size of cacheline on PCI
+  transaction. This feature would waste PCI bandwidth but could improve
+  performance by avoiding partial cacheline write which may cause costly
+  read-modify-copy in memory transaction on some architectures. Disabled by
+  default.
+
+  Supported on:
+
+  - x86_64 with ConnectX-4, ConnectX-4 LX, ConnectX-5, ConnectX-6 and Bluefield.
+  - POWER8 and ARMv8 with ConnectX-4 LX, ConnectX-5, ConnectX-6 and Bluefield.
+
 - ``mprq_en`` parameter [int]
 
   A nonzero value enables configuring Multi-Packet Rx queues. Rx queue is