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| author |   Christian Ehrhardt <christian.ehrhardt@canonical.com> | 2017-05-16 14:51:32 +0200 |
|---|---|---|
| committer | Christian Ehrhardt <christian.ehrhardt@canonical.com> | 2017-05-16 16:20:45 +0200 |
| commit | 7595afa4d30097c1177b69257118d8ad89a539be (patch) | |
| tree | 4bfeadc905c977e45e54a90c42330553b8942e4e /doc/guides/sample_app_ug/qos_scheduler.rst | |
| parent | ce3d555e43e3795b5d9507fcfc76b7a0a92fd0d6 (diff) | |
Imported Upstream version 17.05
Change-Id: Id1e419c5a214e4a18739663b91f0f9a549f1fdc6
Signed-off-by: Christian Ehrhardt <christian.ehrhardt@canonical.com>
Diffstat (limited to 'doc/guides/sample_app_ug/qos_scheduler.rst')
| -rw-r--r-- | doc/guides/sample_app_ug/qos_scheduler.rst | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/doc/guides/sample_app_ug/qos_scheduler.rst b/doc/guides/sample_app_ug/qos_scheduler.rst index 7f9e9259..a6654cb5 100644 --- a/doc/guides/sample_app_ug/qos_scheduler.rst +++ b/doc/guides/sample_app_ug/qos_scheduler.rst @@ -289,7 +289,7 @@ The following is an example command with a single packet flow configuration: .. code-block:: console - ./qos_sched -c a2 -n 4 -- --pfc "3,2,5,7" --cfg ./profile.cfg + ./qos_sched -l 1,5,7 -n 4 -- --pfc "3,2,5,7" --cfg ./profile.cfg This example uses a single packet flow configuration which creates one RX thread on lcore 5 reading from port 3 and a worker thread on lcore 7 writing to port 2. @@ -298,12 +298,12 @@ Another example with 2 packet flow configurations using different ports but shar .. code-block:: console - ./qos_sched -c c6 -n 4 -- --pfc "3,2,2,6,7" --pfc "1,0,2,6,7" --cfg ./profile.cfg + ./qos_sched -l 1,2,6,7 -n 4 -- --pfc "3,2,2,6,7" --pfc "1,0,2,6,7" --cfg ./profile.cfg Note that independent cores for the packet flow configurations for each of the RX, WT and TX thread are also supported, providing flexibility to balance the work. -The EAL coremask is constrained to contain the default mastercore 1 and the RX, WT and TX cores only. +The EAL coremask/corelist is constrained to contain the default mastercore 1 and the RX, WT and TX cores only. Explanation ----------- |