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| author |   Luca Boccassi <luca.boccassi@gmail.com> | 2018-11-01 11:59:50 +0000 |
|---|---|---|
| committer | Luca Boccassi <luca.boccassi@gmail.com> | 2018-11-01 12:00:19 +0000 |
| commit | 8d01b9cd70a67cdafd5b965a70420c3bd7fb3f82 (patch) | |
| tree | 208e3bc33c220854d89d010e3abf720a2e62e546 /drivers/net/cxgbe/base/common.h | |
| parent | b63264c8342e6a1b6971c79550d2af2024b6a4de (diff) | |
New upstream version 18.11-rc1upstream/18.11-rc1
Change-Id: Iaa71986dd6332e878d8f4bf493101b2bbc6313bb
Signed-off-by: Luca Boccassi <luca.boccassi@gmail.com>
Diffstat (limited to 'drivers/net/cxgbe/base/common.h')
| -rw-r--r-- | drivers/net/cxgbe/base/common.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/net/cxgbe/base/common.h b/drivers/net/cxgbe/base/common.h index 157201da..fd200668 100644 --- a/drivers/net/cxgbe/base/common.h +++ b/drivers/net/cxgbe/base/common.h @@ -157,6 +157,7 @@ struct tp_params { int port_shift; int protocol_shift; int ethertype_shift; + int macmatch_shift; u64 hash_filter_mask; }; @@ -270,6 +271,7 @@ struct adapter_params { bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */ u8 fw_caps_support; /* 32-bit Port Capabilities */ + u8 filter2_wr_support; /* FW support for FILTER2_WR */ }; /* Firmware Port Capabilities types. @@ -388,6 +390,12 @@ int t4_free_vi(struct adapter *adap, unsigned int mbox, int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, int mtu, int promisc, int all_multi, int bcast, int vlanex, bool sleep_ok); +int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid, + const u8 *addr, const u8 *mask, unsigned int idx, + u8 lookup_type, u8 port_id, bool sleep_ok); +int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid, + const u8 *addr, const u8 *mask, unsigned int idx, + u8 lookup_type, u8 port_id, bool sleep_ok); int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, int idx, const u8 *addr, bool persist, bool add_smt); int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, |