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authorLuca Boccassi <luca.boccassi@gmail.com>2018-08-14 18:52:30 +0100
committerLuca Boccassi <luca.boccassi@gmail.com>2018-08-14 18:53:17 +0100
commitb63264c8342e6a1b6971c79550d2af2024b6a4de (patch)
tree83114aac64286fe616506c0b3dfaec2ab86ef835 /drivers/net/mvpp2/mrvl_ethdev.h
parentca33590b6af032bff57d9cc70455660466a654b2 (diff)
New upstream version 18.08upstream/18.08
Change-Id: I32fdf5e5016556d9c0a6d88ddaf1fc468961790a Signed-off-by: Luca Boccassi <luca.boccassi@gmail.com>
Diffstat (limited to 'drivers/net/mvpp2/mrvl_ethdev.h')
-rw-r--r--drivers/net/mvpp2/mrvl_ethdev.h109
1 files changed, 109 insertions, 0 deletions
diff --git a/drivers/net/mvpp2/mrvl_ethdev.h b/drivers/net/mvpp2/mrvl_ethdev.h
new file mode 100644
index 00000000..3726f788
--- /dev/null
+++ b/drivers/net/mvpp2/mrvl_ethdev.h
@@ -0,0 +1,109 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2017 Marvell International Ltd.
+ * Copyright(c) 2017 Semihalf.
+ * All rights reserved.
+ */
+
+#ifndef _MRVL_ETHDEV_H_
+#define _MRVL_ETHDEV_H_
+
+#include <rte_spinlock.h>
+#include <rte_flow_driver.h>
+
+#include <env/mv_autogen_comp_flags.h>
+#include <drivers/mv_pp2.h>
+#include <drivers/mv_pp2_bpool.h>
+#include <drivers/mv_pp2_cls.h>
+#include <drivers/mv_pp2_hif.h>
+#include <drivers/mv_pp2_ppio.h>
+
+/** Maximum number of rx queues per port */
+#define MRVL_PP2_RXQ_MAX 32
+
+/** Maximum number of tx queues per port */
+#define MRVL_PP2_TXQ_MAX 8
+
+/** Minimum number of descriptors in tx queue */
+#define MRVL_PP2_TXD_MIN 16
+
+/** Maximum number of descriptors in tx queue */
+#define MRVL_PP2_TXD_MAX 2048
+
+/** Tx queue descriptors alignment */
+#define MRVL_PP2_TXD_ALIGN 16
+
+/** Minimum number of descriptors in rx queue */
+#define MRVL_PP2_RXD_MIN 16
+
+/** Maximum number of descriptors in rx queue */
+#define MRVL_PP2_RXD_MAX 2048
+
+/** Rx queue descriptors alignment */
+#define MRVL_PP2_RXD_ALIGN 16
+
+/** Maximum number of descriptors in tx aggregated queue */
+#define MRVL_PP2_AGGR_TXQD_MAX 2048
+
+/** Maximum number of Traffic Classes. */
+#define MRVL_PP2_TC_MAX 8
+
+/** Packet offset inside RX buffer. */
+#define MRVL_PKT_OFFS 64
+
+/** Maximum number of descriptors in shadow queue. Must be power of 2 */
+#define MRVL_PP2_TX_SHADOWQ_SIZE MRVL_PP2_TXD_MAX
+
+/** Shadow queue size mask (since shadow queue size is power of 2) */
+#define MRVL_PP2_TX_SHADOWQ_MASK (MRVL_PP2_TX_SHADOWQ_SIZE - 1)
+
+/** Minimum number of sent buffers to release from shadow queue to BM */
+#define MRVL_PP2_BUF_RELEASE_BURST_SIZE 64
+
+struct mrvl_priv {
+ /* Hot fields, used in fast path. */
+ struct pp2_bpool *bpool; /**< BPool pointer */
+ struct pp2_ppio *ppio; /**< Port handler pointer */
+ rte_spinlock_t lock; /**< Spinlock for checking bpool status */
+ uint16_t bpool_max_size; /**< BPool maximum size */
+ uint16_t bpool_min_size; /**< BPool minimum size */
+ uint16_t bpool_init_size; /**< Configured BPool size */
+
+ /** Mapping for DPDK rx queue->(TC, MRVL relative inq) */
+ struct {
+ uint8_t tc; /**< Traffic Class */
+ uint8_t inq; /**< Relative in-queue number */
+ } rxq_map[MRVL_PP2_RXQ_MAX] __rte_cache_aligned;
+
+ /* Configuration data, used sporadically. */
+ uint8_t pp_id;
+ uint8_t ppio_id;
+ uint8_t bpool_bit;
+ uint8_t rss_hf_tcp;
+ uint8_t uc_mc_flushed;
+ uint8_t vlan_flushed;
+ uint8_t isolated;
+
+ struct pp2_ppio_params ppio_params;
+ struct pp2_cls_qos_tbl_params qos_tbl_params;
+ struct pp2_cls_tbl *qos_tbl;
+ uint16_t nb_rx_queues;
+
+ struct pp2_cls_tbl_params cls_tbl_params;
+ struct pp2_cls_tbl *cls_tbl;
+ uint32_t cls_tbl_pattern;
+ LIST_HEAD(mrvl_flows, rte_flow) flows;
+
+ struct pp2_cls_plcr *policer;
+};
+
+/** Flow operations forward declaration. */
+extern const struct rte_flow_ops mrvl_flow_ops;
+
+/** Current log type. */
+extern int mrvl_logtype;
+
+#define MRVL_LOG(level, fmt, args...) \
+ rte_log(RTE_LOG_ ## level, mrvl_logtype, "%s(): " fmt "\n", \
+ __func__, ##args)
+
+#endif /* _MRVL_ETHDEV_H_ */