diff options
| author |   Christian Ehrhardt <christian.ehrhardt@canonical.com> | 2017-05-16 14:51:32 +0200 |
|---|---|---|
| committer | Christian Ehrhardt <christian.ehrhardt@canonical.com> | 2017-05-16 16:20:45 +0200 |
| commit | 7595afa4d30097c1177b69257118d8ad89a539be (patch) | |
| tree | 4bfeadc905c977e45e54a90c42330553b8942e4e /drivers/net/qede/base/ecore_gtt_reg_addr.h | |
| parent | ce3d555e43e3795b5d9507fcfc76b7a0a92fd0d6 (diff) | |
Imported Upstream version 17.05
Change-Id: Id1e419c5a214e4a18739663b91f0f9a549f1fdc6
Signed-off-by: Christian Ehrhardt <christian.ehrhardt@canonical.com>
Diffstat (limited to 'drivers/net/qede/base/ecore_gtt_reg_addr.h')
| -rw-r--r-- | drivers/net/qede/base/ecore_gtt_reg_addr.h | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/drivers/net/qede/base/ecore_gtt_reg_addr.h b/drivers/net/qede/base/ecore_gtt_reg_addr.h index 6395b7cd..2acd864d 100644 --- a/drivers/net/qede/base/ecore_gtt_reg_addr.h +++ b/drivers/net/qede/base/ecore_gtt_reg_addr.h @@ -10,43 +10,43 @@ #define GTT_REG_ADDR_H /* Win 2 */ -/* Access:RW DataWidth:0x20 Chips: BB_A0 BB_B0 K2 */ +/* Access:RW DataWidth:0x20 */ #define GTT_BAR0_MAP_REG_IGU_CMD 0x00f000UL /* Win 3 */ -/* Access:RW DataWidth:0x20 Chips: BB_A0 BB_B0 K2 */ +/* Access:RW DataWidth:0x20 */ #define GTT_BAR0_MAP_REG_TSDM_RAM 0x010000UL /* Win 4 */ -/* Access:RW DataWidth:0x20 Chips: BB_A0 BB_B0 K2 */ +/* Access:RW DataWidth:0x20 */ #define GTT_BAR0_MAP_REG_MSDM_RAM 0x011000UL /* Win 5 */ -/* Access:RW DataWidth:0x20 Chips: BB_A0 BB_B0 K2 */ +/* Access:RW DataWidth:0x20 */ #define GTT_BAR0_MAP_REG_MSDM_RAM_1024 0x012000UL /* Win 6 */ -/* Access:RW DataWidth:0x20 Chips: BB_A0 BB_B0 K2 */ +/* Access:RW DataWidth:0x20 */ #define GTT_BAR0_MAP_REG_USDM_RAM 0x013000UL /* Win 7 */ -/* Access:RW DataWidth:0x20 Chips: BB_A0 BB_B0 K2 */ +/* Access:RW DataWidth:0x20 */ #define GTT_BAR0_MAP_REG_USDM_RAM_1024 0x014000UL /* Win 8 */ -/* Access:RW DataWidth:0x20 Chips: BB_A0 BB_B0 K2 */ +/* Access:RW DataWidth:0x20 */ #define GTT_BAR0_MAP_REG_USDM_RAM_2048 0x015000UL /* Win 9 */ -/* Access:RW DataWidth:0x20 Chips: BB_A0 BB_B0 K2 */ +/* Access:RW DataWidth:0x20 */ #define GTT_BAR0_MAP_REG_XSDM_RAM 0x016000UL /* Win 10 */ -/* Access:RW DataWidth:0x20 Chips: BB_A0 BB_B0 K2 */ +/* Access:RW DataWidth:0x20 */ #define GTT_BAR0_MAP_REG_YSDM_RAM 0x017000UL /* Win 11 */ -/* Access:RW DataWidth:0x20 Chips: BB_A0 BB_B0 K2 */ +/* Access:RW DataWidth:0x20 */ #define GTT_BAR0_MAP_REG_PSDM_RAM 0x018000UL #endif |