diff options
author | 2017-05-16 14:51:32 +0200 | |
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committer | 2017-05-16 14:51:32 +0200 | |
commit | fca143f059a0bddd7d47b8dc2df646a891b0eb0f (patch) | |
tree | 4bfeadc905c977e45e54a90c42330553b8942e4e /drivers/net/qede/qede_ethdev.h | |
parent | ce3d555e43e3795b5d9507fcfc76b7a0a92fd0d6 (diff) |
Imported Upstream version 17.05
Diffstat (limited to 'drivers/net/qede/qede_ethdev.h')
-rw-r--r-- | drivers/net/qede/qede_ethdev.h | 134 |
1 files changed, 99 insertions, 35 deletions
diff --git a/drivers/net/qede/qede_ethdev.h b/drivers/net/qede/qede_ethdev.h index a35ea8bd..e4323a0d 100644 --- a/drivers/net/qede/qede_ethdev.h +++ b/drivers/net/qede/qede_ethdev.h @@ -14,7 +14,9 @@ #include <rte_ether.h> #include <rte_ethdev.h> +#include <rte_ethdev_pci.h> #include <rte_dev.h> +#include <rte_ip.h> /* ecore includes */ #include "base/bcm_osal.h" @@ -31,6 +33,11 @@ #include "base/ecore_iov_api.h" #include "base/ecore_cxt.h" #include "base/nvm_cfg.h" +#include "base/ecore_iov_api.h" +#include "base/ecore_sp_commands.h" +#include "base/ecore_l2.h" +#include "base/ecore_dev_api.h" +#include "base/ecore_l2.h" #include "qede_logs.h" #include "qede_if.h" @@ -43,8 +50,8 @@ /* Driver versions */ #define QEDE_PMD_VER_PREFIX "QEDE PMD" -#define QEDE_PMD_VERSION_MAJOR 1 -#define QEDE_PMD_VERSION_MINOR 2 +#define QEDE_PMD_VERSION_MAJOR 2 +#define QEDE_PMD_VERSION_MINOR 4 #define QEDE_PMD_VERSION_REVISION 0 #define QEDE_PMD_VERSION_PATCH 1 @@ -89,27 +96,48 @@ struct ecore_dev *edev = &qdev->edev; \ } -/************* QLogic 25G/40G/100G vendor/devices ids *************/ -#define PCI_VENDOR_ID_QLOGIC 0x1077 - -#define CHIP_NUM_57980E 0x1634 -#define CHIP_NUM_57980S 0x1629 -#define CHIP_NUM_VF 0x1630 -#define CHIP_NUM_57980S_40 0x1634 -#define CHIP_NUM_57980S_25 0x1656 -#define CHIP_NUM_57980S_IOV 0x1664 -#define CHIP_NUM_57980S_100 0x1644 - -#define PCI_DEVICE_ID_NX2_57980E CHIP_NUM_57980E -#define PCI_DEVICE_ID_NX2_57980S CHIP_NUM_57980S -#define PCI_DEVICE_ID_NX2_VF CHIP_NUM_VF -#define PCI_DEVICE_ID_57980S_40 CHIP_NUM_57980S_40 -#define PCI_DEVICE_ID_57980S_25 CHIP_NUM_57980S_25 -#define PCI_DEVICE_ID_57980S_IOV CHIP_NUM_57980S_IOV -#define PCI_DEVICE_ID_57980S_100 CHIP_NUM_57980S_100 +/************* QLogic 10G/25G/40G/50G/100G vendor/devices ids *************/ +#define PCI_VENDOR_ID_QLOGIC 0x1077 + +#define CHIP_NUM_57980E 0x1634 +#define CHIP_NUM_57980S 0x1629 +#define CHIP_NUM_VF 0x1630 +#define CHIP_NUM_57980S_40 0x1634 +#define CHIP_NUM_57980S_25 0x1656 +#define CHIP_NUM_57980S_IOV 0x1664 +#define CHIP_NUM_57980S_100 0x1644 +#define CHIP_NUM_57980S_50 0x1654 +#define CHIP_NUM_AH_50G 0x8070 +#define CHIP_NUM_AH_10G 0x8071 +#define CHIP_NUM_AH_40G 0x8072 +#define CHIP_NUM_AH_25G 0x8073 +#define CHIP_NUM_AH_IOV 0x8090 + +#define PCI_DEVICE_ID_QLOGIC_NX2_57980E CHIP_NUM_57980E +#define PCI_DEVICE_ID_QLOGIC_NX2_57980S CHIP_NUM_57980S +#define PCI_DEVICE_ID_QLOGIC_NX2_VF CHIP_NUM_VF +#define PCI_DEVICE_ID_QLOGIC_57980S_40 CHIP_NUM_57980S_40 +#define PCI_DEVICE_ID_QLOGIC_57980S_25 CHIP_NUM_57980S_25 +#define PCI_DEVICE_ID_QLOGIC_57980S_IOV CHIP_NUM_57980S_IOV +#define PCI_DEVICE_ID_QLOGIC_57980S_100 CHIP_NUM_57980S_100 +#define PCI_DEVICE_ID_QLOGIC_57980S_50 CHIP_NUM_57980S_50 +#define PCI_DEVICE_ID_QLOGIC_AH_50G CHIP_NUM_AH_50G +#define PCI_DEVICE_ID_QLOGIC_AH_10G CHIP_NUM_AH_10G +#define PCI_DEVICE_ID_QLOGIC_AH_40G CHIP_NUM_AH_40G +#define PCI_DEVICE_ID_QLOGIC_AH_25G CHIP_NUM_AH_25G +#define PCI_DEVICE_ID_QLOGIC_AH_IOV CHIP_NUM_AH_IOV + + +#define QEDE_VXLAN_DEF_PORT 8472 extern char fw_file[]; +/* Number of PF connections - 32 RX + 32 TX */ +#define QEDE_PF_NUM_CONNS (64) + +/* Maximum number of flowdir filters */ +#define QEDE_RFS_MAX_FLTR (256) + /* Port/function states */ enum qede_dev_state { QEDE_DEV_INIT, /* Init the chip and Slowpath */ @@ -131,9 +159,25 @@ struct qede_mcast_entry { struct qede_ucast_entry { struct ether_addr mac; uint16_t vlan; + uint16_t vni; SLIST_ENTRY(qede_ucast_entry) list; }; +struct qede_fdir_entry { + uint32_t soft_id; /* unused for now */ + uint16_t pkt_len; /* actual packet length to match */ + uint16_t rx_queue; /* queue to be steered to */ + const struct rte_memzone *mz; /* mz used to hold L2 frame */ + SLIST_ENTRY(qede_fdir_entry) list; +}; + +struct qede_fdir_info { + struct ecore_arfs_config_params arfs; + uint16_t filter_count; + SLIST_HEAD(fdir_list_head, qede_fdir_entry)fdir_list_head; +}; + + /* * Structure to store private data for each port. */ @@ -146,10 +190,12 @@ struct qede_dev { struct qede_fastpath *fp_array; uint8_t num_tc; uint16_t mtu; - bool rss_enabled; - struct qed_update_vport_rss_params rss_params; - uint32_t flags; - bool gro_disable; + bool rss_enable; + struct rte_eth_rss_conf rss_conf; + uint16_t rss_ind_table[ECORE_RSS_IND_TABLE_SIZE]; + uint64_t rss_hf; + uint8_t rss_key_len; + bool enable_lro; uint16_t num_queues; uint8_t fp_num_tx; uint8_t fp_num_rx; @@ -163,25 +209,43 @@ struct qede_dev { SLIST_HEAD(uc_list_head, qede_ucast_entry) uc_list_head; uint16_t num_uc_addr; bool handle_hw_err; + uint16_t num_tunn_filters; + uint16_t vxlan_filter_type; + struct qede_fdir_info fdir_info; + bool vlan_strip_flg; char drv_ver[QEDE_PMD_DRV_VER_STR_SIZE]; }; -/* Static functions */ -static int qede_vlan_filter_set(struct rte_eth_dev *eth_dev, - uint16_t vlan_id, int on); - -static int qede_rss_hash_update(struct rte_eth_dev *eth_dev, - struct rte_eth_rss_conf *rss_conf); +/* Non-static functions */ +int qede_config_rss(struct rte_eth_dev *eth_dev); -static int qede_rss_reta_update(struct rte_eth_dev *eth_dev, - struct rte_eth_rss_reta_entry64 *reta_conf, - uint16_t reta_size); +int qede_rss_hash_update(struct rte_eth_dev *eth_dev, + struct rte_eth_rss_conf *rss_conf); -/* Non-static functions */ -void qede_init_rss_caps(uint8_t *rss_caps, uint64_t hf); +int qede_rss_reta_update(struct rte_eth_dev *eth_dev, + struct rte_eth_rss_reta_entry64 *reta_conf, + uint16_t reta_size); int qed_fill_eth_dev_info(struct ecore_dev *edev, struct qed_dev_eth_info *info); int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up); +int qede_dev_filter_ctrl(struct rte_eth_dev *dev, enum rte_filter_type type, + enum rte_filter_op op, void *arg); + +int qede_fdir_filter_conf(struct rte_eth_dev *eth_dev, + enum rte_filter_op filter_op, void *arg); + +int qede_ntuple_filter_conf(struct rte_eth_dev *eth_dev, + enum rte_filter_op filter_op, void *arg); + +int qede_check_fdir_support(struct rte_eth_dev *eth_dev); + +uint16_t qede_fdir_construct_pkt(struct rte_eth_dev *eth_dev, + struct rte_eth_fdir_filter *fdir, + void *buff, + struct ecore_arfs_config_params *params); + +void qede_fdir_dealloc_resc(struct rte_eth_dev *eth_dev); + #endif /* _QEDE_ETHDEV_H_ */ |