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authorLuca Boccassi <luca.boccassi@gmail.com>2018-02-19 11:16:57 +0000
committerLuca Boccassi <luca.boccassi@gmail.com>2018-02-19 11:17:28 +0000
commitca33590b6af032bff57d9cc70455660466a654b2 (patch)
tree0b68b090bd9b4a78a3614b62400b29279d76d553 /drivers/net/sfc/base/efx_impl.h
parent169a9de21e263aa6599cdc2d87a45ae158d9f509 (diff)
New upstream version 18.02upstream/18.02
Change-Id: I89ed24cb2a49b78fe5be6970b99dd46c1499fcc3 Signed-off-by: Luca Boccassi <luca.boccassi@gmail.com>
Diffstat (limited to 'drivers/net/sfc/base/efx_impl.h')
-rw-r--r--drivers/net/sfc/base/efx_impl.h117
1 files changed, 46 insertions, 71 deletions
diff --git a/drivers/net/sfc/base/efx_impl.h b/drivers/net/sfc/base/efx_impl.h
index 53fa37ac..ed685cba 100644
--- a/drivers/net/sfc/base/efx_impl.h
+++ b/drivers/net/sfc/base/efx_impl.h
@@ -1,31 +1,7 @@
-/*
- * Copyright (c) 2007-2016 Solarflare Communications Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
- * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
- * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
- * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+/* SPDX-License-Identifier: BSD-3-Clause
*
- * The views and conclusions contained in the software and documentation are
- * those of the authors and should not be interpreted as representing official
- * policies, either expressed or implied, of the FreeBSD Project.
+ * Copyright (c) 2007-2018 Solarflare Communications Inc.
+ * All rights reserved.
*/
#ifndef _SYS_EFX_IMPL_H
@@ -74,6 +50,7 @@ extern "C" {
#define EFX_MOD_MON 0x00000400
#define EFX_MOD_FILTER 0x00001000
#define EFX_MOD_LIC 0x00002000
+#define EFX_MOD_TUNNEL 0x00004000
#define EFX_RESET_PHY 0x00000001
#define EFX_RESET_RXQ_ERR 0x00000002
@@ -173,7 +150,7 @@ typedef struct efx_rx_ops_s {
unsigned int);
void (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
#if EFSYS_OPT_RX_PACKED_STREAM
- void (*erxo_qps_update_credits)(efx_rxq_t *);
+ void (*erxo_qpush_ps_credits)(efx_rxq_t *);
uint8_t * (*erxo_qps_packet_info)(efx_rxq_t *, uint8_t *,
uint32_t, uint32_t,
uint16_t *, uint32_t *, uint32_t *);
@@ -181,8 +158,9 @@ typedef struct efx_rx_ops_s {
efx_rc_t (*erxo_qflush)(efx_rxq_t *);
void (*erxo_qenable)(efx_rxq_t *);
efx_rc_t (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
- unsigned int, efx_rxq_type_t,
+ unsigned int, efx_rxq_type_t, uint32_t,
efsys_mem_t *, size_t, uint32_t,
+ unsigned int,
efx_evq_t *, efx_rxq_t *);
void (*erxo_qdestroy)(efx_rxq_t *);
} efx_rx_ops_t;
@@ -261,6 +239,12 @@ efx_filter_reconfigure(
#endif /* EFSYS_OPT_FILTER */
+#if EFSYS_OPT_TUNNEL
+typedef struct efx_tunnel_ops_s {
+ boolean_t (*eto_udp_encap_supported)(efx_nic_t *);
+ efx_rc_t (*eto_reconfigure)(efx_nic_t *);
+} efx_tunnel_ops_t;
+#endif /* EFSYS_OPT_TUNNEL */
typedef struct efx_port_s {
efx_mac_type_t ep_mac_type;
@@ -296,7 +280,6 @@ typedef struct efx_port_s {
uint32_t ep_default_adv_cap_mask;
uint32_t ep_phy_cap_mask;
boolean_t ep_mac_drain;
- boolean_t ep_mac_stats_pending;
#if EFSYS_OPT_BIST
efx_bist_type_t ep_current_bist;
#endif
@@ -358,12 +341,7 @@ typedef struct efx_nic_ops_s {
#ifndef EFX_RXQ_LIMIT_TARGET
#define EFX_RXQ_LIMIT_TARGET 512
#endif
-#ifndef EFX_TXQ_DC_SIZE
-#define EFX_TXQ_DC_SIZE 1 /* 16 descriptors */
-#endif
-#ifndef EFX_RXQ_DC_SIZE
-#define EFX_RXQ_DC_SIZE 3 /* 64 descriptors */
-#endif
+
#if EFSYS_OPT_FILTER
@@ -438,6 +416,22 @@ siena_filter_tbl_clear(
#if EFSYS_OPT_MCDI
+#define EFX_TUNNEL_MAXNENTRIES (16)
+
+#if EFSYS_OPT_TUNNEL
+
+typedef struct efx_tunnel_udp_entry_s {
+ uint16_t etue_port; /* host/cpu-endian */
+ uint16_t etue_protocol;
+} efx_tunnel_udp_entry_t;
+
+typedef struct efx_tunnel_cfg_s {
+ efx_tunnel_udp_entry_t etc_udp_entries[EFX_TUNNEL_MAXNENTRIES];
+ unsigned int etc_udp_entries_num;
+} efx_tunnel_cfg_t;
+
+#endif /* EFSYS_OPT_TUNNEL */
+
typedef struct efx_mcdi_ops_s {
efx_rc_t (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
void (*emco_send_request)(efx_nic_t *, void *, size_t,
@@ -461,6 +455,10 @@ typedef struct efx_mcdi_s {
#endif /* EFSYS_OPT_MCDI */
#if EFSYS_OPT_NVRAM
+
+/* Invalid partition ID for en_nvram_partn_locked field of efx_nc_t */
+#define EFX_NVRAM_PARTN_INVALID (0xffffffffu)
+
typedef struct efx_nvram_ops_s {
#if EFSYS_OPT_DIAG
efx_rc_t (*envo_test)(efx_nic_t *);
@@ -471,11 +469,14 @@ typedef struct efx_nvram_ops_s {
efx_rc_t (*envo_partn_rw_start)(efx_nic_t *, uint32_t, size_t *);
efx_rc_t (*envo_partn_read)(efx_nic_t *, uint32_t,
unsigned int, caddr_t, size_t);
+ efx_rc_t (*envo_partn_read_backup)(efx_nic_t *, uint32_t,
+ unsigned int, caddr_t, size_t);
efx_rc_t (*envo_partn_erase)(efx_nic_t *, uint32_t,
unsigned int, size_t);
efx_rc_t (*envo_partn_write)(efx_nic_t *, uint32_t,
unsigned int, caddr_t, size_t);
- efx_rc_t (*envo_partn_rw_finish)(efx_nic_t *, uint32_t);
+ efx_rc_t (*envo_partn_rw_finish)(efx_nic_t *, uint32_t,
+ uint32_t *);
efx_rc_t (*envo_partn_get_version)(efx_nic_t *, uint32_t,
uint32_t *, uint16_t *);
efx_rc_t (*envo_partn_set_version)(efx_nic_t *, uint32_t,
@@ -564,7 +565,7 @@ efx_mcdi_nvram_update_finish(
__in efx_nic_t *enp,
__in uint32_t partn,
__in boolean_t reboot,
- __out_opt uint32_t *resultp);
+ __out_opt uint32_t *verify_resultp);
#if EFSYS_OPT_DIAG
@@ -643,11 +644,15 @@ struct efx_nic_s {
efx_filter_t en_filter;
const efx_filter_ops_t *en_efop;
#endif /* EFSYS_OPT_FILTER */
+#if EFSYS_OPT_TUNNEL
+ efx_tunnel_cfg_t en_tunnel_cfg;
+ const efx_tunnel_ops_t *en_etop;
+#endif /* EFSYS_OPT_TUNNEL */
#if EFSYS_OPT_MCDI
efx_mcdi_t en_mcdi;
#endif /* EFSYS_OPT_MCDI */
#if EFSYS_OPT_NVRAM
- efx_nvram_type_t en_nvram_locked;
+ uint32_t en_nvram_partn_locked;
const efx_nvram_ops_t *en_envop;
#endif /* EFSYS_OPT_NVRAM */
#if EFSYS_OPT_VPD
@@ -754,6 +759,7 @@ struct efx_rxq_s {
unsigned int er_label;
unsigned int er_mask;
efsys_mem_t *er_esmp;
+ efx_evq_rxq_state_t *er_ev_qstate;
};
#define EFX_RXQ_MAGIC 0x15022005
@@ -1036,8 +1042,7 @@ struct efx_txq_s {
do { \
EFX_CHECK_REG((_enp), (_reg)); \
EFSYS_PROBE7(efx_bar_tbl_doorbell_writeo, \
- const char *, \
- #_reg, \
+ const char *, #_reg, \
uint32_t, (_index), \
uint32_t, _reg ## _OFST, \
uint32_t, (_eop)->eo_u32[3], \
@@ -1072,10 +1077,6 @@ struct efx_txq_s {
} while (B_FALSE)
extern __checkReturn efx_rc_t
-efx_nic_biu_test(
- __in efx_nic_t *enp);
-
-extern __checkReturn efx_rc_t
efx_mac_select(
__in efx_nic_t *enp);
@@ -1143,32 +1144,6 @@ efx_vpd_hunk_set(
#endif /* EFSYS_OPT_VPD */
-#if EFSYS_OPT_DIAG
-
-extern efx_sram_pattern_fn_t __efx_sram_pattern_fns[];
-
-typedef struct efx_register_set_s {
- unsigned int address;
- unsigned int step;
- unsigned int rows;
- efx_oword_t mask;
-} efx_register_set_t;
-
-extern __checkReturn efx_rc_t
-efx_nic_test_registers(
- __in efx_nic_t *enp,
- __in efx_register_set_t *rsp,
- __in size_t count);
-
-extern __checkReturn efx_rc_t
-efx_nic_test_tables(
- __in efx_nic_t *enp,
- __in efx_register_set_t *rsp,
- __in efx_pattern_type_t pattern,
- __in size_t count);
-
-#endif /* EFSYS_OPT_DIAG */
-
#if EFSYS_OPT_MCDI
extern __checkReturn efx_rc_t