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authorLuca Boccassi <luca.boccassi@gmail.com>2018-04-23 14:16:57 +0100
committerLuca Boccassi <luca.boccassi@gmail.com>2018-04-23 14:17:34 +0100
commit39157ec04095ab012d11db23c462844634bfbb8f (patch)
tree643f83dc46445aa7834fe271ce2c21a5cb278cee /lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h
parent47d9763a1dd3103d732da9eec350cfc1cd784717 (diff)
New upstream version 16.11.5upstream/16.11.5
Change-Id: I47171042629a57c6958d50251351e668ca5f3d8b Signed-off-by: Luca Boccassi <luca.boccassi@gmail.com>
Diffstat (limited to 'lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h')
-rw-r--r--lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h8
1 files changed, 4 insertions, 4 deletions
diff --git a/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h b/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h
index fb4fccb4..37f5eff2 100644
--- a/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h
+++ b/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h
@@ -64,9 +64,9 @@ extern "C" {
* occur before the STORE operations generated after.
*/
#ifdef RTE_ARCH_64
-#define rte_wmb() {asm volatile("lwsync" : : : "memory"); }
+#define rte_wmb() asm volatile("lwsync" : : : "memory")
#else
-#define rte_wmb() {asm volatile("sync" : : : "memory"); }
+#define rte_wmb() asm volatile("sync" : : : "memory")
#endif
/**
@@ -76,9 +76,9 @@ extern "C" {
* occur before the LOAD operations generated after.
*/
#ifdef RTE_ARCH_64
-#define rte_rmb() {asm volatile("lwsync" : : : "memory"); }
+#define rte_rmb() asm volatile("lwsync" : : : "memory")
#else
-#define rte_rmb() {asm volatile("sync" : : : "memory"); }
+#define rte_rmb() asm volatile("sync" : : : "memory")
#endif
#define rte_smp_mb() rte_mb()