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authorChristian Ehrhardt <christian.ehrhardt@canonical.com>2019-07-04 10:40:06 +0200
committerChristian Ehrhardt <christian.ehrhardt@canonical.com>2019-07-04 10:48:05 +0200
commit8d53e9f3c6001dcb2865f6e894da5b54e1418f88 (patch)
tree63907f21c13636a987d43463c675d0727a04e327 /lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h
parente2bea7436061ca2e7e14bfcfdc5870f2555c3965 (diff)
New upstream version 18.11.2upstream-18.11-stable
Change-Id: I23eb4f9179abf1f9c659891f8fddb27ee68ad26b Signed-off-by: Christian Ehrhardt <christian.ehrhardt@canonical.com>
Diffstat (limited to 'lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h')
-rw-r--r--lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h8
1 files changed, 0 insertions, 8 deletions
diff --git a/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h b/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h
index ce38350b..797381c0 100644
--- a/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h
+++ b/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h
@@ -63,11 +63,7 @@ extern "C" {
* Guarantees that the STORE operations generated before the barrier
* occur before the STORE operations generated after.
*/
-#ifdef RTE_ARCH_64
-#define rte_wmb() asm volatile("lwsync" : : : "memory")
-#else
#define rte_wmb() asm volatile("sync" : : : "memory")
-#endif
/**
* Read memory barrier.
@@ -75,11 +71,7 @@ extern "C" {
* Guarantees that the LOAD operations generated before the barrier
* occur before the LOAD operations generated after.
*/
-#ifdef RTE_ARCH_64
-#define rte_rmb() asm volatile("lwsync" : : : "memory")
-#else
#define rte_rmb() asm volatile("sync" : : : "memory")
-#endif
#define rte_smp_mb() rte_mb()