diff options
| author |   Ricardo Salveti <ricardo.salveti@linaro.org> | 2016-07-25 13:22:22 -0300 |
|---|---|---|
| committer | Ricardo Salveti <ricardo.salveti@linaro.org> | 2016-07-25 13:23:50 -0300 |
| commit | 7b53c036e6bf56623b8273018ff1c8cc62847857 (patch) | |
| tree | 4af0da8c150bbebd7d1d252d6ac801a7efef0d23 /lib/librte_eal/common/include/arch/ppc_64 | |
| parent | 5d4e5dcd8a186778b3d78e27c81550d07a288fd2 (diff) | |
Imported Upstream version 16.07-rc4
Change-Id: Ic57f6a3726f2dbd1682223648d91310f45705327
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
Diffstat (limited to 'lib/librte_eal/common/include/arch/ppc_64')
| -rw-r--r-- | lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h b/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h index feae4868..924e8940 100644 --- a/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h +++ b/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h @@ -62,7 +62,11 @@ extern "C" { * Guarantees that the STORE operations generated before the barrier * occur before the STORE operations generated after. */ +#ifdef RTE_ARCH_64 +#define rte_wmb() {asm volatile("lwsync" : : : "memory"); } +#else #define rte_wmb() {asm volatile("sync" : : : "memory"); } +#endif /** * Read memory barrier. @@ -70,13 +74,17 @@ extern "C" { * Guarantees that the LOAD operations generated before the barrier * occur before the LOAD operations generated after. */ +#ifdef RTE_ARCH_64 +#define rte_rmb() {asm volatile("lwsync" : : : "memory"); } +#else #define rte_rmb() {asm volatile("sync" : : : "memory"); } +#endif #define rte_smp_mb() rte_mb() -#define rte_smp_wmb() rte_compiler_barrier() +#define rte_smp_wmb() rte_wmb() -#define rte_smp_rmb() rte_compiler_barrier() +#define rte_smp_rmb() rte_rmb() /*------------------------- 16 bit atomic operations -------------------------*/ /* To be compatible with Power7, use GCC built-in functions for 16 bit |