diff options
author | 2018-06-18 13:36:41 +0200 | |
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committer | 2018-06-18 13:44:40 +0200 | |
commit | 82ecfad773dbce052e2b46a4712a88d2ac266b8a (patch) | |
tree | 61b675053cd2518d1cc287b3db03969f5fa43612 /lib/librte_eal/common/include/arch | |
parent | 547f5865f56b7a2277e00071d1c97d733140e418 (diff) |
New upstream version 17.11.3
Change-Id: Ic462f86fdc2d928727f49581036c19b7914c682b
Signed-off-by: Christian Ehrhardt <christian.ehrhardt@canonical.com>
Diffstat (limited to 'lib/librte_eal/common/include/arch')
-rw-r--r-- | lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h b/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h index 6993dd29..3a80311b 100644 --- a/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h +++ b/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h @@ -55,7 +55,7 @@ extern "C" { * Guarantees that the LOAD and STORE operations generated before the * barrier occur before the LOAD and STORE operations generated after. */ -#define rte_mb() {asm volatile("sync" : : : "memory"); } +#define rte_mb() asm volatile("sync" : : : "memory") /** * Write memory barrier. |