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Diffstat (limited to 'doc/guides/nics/mlx5.rst')
| -rw-r--r-- | doc/guides/nics/mlx5.rst | 27 |
1 files changed, 13 insertions, 14 deletions
diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index 23f0f570..436898ac 100644 --- a/doc/guides/nics/mlx5.rst +++ b/doc/guides/nics/mlx5.rst @@ -227,20 +227,6 @@ Environment variables enabled and most useful when ``CONFIG_RTE_EAL_PMD_PATH`` is also set, since ``LD_LIBRARY_PATH`` has no effect in this case. -- ``MLX5_PMD_ENABLE_PADDING`` - - Enables HW packet padding in PCI bus transactions. - - When packet size is cache aligned and CRC stripping is enabled, 4 fewer - bytes are written to the PCI bus. Enabling padding makes such packets - aligned again. - - In cases where PCI bandwidth is the bottleneck, padding can improve - performance by 10%. - - This is disabled by default since this can also decrease performance for - unaligned packet sizes. - - ``MLX5_SHUT_UP_BF`` Configures HW Tx doorbell register as IO-mapped. @@ -295,6 +281,19 @@ Run-time configuration - CPU having 128B cacheline with ConnectX-5 and Bluefield. +- ``rxq_pkt_pad_en`` parameter [int] + + A nonzero value enables padding Rx packet to the size of cacheline on PCI + transaction. This feature would waste PCI bandwidth but could improve + performance by avoiding partial cacheline write which may cause costly + read-modify-copy in memory transaction on some architectures. Disabled by + default. + + Supported on: + + - x86_64 with ConnectX-4, ConnectX-4 LX, ConnectX-5, ConnectX-6 and Bluefield. + - POWER8 and ARMv8 with ConnectX-4 LX, ConnectX-5, ConnectX-6 and Bluefield. + - ``mprq_en`` parameter [int] A nonzero value enables configuring Multi-Packet Rx queues. Rx queue is |