diff options
Diffstat (limited to 'drivers/bus/fslmc/portal')
| -rw-r--r-- | drivers/bus/fslmc/portal/dpaa2_hw_dpbp.c | 46 | ||||
| -rw-r--r-- | drivers/bus/fslmc/portal/dpaa2_hw_dpci.c | 179 | ||||
| -rw-r--r-- | drivers/bus/fslmc/portal/dpaa2_hw_dpio.c | 209 | ||||
| -rw-r--r-- | drivers/bus/fslmc/portal/dpaa2_hw_dpio.h | 7 | ||||
| -rw-r--r-- | drivers/bus/fslmc/portal/dpaa2_hw_pvt.h | 114 |
5 files changed, 465 insertions, 90 deletions
diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_dpbp.c b/drivers/bus/fslmc/portal/dpaa2_hw_dpbp.c index 2fb285c1..33f9eedf 100644 --- a/drivers/bus/fslmc/portal/dpaa2_hw_dpbp.c +++ b/drivers/bus/fslmc/portal/dpaa2_hw_dpbp.c @@ -2,7 +2,7 @@ * BSD LICENSE * * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved. - * Copyright (c) 2016 NXP. All rights reserved. + * Copyright 2016 NXP. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -53,29 +53,20 @@ #include "portal/dpaa2_hw_pvt.h" #include "portal/dpaa2_hw_dpio.h" -TAILQ_HEAD(dpbp_device_list, dpaa2_dpbp_dev); -static struct dpbp_device_list *dpbp_dev_list; /*!< DPBP device list */ +TAILQ_HEAD(dpbp_dev_list, dpaa2_dpbp_dev); +static struct dpbp_dev_list dpbp_dev_list + = TAILQ_HEAD_INITIALIZER(dpbp_dev_list); /*!< DPBP device list */ -int -dpaa2_create_dpbp_device( - int dpbp_id) +static int +dpaa2_create_dpbp_device(struct fslmc_vfio_device *vdev __rte_unused, + struct vfio_device_info *obj_info __rte_unused, + int dpbp_id) { struct dpaa2_dpbp_dev *dpbp_node; int ret; - if (!dpbp_dev_list) { - dpbp_dev_list = malloc(sizeof(struct dpbp_device_list)); - if (!dpbp_dev_list) { - PMD_INIT_LOG(ERR, "Memory alloc failed in DPBP list\n"); - return -1; - } - /* Initialize the DPBP List */ - TAILQ_INIT(dpbp_dev_list); - } - /* Allocate DPAA2 dpbp handle */ - dpbp_node = (struct dpaa2_dpbp_dev *) - malloc(sizeof(struct dpaa2_dpbp_dev)); + dpbp_node = rte_malloc(NULL, sizeof(struct dpaa2_dpbp_dev), 0); if (!dpbp_node) { PMD_INIT_LOG(ERR, "Memory allocation failed for DPBP Device"); return -1; @@ -88,7 +79,7 @@ dpaa2_create_dpbp_device( if (ret) { PMD_INIT_LOG(ERR, "Resource alloc failure with err code: %d", ret); - free(dpbp_node); + rte_free(dpbp_node); return -1; } @@ -98,16 +89,16 @@ dpaa2_create_dpbp_device( PMD_INIT_LOG(ERR, "Failure cleaning dpbp device with" " error code %d\n", ret); dpbp_close(&dpbp_node->dpbp, CMD_PRI_LOW, dpbp_node->token); - free(dpbp_node); + rte_free(dpbp_node); return -1; } dpbp_node->dpbp_id = dpbp_id; rte_atomic16_init(&dpbp_node->in_use); - TAILQ_INSERT_HEAD(dpbp_dev_list, dpbp_node, next); + TAILQ_INSERT_TAIL(&dpbp_dev_list, dpbp_node, next); - PMD_INIT_LOG(DEBUG, "Buffer pool resource initialized %d", dpbp_id); + PMD_INIT_LOG(DEBUG, "DPAA2: Added [dpbp.%d]", dpbp_id); return 0; } @@ -117,7 +108,7 @@ struct dpaa2_dpbp_dev *dpaa2_alloc_dpbp_dev(void) struct dpaa2_dpbp_dev *dpbp_dev = NULL; /* Get DPBP dev handle from list using index */ - TAILQ_FOREACH(dpbp_dev, dpbp_dev_list, next) { + TAILQ_FOREACH(dpbp_dev, &dpbp_dev_list, next) { if (dpbp_dev && rte_atomic16_test_and_set(&dpbp_dev->in_use)) break; } @@ -130,10 +121,17 @@ void dpaa2_free_dpbp_dev(struct dpaa2_dpbp_dev *dpbp) struct dpaa2_dpbp_dev *dpbp_dev = NULL; /* Match DPBP handle and mark it free */ - TAILQ_FOREACH(dpbp_dev, dpbp_dev_list, next) { + TAILQ_FOREACH(dpbp_dev, &dpbp_dev_list, next) { if (dpbp_dev == dpbp) { rte_atomic16_dec(&dpbp_dev->in_use); return; } } } + +static struct rte_dpaa2_object rte_dpaa2_dpbp_obj = { + .object_id = DPAA2_MC_DPBP_DEVID, + .create = dpaa2_create_dpbp_device, +}; + +RTE_PMD_REGISTER_DPAA2_OBJECT(dpbp, rte_dpaa2_dpbp_obj); diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_dpci.c b/drivers/bus/fslmc/portal/dpaa2_hw_dpci.c new file mode 100644 index 00000000..478e4f7e --- /dev/null +++ b/drivers/bus/fslmc/portal/dpaa2_hw_dpci.c @@ -0,0 +1,179 @@ +/*- + * BSD LICENSE + * + * Copyright 2017 NXP. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Freescale Semiconductor, Inc nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include <unistd.h> +#include <stdio.h> +#include <sys/types.h> +#include <string.h> +#include <stdlib.h> +#include <fcntl.h> +#include <errno.h> + +#include <rte_malloc.h> +#include <rte_memcpy.h> +#include <rte_string_fns.h> +#include <rte_cycles.h> +#include <rte_kvargs.h> +#include <rte_dev.h> +#include <rte_ethdev.h> + +#include <fslmc_logs.h> +#include <fslmc_vfio.h> +#include <mc/fsl_dpci.h> +#include "portal/dpaa2_hw_pvt.h" +#include "portal/dpaa2_hw_dpio.h" + +TAILQ_HEAD(dpci_dev_list, dpaa2_dpci_dev); +static struct dpci_dev_list dpci_dev_list + = TAILQ_HEAD_INITIALIZER(dpci_dev_list); /*!< DPCI device list */ + +static int +rte_dpaa2_create_dpci_device(struct fslmc_vfio_device *vdev __rte_unused, + struct vfio_device_info *obj_info __rte_unused, + int dpci_id) +{ + struct dpaa2_dpci_dev *dpci_node; + struct dpci_attr attr; + struct dpci_rx_queue_cfg rx_queue_cfg; + struct dpci_rx_queue_attr rx_attr; + int ret, i; + + /* Allocate DPAA2 dpci handle */ + dpci_node = rte_malloc(NULL, sizeof(struct dpaa2_dpci_dev), 0); + if (!dpci_node) { + PMD_INIT_LOG(ERR, "Memory allocation failed for DPCI Device"); + return -1; + } + + /* Open the dpci object */ + dpci_node->dpci.regs = rte_mcp_ptr_list[MC_PORTAL_INDEX]; + ret = dpci_open(&dpci_node->dpci, + CMD_PRI_LOW, dpci_id, &dpci_node->token); + if (ret) { + PMD_INIT_LOG(ERR, "Resource alloc failure with err code: %d", + ret); + rte_free(dpci_node); + return -1; + } + + /* Get the device attributes */ + ret = dpci_get_attributes(&dpci_node->dpci, + CMD_PRI_LOW, dpci_node->token, &attr); + if (ret != 0) { + PMD_INIT_LOG(ERR, "Reading device failed with err code: %d", + ret); + rte_free(dpci_node); + return -1; + } + + /* Set up the Rx Queue */ + memset(&rx_queue_cfg, 0, sizeof(struct dpci_rx_queue_cfg)); + ret = dpci_set_rx_queue(&dpci_node->dpci, + CMD_PRI_LOW, + dpci_node->token, + 0, &rx_queue_cfg); + if (ret) { + PMD_INIT_LOG(ERR, "Setting Rx queue failed with err code: %d", + ret); + rte_free(dpci_node); + return -1; + } + + /* Enable the device */ + ret = dpci_enable(&dpci_node->dpci, + CMD_PRI_LOW, dpci_node->token); + if (ret != 0) { + PMD_INIT_LOG(ERR, "Enabling device failed with err code: %d", + ret); + rte_free(dpci_node); + return -1; + } + + for (i = 0; i < DPAA2_DPCI_MAX_QUEUES; i++) { + /* Get the Rx FQID's */ + ret = dpci_get_rx_queue(&dpci_node->dpci, + CMD_PRI_LOW, + dpci_node->token, i, + &rx_attr); + if (ret != 0) { + PMD_INIT_LOG(ERR, + "Reading device failed with err code: %d", + ret); + rte_free(dpci_node); + return -1; + } + + dpci_node->queue[i].fqid = rx_attr.fqid; + } + + dpci_node->dpci_id = dpci_id; + rte_atomic16_init(&dpci_node->in_use); + + TAILQ_INSERT_TAIL(&dpci_dev_list, dpci_node, next); + + PMD_INIT_LOG(DEBUG, "DPAA2: Added [dpci.%d]", dpci_id); + + return 0; +} + +struct dpaa2_dpci_dev *rte_dpaa2_alloc_dpci_dev(void) +{ + struct dpaa2_dpci_dev *dpci_dev = NULL; + + /* Get DPCI dev handle from list using index */ + TAILQ_FOREACH(dpci_dev, &dpci_dev_list, next) { + if (dpci_dev && rte_atomic16_test_and_set(&dpci_dev->in_use)) + break; + } + + return dpci_dev; +} + +void rte_dpaa2_free_dpci_dev(struct dpaa2_dpci_dev *dpci) +{ + struct dpaa2_dpci_dev *dpci_dev = NULL; + + /* Match DPCI handle and mark it free */ + TAILQ_FOREACH(dpci_dev, &dpci_dev_list, next) { + if (dpci_dev == dpci) { + rte_atomic16_dec(&dpci_dev->in_use); + return; + } + } +} + +static struct rte_dpaa2_object rte_dpaa2_dpci_obj = { + .object_id = DPAA2_MC_DPCI_DEVID, + .create = rte_dpaa2_create_dpci_device, +}; + +RTE_PMD_REGISTER_DPAA2_OBJECT(dpci, rte_dpaa2_dpci_obj); diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c index a1a58b9c..283441b4 100644 --- a/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c +++ b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c @@ -2,7 +2,7 @@ * BSD LICENSE * * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved. - * Copyright (c) 2016 NXP. All rights reserved. + * Copyright 2016 NXP. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -46,6 +46,8 @@ #include <sys/stat.h> #include <sys/mman.h> #include <sys/syscall.h> +#include <sys/epoll.h> +#include<sys/eventfd.h> #include <rte_mbuf.h> #include <rte_ethdev.h> @@ -55,20 +57,23 @@ #include <rte_cycles.h> #include <rte_kvargs.h> #include <rte_dev.h> -#include <rte_ethdev.h> #include <fslmc_logs.h> #include <fslmc_vfio.h> #include "dpaa2_hw_pvt.h" #include "dpaa2_hw_dpio.h" +#include <mc/fsl_dpmng.h> #define NUM_HOST_CPUS RTE_MAX_LCORE struct dpaa2_io_portal_t dpaa2_io_portal[RTE_MAX_LCORE]; RTE_DEFINE_PER_LCORE(struct dpaa2_io_portal_t, _dpaa2_io); -TAILQ_HEAD(dpio_device_list, dpaa2_dpio_dev); -static struct dpio_device_list *dpio_dev_list; /*!< DPIO device list */ +struct swp_active_dqs rte_global_active_dqs_list[NUM_MAX_SWP]; + +TAILQ_HEAD(dpio_dev_list, dpaa2_dpio_dev); +static struct dpio_dev_list dpio_dev_list + = TAILQ_HEAD_INITIALIZER(dpio_dev_list); /*!< DPIO device list */ static uint32_t io_space_count; /*Stashing Macros default for LS208x*/ @@ -102,6 +107,95 @@ dpaa2_core_cluster_sdest(int cpu_id) return dpaa2_core_cluster_base + x; } +static void dpaa2_affine_dpio_intr_to_respective_core(int32_t dpio_id) +{ +#define STRING_LEN 28 +#define COMMAND_LEN 50 + uint32_t cpu_mask = 1; + int ret; + size_t len = 0; + char *temp = NULL, *token = NULL; + char string[STRING_LEN], command[COMMAND_LEN]; + FILE *file; + + snprintf(string, STRING_LEN, "dpio.%d", dpio_id); + file = fopen("/proc/interrupts", "r"); + if (!file) { + PMD_DRV_LOG(WARNING, "Failed to open /proc/interrupts file\n"); + return; + } + while (getline(&temp, &len, file) != -1) { + if ((strstr(temp, string)) != NULL) { + token = strtok(temp, ":"); + break; + } + } + + if (!token) { + PMD_DRV_LOG(WARNING, "Failed to get interrupt id for dpio.%d\n", + dpio_id); + if (temp) + free(temp); + fclose(file); + return; + } + + cpu_mask = cpu_mask << rte_lcore_id(); + snprintf(command, COMMAND_LEN, "echo %X > /proc/irq/%s/smp_affinity", + cpu_mask, token); + ret = system(command); + if (ret < 0) + PMD_DRV_LOG(WARNING, + "Failed to affine interrupts on respective core\n"); + else + PMD_DRV_LOG(WARNING, " %s command is executed\n", command); + + free(temp); + fclose(file); +} + +static int dpaa2_dpio_intr_init(struct dpaa2_dpio_dev *dpio_dev) +{ + struct epoll_event epoll_ev; + int eventfd, dpio_epoll_fd, ret; + int threshold = 0x3, timeout = 0xFF; + + dpio_epoll_fd = epoll_create(1); + ret = rte_dpaa2_intr_enable(&dpio_dev->intr_handle, 0); + if (ret) { + PMD_DRV_LOG(ERR, "Interrupt registeration failed\n"); + return -1; + } + + if (getenv("DPAA2_PORTAL_INTR_THRESHOLD")) + threshold = atoi(getenv("DPAA2_PORTAL_INTR_THRESHOLD")); + + if (getenv("DPAA2_PORTAL_INTR_TIMEOUT")) + sscanf(getenv("DPAA2_PORTAL_INTR_TIMEOUT"), "%x", &timeout); + + qbman_swp_interrupt_set_trigger(dpio_dev->sw_portal, + QBMAN_SWP_INTERRUPT_DQRI); + qbman_swp_interrupt_clear_status(dpio_dev->sw_portal, 0xffffffff); + qbman_swp_interrupt_set_inhibit(dpio_dev->sw_portal, 0); + qbman_swp_dqrr_thrshld_write(dpio_dev->sw_portal, threshold); + qbman_swp_intr_timeout_write(dpio_dev->sw_portal, timeout); + + eventfd = dpio_dev->intr_handle.fd; + epoll_ev.events = EPOLLIN | EPOLLPRI | EPOLLET; + epoll_ev.data.fd = eventfd; + + ret = epoll_ctl(dpio_epoll_fd, EPOLL_CTL_ADD, eventfd, &epoll_ev); + if (ret < 0) { + PMD_DRV_LOG(ERR, "epoll_ctl failed\n"); + return -1; + } + dpio_dev->epoll_fd = dpio_epoll_fd; + + dpaa2_affine_dpio_intr_to_respective_core(dpio_dev->hw_id); + + return 0; +} + static int configure_dpio_qbman_swp(struct dpaa2_dpio_dev *dpio_dev) { @@ -147,8 +241,6 @@ configure_dpio_qbman_swp(struct dpaa2_dpio_dev *dpio_dev) } PMD_INIT_LOG(DEBUG, "Qbman Portal ID %d", attr.qbman_portal_id); - PMD_INIT_LOG(DEBUG, "Portal CE adr 0x%lX", attr.qbman_portal_ce_offset); - PMD_INIT_LOG(DEBUG, "Portal CI adr 0x%lX", attr.qbman_portal_ci_offset); /* Configure & setup SW portal */ p_des.block = NULL; @@ -166,19 +258,31 @@ configure_dpio_qbman_swp(struct dpaa2_dpio_dev *dpio_dev) return -1; } - PMD_INIT_LOG(DEBUG, "QBMan SW Portal 0x%p\n", dpio_dev->sw_portal); - return 0; } static int -dpaa2_configure_stashing(struct dpaa2_dpio_dev *dpio_dev) +dpaa2_configure_stashing(struct dpaa2_dpio_dev *dpio_dev, int cpu_id) { - int sdest; - int cpu_id, ret; + int sdest, ret; + static int first_time; + + /* find the SoC type for the first time */ + if (!first_time) { + struct mc_soc_version mc_plat_info = {0}; + + if (mc_get_soc_version(dpio_dev->dpio, + CMD_PRI_LOW, &mc_plat_info)) { + PMD_INIT_LOG(ERR, "\tmc_get_soc_version failed\n"); + } else if ((mc_plat_info.svr & 0xffff0000) == SVR_LS1080A) { + dpaa2_core_cluster_base = 0x02; + dpaa2_cluster_sz = 4; + PMD_INIT_LOG(DEBUG, "\tLS108x (A53) Platform Detected"); + } + first_time = 1; + } /* Set the Stashing Destination */ - cpu_id = rte_lcore_id(); if (cpu_id < 0) { cpu_id = rte_get_master_lcore(); if (cpu_id < 0) { @@ -188,8 +292,6 @@ dpaa2_configure_stashing(struct dpaa2_dpio_dev *dpio_dev) } /* Set the STASH Destination depending on Current CPU ID. * Valid values of SDEST are 4,5,6,7. Where, - * CPU 0-1 will have SDEST 4 - * CPU 2-3 will have SDEST 5.....and so on. */ sdest = dpaa2_core_cluster_sdest(cpu_id); @@ -203,16 +305,21 @@ dpaa2_configure_stashing(struct dpaa2_dpio_dev *dpio_dev) return -1; } + if (dpaa2_dpio_intr_init(dpio_dev)) { + PMD_DRV_LOG(ERR, "Interrupt registration failed for dpio\n"); + return -1; + } + return 0; } -static inline struct dpaa2_dpio_dev *dpaa2_get_qbman_swp(void) +struct dpaa2_dpio_dev *dpaa2_get_qbman_swp(int cpu_id) { struct dpaa2_dpio_dev *dpio_dev = NULL; int ret; /* Get DPIO dev handle from list using index */ - TAILQ_FOREACH(dpio_dev, dpio_dev_list, next) { + TAILQ_FOREACH(dpio_dev, &dpio_dev_list, next) { if (dpio_dev && rte_atomic16_test_and_set(&dpio_dev->ref_count)) break; } @@ -222,7 +329,7 @@ static inline struct dpaa2_dpio_dev *dpaa2_get_qbman_swp(void) PMD_DRV_LOG(DEBUG, "New Portal=0x%x (%d) affined thread - %lu", dpio_dev, dpio_dev->index, syscall(SYS_gettid)); - ret = dpaa2_configure_stashing(dpio_dev); + ret = dpaa2_configure_stashing(dpio_dev, cpu_id); if (ret) PMD_DRV_LOG(ERR, "dpaa2_configure_stashing failed"); @@ -262,7 +369,7 @@ dpaa2_affine_qbman_swp(void) } /* Populate the dpaa2_io_portal structure */ - dpaa2_io_portal[lcore_id].dpio_dev = dpaa2_get_qbman_swp(); + dpaa2_io_portal[lcore_id].dpio_dev = dpaa2_get_qbman_swp(lcore_id); if (dpaa2_io_portal[lcore_id].dpio_dev) { RTE_PER_LCORE(_dpaa2_io).dpio_dev @@ -308,7 +415,7 @@ dpaa2_affine_qbman_swp_sec(void) } /* Populate the dpaa2_io_portal structure */ - dpaa2_io_portal[lcore_id].sec_dpio_dev = dpaa2_get_qbman_swp(); + dpaa2_io_portal[lcore_id].sec_dpio_dev = dpaa2_get_qbman_swp(lcore_id); if (dpaa2_io_portal[lcore_id].sec_dpio_dev) { RTE_PER_LCORE(_dpaa2_io).sec_dpio_dev @@ -320,13 +427,14 @@ dpaa2_affine_qbman_swp_sec(void) } } -int +static int dpaa2_create_dpio_device(struct fslmc_vfio_device *vdev, struct vfio_device_info *obj_info, - int object_id) + int object_id) { struct dpaa2_dpio_dev *dpio_dev; struct vfio_region_info reg_info = { .argsz = sizeof(reg_info)}; + int vfio_dev_fd; if (obj_info->num_regions < NUM_DPIO_REGIONS) { PMD_INIT_LOG(ERR, "ERROR, Not sufficient number " @@ -334,80 +442,57 @@ dpaa2_create_dpio_device(struct fslmc_vfio_device *vdev, return -1; } - if (!dpio_dev_list) { - dpio_dev_list = malloc(sizeof(struct dpio_device_list)); - if (!dpio_dev_list) { - PMD_INIT_LOG(ERR, "Memory alloc failed in DPIO list\n"); - return -1; - } - - /* Initialize the DPIO List */ - TAILQ_INIT(dpio_dev_list); - } - - dpio_dev = malloc(sizeof(struct dpaa2_dpio_dev)); + dpio_dev = rte_malloc(NULL, sizeof(struct dpaa2_dpio_dev), + RTE_CACHE_LINE_SIZE); if (!dpio_dev) { PMD_INIT_LOG(ERR, "Memory allocation failed for DPIO Device\n"); return -1; } - PMD_DRV_LOG(INFO, "\t Aloocated DPIO [%p]", dpio_dev); dpio_dev->dpio = NULL; dpio_dev->hw_id = object_id; - dpio_dev->vfio_fd = vdev->fd; + dpio_dev->intr_handle.vfio_dev_fd = vdev->fd; rte_atomic16_init(&dpio_dev->ref_count); /* Using single portal for all devices */ dpio_dev->mc_portal = rte_mcp_ptr_list[MC_PORTAL_INDEX]; reg_info.index = 0; - if (ioctl(dpio_dev->vfio_fd, VFIO_DEVICE_GET_REGION_INFO, ®_info)) { + vfio_dev_fd = dpio_dev->intr_handle.vfio_dev_fd; + if (ioctl(vfio_dev_fd, VFIO_DEVICE_GET_REGION_INFO, ®_info)) { PMD_INIT_LOG(ERR, "vfio: error getting region info\n"); - free(dpio_dev); + rte_free(dpio_dev); return -1; } - PMD_DRV_LOG(DEBUG, "\t Region Offset = %llx", reg_info.offset); - PMD_DRV_LOG(DEBUG, "\t Region Size = %llx", reg_info.size); dpio_dev->ce_size = reg_info.size; dpio_dev->qbman_portal_ce_paddr = (uint64_t)mmap(NULL, reg_info.size, PROT_WRITE | PROT_READ, MAP_SHARED, - dpio_dev->vfio_fd, reg_info.offset); - - /* Create Mapping for QBMan Cache Enabled area. This is a fix for - * SMMU fault for DQRR statshing transaction. - */ - if (vfio_dmamap_mem_region(dpio_dev->qbman_portal_ce_paddr, - reg_info.offset, reg_info.size)) { - PMD_INIT_LOG(ERR, "DMAMAP for Portal CE area failed.\n"); - free(dpio_dev); - return -1; - } + vfio_dev_fd, reg_info.offset); reg_info.index = 1; - if (ioctl(dpio_dev->vfio_fd, VFIO_DEVICE_GET_REGION_INFO, ®_info)) { + if (ioctl(vfio_dev_fd, VFIO_DEVICE_GET_REGION_INFO, ®_info)) { PMD_INIT_LOG(ERR, "vfio: error getting region info\n"); - free(dpio_dev); + rte_free(dpio_dev); return -1; } - PMD_DRV_LOG(DEBUG, "\t Region Offset = %llx", reg_info.offset); - PMD_DRV_LOG(DEBUG, "\t Region Size = %llx", reg_info.size); dpio_dev->ci_size = reg_info.size; dpio_dev->qbman_portal_ci_paddr = (uint64_t)mmap(NULL, reg_info.size, PROT_WRITE | PROT_READ, MAP_SHARED, - dpio_dev->vfio_fd, reg_info.offset); + vfio_dev_fd, reg_info.offset); if (configure_dpio_qbman_swp(dpio_dev)) { PMD_INIT_LOG(ERR, "Fail to configure the dpio qbman portal for %d\n", dpio_dev->hw_id); - free(dpio_dev); + rte_free(dpio_dev); return -1; } io_space_count++; dpio_dev->index = io_space_count; - TAILQ_INSERT_HEAD(dpio_dev_list, dpio_dev, next); + TAILQ_INSERT_TAIL(&dpio_dev_list, dpio_dev, next); + PMD_INIT_LOG(DEBUG, "DPAA2: Added [dpio.%d]", object_id); return 0; } @@ -437,9 +522,15 @@ dpaa2_alloc_dq_storage(struct queue_storage_info_t *q_storage) } return 0; fail: - i -= 1; - while (i >= 0) + while (--i >= 0) rte_free(q_storage->dq_storage[i]); return -1; } + +static struct rte_dpaa2_object rte_dpaa2_dpio_obj = { + .object_id = DPAA2_MC_DPIO_DEVID, + .create = dpaa2_create_dpio_device, +}; + +RTE_PMD_REGISTER_DPAA2_OBJECT(dpio, rte_dpaa2_dpio_obj); diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_dpio.h b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.h index f2e11680..e845340c 100644 --- a/drivers/bus/fslmc/portal/dpaa2_hw_dpio.h +++ b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.h @@ -2,7 +2,7 @@ * BSD LICENSE * * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved. - * Copyright (c) 2016 NXP. All rights reserved. + * Copyright 2016 NXP. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -42,6 +42,7 @@ struct dpaa2_io_portal_t { struct dpaa2_dpio_dev *sec_dpio_dev; uint64_t net_tid; uint64_t sec_tid; + void *eventdev; }; /*! Global per thread DPIO portal */ @@ -53,6 +54,10 @@ RTE_DECLARE_PER_LCORE(struct dpaa2_io_portal_t, _dpaa2_io); #define DPAA2_PER_LCORE_SEC_DPIO RTE_PER_LCORE(_dpaa2_io).sec_dpio_dev #define DPAA2_PER_LCORE_SEC_PORTAL DPAA2_PER_LCORE_SEC_DPIO->sw_portal +extern struct dpaa2_io_portal_t dpaa2_io_portal[RTE_MAX_LCORE]; + +struct dpaa2_dpio_dev *dpaa2_get_qbman_swp(int cpu_id); + /* Affine a DPIO portal to current processing thread */ int dpaa2_affine_qbman_swp(void); diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h b/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h index c0223734..5d7a8282 100644 --- a/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h +++ b/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h @@ -2,7 +2,7 @@ * BSD LICENSE * * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved. - * Copyright (c) 2016 NXP. All rights reserved. + * Copyright 2016 NXP. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -34,6 +34,8 @@ #ifndef _DPAA2_HW_PVT_H_ #define _DPAA2_HW_PVT_H_ +#include <rte_eventdev.h> + #include <mc/fsl_mc_sys.h> #include <fsl_qbman_portal.h> @@ -46,6 +48,10 @@ #define lower_32_bits(x) ((uint32_t)(x)) #define upper_32_bits(x) ((uint32_t)(((x) >> 16) >> 16)) +#define SVR_LS1080A 0x87030000 +#define SVR_LS2080A 0x87010000 +#define SVR_LS2088A 0x87090000 + #ifndef ETH_VLAN_HLEN #define ETH_VLAN_HLEN 4 /** < Vlan Header Length */ #endif @@ -65,7 +71,7 @@ #define MAX_BPID 256 #define DPAA2_MBUF_HW_ANNOTATION 64 -#define DPAA2_FD_PTA_SIZE 64 +#define DPAA2_FD_PTA_SIZE 0 #if (DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE) > RTE_PKTMBUF_HEADROOM #error "Annotation requirement is more than RTE_PKTMBUF_HEADROOM" @@ -75,6 +81,8 @@ #define DPAA2_HW_BUF_RESERVE 0 #define DPAA2_PACKET_LAYOUT_ALIGN 64 /*changing from 256 */ +#define DPAA2_DPCI_MAX_QUEUES 2 + struct dpaa2_dpio_dev { TAILQ_ENTRY(dpaa2_dpio_dev) next; /**< Pointer to Next device instance */ @@ -93,8 +101,11 @@ struct dpaa2_dpio_dev { uintptr_t qbman_portal_ci_paddr; /**< Physical address of Cache Inhibit Area */ uintptr_t ci_size; /**< Size of the CI region */ - int32_t vfio_fd; /**< File descriptor received via VFIO */ + struct rte_intr_handle intr_handle; /* Interrupt related info */ + int32_t epoll_fd; /**< File descriptor created for interrupt polling */ int32_t hw_id; /**< An unique ID of this DPIO device instance */ + uint64_t dqrr_held; + uint8_t dqrr_size; }; struct dpaa2_dpbp_dev { @@ -108,8 +119,16 @@ struct dpaa2_dpbp_dev { struct queue_storage_info_t { struct qbman_result *dq_storage[NUM_DQS_PER_QUEUE]; + struct qbman_result *active_dqs; + int active_dpio_id; + int toggle; }; +typedef void (dpaa2_queue_cb_dqrr_t)(struct qbman_swp *swp, + const struct qbman_fd *fd, + const struct qbman_result *dq, + struct rte_event *ev); + struct dpaa2_queue { struct rte_mempool *mb_pool; /**< mbuf pool to populate RX ring. */ void *dev; @@ -120,7 +139,30 @@ struct dpaa2_queue { uint64_t rx_pkts; uint64_t tx_pkts; uint64_t err_pkts; - struct queue_storage_info_t *q_storage; + union { + struct queue_storage_info_t *q_storage; + struct qbman_result *cscn; + }; + dpaa2_queue_cb_dqrr_t *cb; +}; + +struct swp_active_dqs { + struct qbman_result *global_active_dqs; + uint64_t reserved[7]; +}; + +#define NUM_MAX_SWP 64 + +extern struct swp_active_dqs rte_global_active_dqs_list[NUM_MAX_SWP]; + +struct dpaa2_dpci_dev { + TAILQ_ENTRY(dpaa2_dpci_dev) next; + /**< Pointer to Next device instance */ + struct fsl_mc_io dpci; /** handle to DPCI portal object */ + uint16_t token; + rte_atomic16_t in_use; + uint32_t dpci_id; /*HW ID for DPCI object */ + struct dpaa2_queue queue[DPAA2_DPCI_MAX_QUEUES]; }; /*! Global MCP list */ @@ -137,6 +179,19 @@ struct qbman_fle { uint32_t reserved[3]; /* Not used currently */ }; +struct qbman_sge { + uint32_t addr_lo; + uint32_t addr_hi; + uint32_t length; + uint32_t fin_bpid_offset; +}; + +/* There are three types of frames: Single, Scatter Gather and Frame Lists */ +enum qbman_fd_format { + qbman_fd_single = 0, + qbman_fd_list, + qbman_fd_sg +}; /*Macros to define operations on FD*/ #define DPAA2_SET_FD_ADDR(fd, addr) do { \ fd->simple.addr_lo = lower_32_bits((uint64_t)(addr)); \ @@ -163,10 +218,17 @@ struct qbman_fle { fle->addr_lo = lower_32_bits((uint64_t)addr); \ fle->addr_hi = upper_32_bits((uint64_t)addr); \ } while (0) +#define DPAA2_GET_FLE_CTXT(fle) \ + (uint64_t)((((uint64_t)((fle)->reserved[1])) << 32) + \ + (fle)->reserved[0]) +#define DPAA2_FLE_SAVE_CTXT(fle, addr) do { \ + fle->reserved[0] = lower_32_bits((uint64_t)addr); \ + fle->reserved[1] = upper_32_bits((uint64_t)addr); \ +} while (0) #define DPAA2_SET_FLE_OFFSET(fle, offset) \ ((fle)->fin_bpid_offset |= (uint32_t)(offset) << 16) #define DPAA2_SET_FLE_BPID(fle, bpid) ((fle)->fin_bpid_offset |= (uint64_t)bpid) -#define DPAA2_GET_FLE_BPID(fle, bpid) (fle->fin_bpid_offset & 0x000000ff) +#define DPAA2_GET_FLE_BPID(fle) ((fle)->fin_bpid_offset & 0x000000ff) #define DPAA2_SET_FLE_FIN(fle) (fle->fin_bpid_offset |= (uint64_t)1 << 31) #define DPAA2_SET_FLE_IVP(fle) (((fle)->fin_bpid_offset |= 0x00004000)) #define DPAA2_SET_FD_COMPOUND_FMT(fd) \ @@ -178,6 +240,7 @@ struct qbman_fle { #define DPAA2_GET_FD_BPID(fd) (((fd)->simple.bpid_offset & 0x00003FFF)) #define DPAA2_GET_FD_IVP(fd) ((fd->simple.bpid_offset & 0x00004000) >> 14) #define DPAA2_GET_FD_OFFSET(fd) (((fd)->simple.bpid_offset & 0x0FFF0000) >> 16) +#define DPAA2_GET_FLE_OFFSET(fle) (((fle)->fin_bpid_offset & 0x0FFF0000) >> 16) #define DPAA2_SET_FLE_SG_EXT(fle) (fle->fin_bpid_offset |= (uint64_t)1 << 29) #define DPAA2_IS_SET_FLE_SG_EXT(fle) \ ((fle->fin_bpid_offset & ((uint64_t)1 << 29)) ? 1 : 0) @@ -187,6 +250,17 @@ struct qbman_fle { #define DPAA2_ASAL_VAL (DPAA2_MBUF_HW_ANNOTATION / 64) +#define DPAA2_FD_SET_FORMAT(fd, format) do { \ + (fd)->simple.bpid_offset &= 0xCFFFFFFF; \ + (fd)->simple.bpid_offset |= (uint32_t)format << 28; \ +} while (0) +#define DPAA2_FD_GET_FORMAT(fd) (((fd)->simple.bpid_offset >> 28) & 0x3) + +#define DPAA2_SG_SET_FINAL(sg, fin) do { \ + (sg)->fin_bpid_offset &= 0x7FFFFFFF; \ + (sg)->fin_bpid_offset |= (uint32_t)fin << 31; \ +} while (0) +#define DPAA2_SG_IS_FINAL(sg) (!!((sg)->fin_bpid_offset >> 31)) /* Only Enqueue Error responses will be * pushed on FQID_ERR of Enqueue FQ */ @@ -231,7 +305,7 @@ static phys_addr_t dpaa2_mem_vtop(uint64_t vaddr) /** * When we are using Physical addresses as IO Virtual Addresses, * Need to call conversion routines dpaa2_mem_vtop & dpaa2_mem_ptov - * whereever required. + * wherever required. * These routines are called with help of below MACRO's */ @@ -264,7 +338,35 @@ static phys_addr_t dpaa2_mem_vtop(uint64_t vaddr) #endif /* RTE_LIBRTE_DPAA2_USE_PHYS_IOVA */ +static inline +int check_swp_active_dqs(uint16_t dpio_index) +{ + if (rte_global_active_dqs_list[dpio_index].global_active_dqs != NULL) + return 1; + return 0; +} + +static inline +void clear_swp_active_dqs(uint16_t dpio_index) +{ + rte_global_active_dqs_list[dpio_index].global_active_dqs = NULL; +} + +static inline +struct qbman_result *get_swp_active_dqs(uint16_t dpio_index) +{ + return rte_global_active_dqs_list[dpio_index].global_active_dqs; +} + +static inline +void set_swp_active_dqs(uint16_t dpio_index, struct qbman_result *dqs) +{ + rte_global_active_dqs_list[dpio_index].global_active_dqs = dqs; +} struct dpaa2_dpbp_dev *dpaa2_alloc_dpbp_dev(void); void dpaa2_free_dpbp_dev(struct dpaa2_dpbp_dev *dpbp); +struct dpaa2_dpci_dev *rte_dpaa2_alloc_dpci_dev(void); +void rte_dpaa2_free_dpci_dev(struct dpaa2_dpci_dev *dpci); + #endif |