diff options
Diffstat (limited to 'drivers/net/bnx2x/bnx2x.h')
| -rw-r--r-- | drivers/net/bnx2x/bnx2x.h | 42 |
1 files changed, 28 insertions, 14 deletions
diff --git a/drivers/net/bnx2x/bnx2x.h b/drivers/net/bnx2x/bnx2x.h index 0f6024fb..74780725 100644 --- a/drivers/net/bnx2x/bnx2x.h +++ b/drivers/net/bnx2x/bnx2x.h @@ -725,6 +725,13 @@ struct bnx2x_port { uint32_t phy_addr; + /* Used to synchronize phy accesses. */ + rte_spinlock_t phy_mtx; + char phy_mtx_name[32]; + +#define BNX2X_PHY_LOCK(sc) rte_spinlock_lock(&sc->port.phy_mtx) +#define BNX2X_PHY_UNLOCK(sc) rte_spinlock_unlock(&sc->port.phy_mtx) + /* * MCP scratchpad address for port specific statistics. * The device is responsible for writing statistcss @@ -803,6 +810,10 @@ struct bnx2x_mf_info { /* Device information data structure. */ struct bnx2x_devinfo { +#if 1 +#define NAME_SIZE 128 + char name[NAME_SIZE]; +#endif /* PCIe info */ uint16_t vendor_id; uint16_t device_id; @@ -820,6 +831,7 @@ struct bnx2x_devinfo { #define CHIP_ID(sc) ((sc)->devinfo.chip_id & 0xffff0000) #define CHIP_NUM(sc) ((sc)->devinfo.chip_id >> 16) /* device ids */ +#define CHIP_NUM_57710 0x164e #define CHIP_NUM_57711 0x164f #define CHIP_NUM_57711E 0x1650 #define CHIP_NUM_57712 0x1662 @@ -861,6 +873,8 @@ struct bnx2x_devinfo { #define CHIP_METAL(sc) ((sc->devinfo.chip_id) & 0x00000ff0) #define CHIP_BOND_ID(sc) ((sc->devinfo.chip_id) & 0x0000000f) +#define CHIP_IS_E1(sc) (CHIP_NUM(sc) == CHIP_NUM_57710) +#define CHIP_IS_57710(sc) (CHIP_NUM(sc) == CHIP_NUM_57710) #define CHIP_IS_57711(sc) (CHIP_NUM(sc) == CHIP_NUM_57711) #define CHIP_IS_57711E(sc) (CHIP_NUM(sc) == CHIP_NUM_57711E) #define CHIP_IS_E1H(sc) ((CHIP_IS_57711(sc)) || \ @@ -1418,7 +1432,7 @@ struct bnx2x_func_init_params { static inline void bnx2x_reg_write8(struct bnx2x_softc *sc, size_t offset, uint8_t val) { - PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%02x", + PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "offset=0x%08lx val=0x%02x", (unsigned long)offset, val); rte_write8(val, ((uint8_t *)sc->bar[BAR0].base_addr + offset)); } @@ -1428,10 +1442,10 @@ bnx2x_reg_write16(struct bnx2x_softc *sc, size_t offset, uint16_t val) { #ifdef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC if ((offset % 2) != 0) - PMD_DRV_LOG(NOTICE, "Unaligned 16-bit write to 0x%08lx", + PMD_DRV_LOG(NOTICE, sc, "Unaligned 16-bit write to 0x%08lx", (unsigned long)offset); #endif - PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%04x", + PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "offset=0x%08lx val=0x%04x", (unsigned long)offset, val); rte_write16(val, ((uint8_t *)sc->bar[BAR0].base_addr + offset)); @@ -1442,11 +1456,11 @@ bnx2x_reg_write32(struct bnx2x_softc *sc, size_t offset, uint32_t val) { #ifdef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC if ((offset % 4) != 0) - PMD_DRV_LOG(NOTICE, "Unaligned 32-bit write to 0x%08lx", + PMD_DRV_LOG(NOTICE, sc, "Unaligned 32-bit write to 0x%08lx", (unsigned long)offset); #endif - PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%08x", + PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "offset=0x%08lx val=0x%08x", (unsigned long)offset, val); rte_write32(val, ((uint8_t *)sc->bar[BAR0].base_addr + offset)); } @@ -1457,7 +1471,7 @@ bnx2x_reg_read8(struct bnx2x_softc *sc, size_t offset) uint8_t val; val = rte_read8((uint8_t *)sc->bar[BAR0].base_addr + offset); - PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%02x", + PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "offset=0x%08lx val=0x%02x", (unsigned long)offset, val); return val; @@ -1470,12 +1484,12 @@ bnx2x_reg_read16(struct bnx2x_softc *sc, size_t offset) #ifdef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC if ((offset % 2) != 0) - PMD_DRV_LOG(NOTICE, "Unaligned 16-bit read from 0x%08lx", + PMD_DRV_LOG(NOTICE, sc, "Unaligned 16-bit read from 0x%08lx", (unsigned long)offset); #endif val = rte_read16(((uint8_t *)sc->bar[BAR0].base_addr + offset)); - PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%08x", + PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "offset=0x%08lx val=0x%08x", (unsigned long)offset, val); return val; @@ -1488,12 +1502,12 @@ bnx2x_reg_read32(struct bnx2x_softc *sc, size_t offset) #ifdef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC if ((offset % 4) != 0) - PMD_DRV_LOG(NOTICE, "Unaligned 32-bit read from 0x%08lx", + PMD_DRV_LOG(NOTICE, sc, "Unaligned 32-bit read from 0x%08lx", (unsigned long)offset); #endif val = rte_read32(((uint8_t *)sc->bar[BAR0].base_addr + offset)); - PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%08x", + PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "offset=0x%08lx val=0x%08x", (unsigned long)offset, val); return val; @@ -1970,7 +1984,7 @@ bnx2x_set_rx_mode(struct bnx2x_softc *sc) bnx2x_vf_set_rx_mode(sc); } } else { - PMD_DRV_LOG(NOTICE, "Card is not ready to change mode"); + PMD_DRV_LOG(NOTICE, sc, "Card is not ready to change mode"); } } @@ -1978,7 +1992,7 @@ static inline int pci_read(struct bnx2x_softc *sc, size_t addr, void *val, uint8_t size) { if (rte_pci_read_config(sc->pci_dev, val, size, addr) <= 0) { - PMD_DRV_LOG(ERR, "Can't read from PCI config space"); + PMD_DRV_LOG(ERR, sc, "Can't read from PCI config space"); return ENXIO; } @@ -1991,7 +2005,7 @@ static inline int pci_write_word(struct bnx2x_softc *sc, size_t addr, off_t val) if (rte_pci_write_config(sc->pci_dev, &val16, sizeof(val16), addr) <= 0) { - PMD_DRV_LOG(ERR, "Can't write to PCI config space"); + PMD_DRV_LOG(ERR, sc, "Can't write to PCI config space"); return ENXIO; } @@ -2003,7 +2017,7 @@ static inline int pci_write_long(struct bnx2x_softc *sc, size_t addr, off_t val) uint32_t val32 = val; if (rte_pci_write_config(sc->pci_dev, &val32, sizeof(val32), addr) <= 0) { - PMD_DRV_LOG(ERR, "Can't write to PCI config space"); + PMD_DRV_LOG(ERR, sc, "Can't write to PCI config space"); return ENXIO; } |