diff options
Diffstat (limited to 'drivers/net/bnx2x/elink.c')
| -rw-r--r-- | drivers/net/bnx2x/elink.c | 7908 |
1 files changed, 5024 insertions, 2884 deletions
diff --git a/drivers/net/bnx2x/elink.c b/drivers/net/bnx2x/elink.c index b63fd23e..d5693668 100644 --- a/drivers/net/bnx2x/elink.c +++ b/drivers/net/bnx2x/elink.c @@ -18,166 +18,159 @@ #include "ecore_hsi.h" #include "ecore_reg.h" -static elink_status_t elink_link_reset(struct elink_params *params, - struct elink_vars *vars, - uint8_t reset_ext_phy); -static elink_status_t elink_check_half_open_conn(struct elink_params *params, - struct elink_vars *vars, - uint8_t notify); -static elink_status_t elink_sfp_module_detection(struct elink_phy *phy, - struct elink_params *params); #define MDIO_REG_BANK_CL73_IEEEB0 0x0 -#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL 0x0 -#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN 0x0200 -#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN 0x1000 -#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST 0x8000 + #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL 0x0 + #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN 0x0200 + #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN 0x1000 + #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST 0x8000 #define MDIO_REG_BANK_CL73_IEEEB1 0x10 -#define MDIO_CL73_IEEEB1_AN_ADV1 0x00 -#define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE 0x0400 -#define MDIO_CL73_IEEEB1_AN_ADV1_ASYMMETRIC 0x0800 -#define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH 0x0C00 -#define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK 0x0C00 -#define MDIO_CL73_IEEEB1_AN_ADV2 0x01 -#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M 0x0000 -#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX 0x0020 -#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 0x0040 -#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR 0x0080 -#define MDIO_CL73_IEEEB1_AN_LP_ADV1 0x03 -#define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE 0x0400 -#define MDIO_CL73_IEEEB1_AN_LP_ADV1_ASYMMETRIC 0x0800 -#define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_BOTH 0x0C00 -#define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK 0x0C00 -#define MDIO_CL73_IEEEB1_AN_LP_ADV2 0x04 + #define MDIO_CL73_IEEEB1_AN_ADV1 0x00 + #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE 0x0400 + #define MDIO_CL73_IEEEB1_AN_ADV1_ASYMMETRIC 0x0800 + #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH 0x0C00 + #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK 0x0C00 + #define MDIO_CL73_IEEEB1_AN_ADV2 0x01 + #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M 0x0000 + #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX 0x0020 + #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 0x0040 + #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR 0x0080 + #define MDIO_CL73_IEEEB1_AN_LP_ADV1 0x03 + #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE 0x0400 + #define MDIO_CL73_IEEEB1_AN_LP_ADV1_ASYMMETRIC 0x0800 + #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_BOTH 0x0C00 + #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK 0x0C00 + #define MDIO_CL73_IEEEB1_AN_LP_ADV2 0x04 #define MDIO_REG_BANK_RX0 0x80b0 -#define MDIO_RX0_RX_STATUS 0x10 -#define MDIO_RX0_RX_STATUS_SIGDET 0x8000 -#define MDIO_RX0_RX_STATUS_RX_SEQ_DONE 0x1000 -#define MDIO_RX0_RX_EQ_BOOST 0x1c -#define MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 -#define MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL 0x10 + #define MDIO_RX0_RX_STATUS 0x10 + #define MDIO_RX0_RX_STATUS_SIGDET 0x8000 + #define MDIO_RX0_RX_STATUS_RX_SEQ_DONE 0x1000 + #define MDIO_RX0_RX_EQ_BOOST 0x1c + #define MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 + #define MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL 0x10 #define MDIO_REG_BANK_RX1 0x80c0 -#define MDIO_RX1_RX_EQ_BOOST 0x1c -#define MDIO_RX1_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 -#define MDIO_RX1_RX_EQ_BOOST_OFFSET_CTRL 0x10 + #define MDIO_RX1_RX_EQ_BOOST 0x1c + #define MDIO_RX1_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 + #define MDIO_RX1_RX_EQ_BOOST_OFFSET_CTRL 0x10 #define MDIO_REG_BANK_RX2 0x80d0 -#define MDIO_RX2_RX_EQ_BOOST 0x1c -#define MDIO_RX2_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 -#define MDIO_RX2_RX_EQ_BOOST_OFFSET_CTRL 0x10 + #define MDIO_RX2_RX_EQ_BOOST 0x1c + #define MDIO_RX2_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 + #define MDIO_RX2_RX_EQ_BOOST_OFFSET_CTRL 0x10 #define MDIO_REG_BANK_RX3 0x80e0 -#define MDIO_RX3_RX_EQ_BOOST 0x1c -#define MDIO_RX3_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 -#define MDIO_RX3_RX_EQ_BOOST_OFFSET_CTRL 0x10 + #define MDIO_RX3_RX_EQ_BOOST 0x1c + #define MDIO_RX3_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 + #define MDIO_RX3_RX_EQ_BOOST_OFFSET_CTRL 0x10 #define MDIO_REG_BANK_RX_ALL 0x80f0 -#define MDIO_RX_ALL_RX_EQ_BOOST 0x1c -#define MDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 -#define MDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL 0x10 + #define MDIO_RX_ALL_RX_EQ_BOOST 0x1c + #define MDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 + #define MDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL 0x10 #define MDIO_REG_BANK_TX0 0x8060 -#define MDIO_TX0_TX_DRIVER 0x17 -#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000 -#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12 -#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00 -#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8 -#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0 -#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4 -#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e -#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1 -#define MDIO_TX0_TX_DRIVER_ICBUF1T 1 + #define MDIO_TX0_TX_DRIVER 0x17 + #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000 + #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12 + #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00 + #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8 + #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0 + #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4 + #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e + #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1 + #define MDIO_TX0_TX_DRIVER_ICBUF1T 1 #define MDIO_REG_BANK_TX1 0x8070 -#define MDIO_TX1_TX_DRIVER 0x17 -#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000 -#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12 -#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00 -#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8 -#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0 -#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4 -#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e -#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1 -#define MDIO_TX0_TX_DRIVER_ICBUF1T 1 + #define MDIO_TX1_TX_DRIVER 0x17 + #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000 + #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12 + #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00 + #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8 + #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0 + #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4 + #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e + #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1 + #define MDIO_TX0_TX_DRIVER_ICBUF1T 1 #define MDIO_REG_BANK_TX2 0x8080 -#define MDIO_TX2_TX_DRIVER 0x17 -#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000 -#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12 -#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00 -#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8 -#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0 -#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4 -#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e -#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1 -#define MDIO_TX0_TX_DRIVER_ICBUF1T 1 + #define MDIO_TX2_TX_DRIVER 0x17 + #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000 + #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12 + #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00 + #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8 + #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0 + #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4 + #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e + #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1 + #define MDIO_TX0_TX_DRIVER_ICBUF1T 1 #define MDIO_REG_BANK_TX3 0x8090 -#define MDIO_TX3_TX_DRIVER 0x17 -#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000 -#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12 -#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00 -#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8 -#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0 -#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4 -#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e -#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1 -#define MDIO_TX0_TX_DRIVER_ICBUF1T 1 + #define MDIO_TX3_TX_DRIVER 0x17 + #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000 + #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12 + #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00 + #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8 + #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0 + #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4 + #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e + #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1 + #define MDIO_TX0_TX_DRIVER_ICBUF1T 1 #define MDIO_REG_BANK_XGXS_BLOCK0 0x8000 -#define MDIO_BLOCK0_XGXS_CONTROL 0x10 + #define MDIO_BLOCK0_XGXS_CONTROL 0x10 #define MDIO_REG_BANK_XGXS_BLOCK1 0x8010 -#define MDIO_BLOCK1_LANE_CTRL0 0x15 -#define MDIO_BLOCK1_LANE_CTRL1 0x16 -#define MDIO_BLOCK1_LANE_CTRL2 0x17 -#define MDIO_BLOCK1_LANE_PRBS 0x19 + #define MDIO_BLOCK1_LANE_CTRL0 0x15 + #define MDIO_BLOCK1_LANE_CTRL1 0x16 + #define MDIO_BLOCK1_LANE_CTRL2 0x17 + #define MDIO_BLOCK1_LANE_PRBS 0x19 #define MDIO_REG_BANK_XGXS_BLOCK2 0x8100 -#define MDIO_XGXS_BLOCK2_RX_LN_SWAP 0x10 -#define MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE 0x8000 -#define MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE 0x4000 -#define MDIO_XGXS_BLOCK2_TX_LN_SWAP 0x11 -#define MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE 0x8000 -#define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G 0x14 -#define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS 0x0001 -#define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS 0x0010 -#define MDIO_XGXS_BLOCK2_TEST_MODE_LANE 0x15 + #define MDIO_XGXS_BLOCK2_RX_LN_SWAP 0x10 + #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE 0x8000 + #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE 0x4000 + #define MDIO_XGXS_BLOCK2_TX_LN_SWAP 0x11 + #define MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE 0x8000 + #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G 0x14 + #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS 0x0001 + #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS 0x0010 + #define MDIO_XGXS_BLOCK2_TEST_MODE_LANE 0x15 #define MDIO_REG_BANK_GP_STATUS 0x8120 #define MDIO_GP_STATUS_TOP_AN_STATUS1 0x1B -#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE 0x0001 -#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE 0x0002 -#define MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS 0x0004 -#define MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS 0x0008 -#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE 0x0010 -#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE 0x0020 -#define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 0x0040 -#define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE 0x0080 -#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK 0x3f00 -#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M 0x0000 -#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M 0x0100 -#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G 0x0200 -#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G 0x0300 -#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G 0x0400 -#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G 0x0500 -#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG 0x0600 -#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 0x0700 -#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG 0x0800 -#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G 0x0900 -#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G 0x0A00 -#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G 0x0B00 -#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G 0x0C00 -#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 0x0D00 -#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 0x0E00 -#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR 0x0F00 -#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI 0x1B00 -#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS 0x1E00 -#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI 0x1F00 -#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2 0x3900 + #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE 0x0001 + #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE 0x0002 + #define MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS 0x0004 + #define MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS 0x0008 + #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE 0x0010 + #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE 0x0020 + #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 0x0040 + #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE 0x0080 + #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK 0x3f00 + #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M 0x0000 + #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M 0x0100 + #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G 0x0200 + #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G 0x0300 + #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G 0x0400 + #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G 0x0500 + #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG 0x0600 + #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 0x0700 + #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG 0x0800 + #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G 0x0900 + #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G 0x0A00 + #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G 0x0B00 + #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G 0x0C00 + #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 0x0D00 + #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 0x0E00 + #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR 0x0F00 + #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI 0x1B00 + #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS 0x1E00 + #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI 0x1F00 + #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2 0x3900 + #define MDIO_REG_BANK_10G_PARALLEL_DETECT 0x8130 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS 0x10 @@ -320,6 +313,7 @@ bit15=link,bit12=duplex,bits11:10=speed,bit14=acknowledge. Theotherbitsarereservedandshouldbezero*/ #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE 0x0001 + #define MDIO_PMA_DEVAD 0x1 /*ieee*/ #define MDIO_PMA_REG_CTRL 0x0 @@ -328,7 +322,7 @@ Theotherbitsarereservedandshouldbezero*/ #define MDIO_PMA_REG_TX_DISABLE 0x0009 #define MDIO_PMA_REG_RX_SD 0xa /*bnx2x*/ -#define MDIO_PMA_REG_BNX2X_CTRL 0x0096 +#define MDIO_PMA_REG_BCM_CTRL 0x0096 #define MDIO_PMA_REG_FEC_CTRL 0x00ab #define MDIO_PMA_LASI_RXCTRL 0x9000 #define MDIO_PMA_LASI_TXCTRL 0x9001 @@ -343,8 +337,8 @@ Theotherbitsarereservedandshouldbezero*/ #define MDIO_PMA_REG_CMU_PLL_BYPASS 0xca09 #define MDIO_PMA_REG_MISC_CTRL 0xca0a #define MDIO_PMA_REG_GEN_CTRL 0xca10 -#define MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP 0x0188 -#define MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET 0x018a + #define MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP 0x0188 + #define MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET 0x018a #define MDIO_PMA_REG_M8051_MSGIN_REG 0xca12 #define MDIO_PMA_REG_M8051_MSGOUT_REG 0xca13 #define MDIO_PMA_REG_ROM_VER1 0xca19 @@ -358,21 +352,21 @@ Theotherbitsarereservedandshouldbezero*/ #define MDIO_PMA_REG_MISC_CTRL1 0xca85 #define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL 0x8000 -#define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK 0x000c -#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE 0x0000 -#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE 0x0004 -#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IN_PROGRESS 0x0008 -#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_FAILED 0x000c +#define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK 0x000c +#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE 0x0000 +#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE 0x0004 +#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IN_PROGRESS 0x0008 +#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_FAILED 0x000c #define MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT 0x8002 #define MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR 0x8003 #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF 0xc820 -#define MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK 0xff + #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK 0xff #define MDIO_PMA_REG_8726_TX_CTRL1 0xca01 #define MDIO_PMA_REG_8726_TX_CTRL2 0xca05 #define MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR 0x8005 #define MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF 0x8007 -#define MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK 0xff + #define MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK 0xff #define MDIO_PMA_REG_8727_MISC_CTRL 0x8309 #define MDIO_PMA_REG_8727_TX_CTRL1 0xca02 #define MDIO_PMA_REG_8727_TX_CTRL2 0xca05 @@ -404,6 +398,8 @@ Theotherbitsarereservedandshouldbezero*/ #define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK 0x800 #define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT 11 + + #define MDIO_WIS_DEVAD 0x2 /*bnx2x*/ #define MDIO_WIS_REG_LASI_CNTL 0x9002 @@ -415,13 +411,15 @@ Theotherbitsarereservedandshouldbezero*/ #define MDIO_PCS_REG_7101_DSP_ACCESS 0xD000 #define MDIO_PCS_REG_7101_SPI_MUX 0xD008 #define MDIO_PCS_REG_7101_SPI_CTRL_ADDR 0xE12A -#define MDIO_PCS_REG_7101_SPI_RESET_BIT (5) + #define MDIO_PCS_REG_7101_SPI_RESET_BIT (5) #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR 0xE02A -#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD (6) -#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_BULK_ERASE_CMD (0xC7) -#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD (2) + #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD (6) + #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_BULK_ERASE_CMD (0xC7) + #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD (2) #define MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR 0xE028 + + #define MDIO_XS_DEVAD 0x4 #define MDIO_XS_REG_STATUS 0x0001 #define MDIO_XS_PLL_SEQUENCER 0x8000 @@ -439,12 +437,12 @@ Theotherbitsarereservedandshouldbezero*/ /*ieee*/ #define MDIO_AN_REG_CTRL 0x0000 #define MDIO_AN_REG_STATUS 0x0001 -#define MDIO_AN_REG_STATUS_AN_COMPLETE 0x0020 + #define MDIO_AN_REG_STATUS_AN_COMPLETE 0x0020 #define MDIO_AN_REG_ADV_PAUSE 0x0010 -#define MDIO_AN_REG_ADV_PAUSE_PAUSE 0x0400 -#define MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC 0x0800 -#define MDIO_AN_REG_ADV_PAUSE_BOTH 0x0C00 -#define MDIO_AN_REG_ADV_PAUSE_MASK 0x0C00 + #define MDIO_AN_REG_ADV_PAUSE_PAUSE 0x0400 + #define MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC 0x0800 + #define MDIO_AN_REG_ADV_PAUSE_BOTH 0x0C00 + #define MDIO_AN_REG_ADV_PAUSE_MASK 0x0C00 #define MDIO_AN_REG_ADV 0x0011 #define MDIO_AN_REG_ADV2 0x0012 #define MDIO_AN_REG_LP_AUTO_NEG 0x0013 @@ -465,13 +463,16 @@ Theotherbitsarereservedandshouldbezero*/ #define MDIO_AN_REG_8481_10GBASE_T_AN_CTRL 0x0020 #define MDIO_AN_REG_8481_LEGACY_MII_CTRL 0xffe0 -#define MDIO_AN_REG_8481_MII_CTRL_FORCE_1G 0x40 + #define MDIO_AN_REG_8481_MII_CTRL_FORCE_1G 0x40 #define MDIO_AN_REG_8481_LEGACY_MII_STATUS 0xffe1 +#define MDIO_AN_REG_848xx_ID_MSB 0xffe2 + #define BNX2X84858_PHY_ID 0x600d +#define MDIO_AN_REG_848xx_ID_LSB 0xffe3 #define MDIO_AN_REG_8481_LEGACY_AN_ADV 0xffe4 #define MDIO_AN_REG_8481_LEGACY_AN_EXPANSION 0xffe6 #define MDIO_AN_REG_8481_1000T_CTRL 0xffe9 #define MDIO_AN_REG_8481_1G_100T_EXT_CTRL 0xfff0 -#define MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF 0x0008 + #define MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF 0x0008 #define MDIO_AN_REG_8481_EXPANSION_REG_RD_RW 0xfff5 #define MDIO_AN_REG_8481_EXPANSION_REG_ACCESS 0xfff7 #define MDIO_AN_REG_8481_AUX_CTRL 0xfff8 @@ -480,62 +481,62 @@ Theotherbitsarereservedandshouldbezero*/ /* BNX2X84823 only */ #define MDIO_CTL_DEVAD 0x1e #define MDIO_CTL_REG_84823_MEDIA 0x401a -#define MDIO_CTL_REG_84823_MEDIA_MAC_MASK 0x0018 + #define MDIO_CTL_REG_84823_MEDIA_MAC_MASK 0x0018 /* These pins configure the BNX2X84823 interface to MAC after reset. */ -#define MDIO_CTL_REG_84823_CTRL_MAC_XFI 0x0008 -#define MDIO_CTL_REG_84823_MEDIA_MAC_XAUI_M 0x0010 + #define MDIO_CTL_REG_84823_CTRL_MAC_XFI 0x0008 + #define MDIO_CTL_REG_84823_MEDIA_MAC_XAUI_M 0x0010 /* These pins configure the BNX2X84823 interface to Line after reset. */ -#define MDIO_CTL_REG_84823_MEDIA_LINE_MASK 0x0060 -#define MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L 0x0020 -#define MDIO_CTL_REG_84823_MEDIA_LINE_XFI 0x0040 + #define MDIO_CTL_REG_84823_MEDIA_LINE_MASK 0x0060 + #define MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L 0x0020 + #define MDIO_CTL_REG_84823_MEDIA_LINE_XFI 0x0040 /* When this pin is active high during reset, 10GBASE-T core is power * down, When it is active low the 10GBASE-T is power up */ -#define MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN 0x0080 -#define MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK 0x0100 -#define MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER 0x0000 -#define MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER 0x0100 -#define MDIO_CTL_REG_84823_MEDIA_FIBER_1G 0x1000 + #define MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN 0x0080 + #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK 0x0100 + #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER 0x0000 + #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER 0x0100 + #define MDIO_CTL_REG_84823_MEDIA_FIBER_1G 0x1000 #define MDIO_CTL_REG_84823_USER_CTRL_REG 0x4005 -#define MDIO_CTL_REG_84823_USER_CTRL_CMS 0x0080 + #define MDIO_CTL_REG_84823_USER_CTRL_CMS 0x0080 #define MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH 0xa82b -#define MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ 0x2f + #define MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ 0x2f #define MDIO_PMA_REG_84823_CTL_LED_CTL_1 0xa8e3 #define MDIO_PMA_REG_84833_CTL_LED_CTL_1 0xa8ec -#define MDIO_PMA_REG_84823_LED3_STRETCH_EN 0x0080 + #define MDIO_PMA_REG_84823_LED3_STRETCH_EN 0x0080 /* BNX2X84833 only */ #define MDIO_84833_TOP_CFG_FW_REV 0x400f -#define MDIO_84833_TOP_CFG_FW_EEE 0x10b1 -#define MDIO_84833_TOP_CFG_FW_NO_EEE 0x1f81 +#define MDIO_84833_TOP_CFG_FW_EEE 0x10b1 +#define MDIO_84833_TOP_CFG_FW_NO_EEE 0x1f81 #define MDIO_84833_TOP_CFG_XGPHY_STRAP1 0x401a -#define MDIO_84833_SUPER_ISOLATE 0x8000 -/* These are mailbox register set used by 84833. */ -#define MDIO_84833_TOP_CFG_SCRATCH_REG0 0x4005 -#define MDIO_84833_TOP_CFG_SCRATCH_REG1 0x4006 -#define MDIO_84833_TOP_CFG_SCRATCH_REG2 0x4007 -#define MDIO_84833_TOP_CFG_SCRATCH_REG3 0x4008 -#define MDIO_84833_TOP_CFG_SCRATCH_REG4 0x4009 -#define MDIO_84833_TOP_CFG_SCRATCH_REG26 0x4037 -#define MDIO_84833_TOP_CFG_SCRATCH_REG27 0x4038 -#define MDIO_84833_TOP_CFG_SCRATCH_REG28 0x4039 -#define MDIO_84833_TOP_CFG_SCRATCH_REG29 0x403a -#define MDIO_84833_TOP_CFG_SCRATCH_REG30 0x403b -#define MDIO_84833_TOP_CFG_SCRATCH_REG31 0x403c -#define MDIO_84833_CMD_HDLR_COMMAND MDIO_84833_TOP_CFG_SCRATCH_REG0 -#define MDIO_84833_CMD_HDLR_STATUS MDIO_84833_TOP_CFG_SCRATCH_REG26 -#define MDIO_84833_CMD_HDLR_DATA1 MDIO_84833_TOP_CFG_SCRATCH_REG27 -#define MDIO_84833_CMD_HDLR_DATA2 MDIO_84833_TOP_CFG_SCRATCH_REG28 -#define MDIO_84833_CMD_HDLR_DATA3 MDIO_84833_TOP_CFG_SCRATCH_REG29 -#define MDIO_84833_CMD_HDLR_DATA4 MDIO_84833_TOP_CFG_SCRATCH_REG30 -#define MDIO_84833_CMD_HDLR_DATA5 MDIO_84833_TOP_CFG_SCRATCH_REG31 - -/* Mailbox command set used by 84833. */ -#define PHY84833_CMD_SET_PAIR_SWAP 0x8001 -#define PHY84833_CMD_GET_EEE_MODE 0x8008 -#define PHY84833_CMD_SET_EEE_MODE 0x8009 -#define PHY84833_CMD_GET_CURRENT_TEMP 0x8031 -/* Mailbox status set used by 84833. */ +#define MDIO_84833_SUPER_ISOLATE 0x8000 +/* These are mailbox register set used by 84833/84858. */ +#define MDIO_848xx_TOP_CFG_SCRATCH_REG0 0x4005 +#define MDIO_848xx_TOP_CFG_SCRATCH_REG1 0x4006 +#define MDIO_848xx_TOP_CFG_SCRATCH_REG2 0x4007 +#define MDIO_848xx_TOP_CFG_SCRATCH_REG3 0x4008 +#define MDIO_848xx_TOP_CFG_SCRATCH_REG4 0x4009 +#define MDIO_848xx_TOP_CFG_SCRATCH_REG26 0x4037 +#define MDIO_848xx_TOP_CFG_SCRATCH_REG27 0x4038 +#define MDIO_848xx_TOP_CFG_SCRATCH_REG28 0x4039 +#define MDIO_848xx_TOP_CFG_SCRATCH_REG29 0x403a +#define MDIO_848xx_TOP_CFG_SCRATCH_REG30 0x403b +#define MDIO_848xx_TOP_CFG_SCRATCH_REG31 0x403c +#define MDIO_848xx_CMD_HDLR_COMMAND (MDIO_848xx_TOP_CFG_SCRATCH_REG0) +#define MDIO_848xx_CMD_HDLR_STATUS (MDIO_848xx_TOP_CFG_SCRATCH_REG26) +#define MDIO_848xx_CMD_HDLR_DATA1 (MDIO_848xx_TOP_CFG_SCRATCH_REG27) +#define MDIO_848xx_CMD_HDLR_DATA2 (MDIO_848xx_TOP_CFG_SCRATCH_REG28) +#define MDIO_848xx_CMD_HDLR_DATA3 (MDIO_848xx_TOP_CFG_SCRATCH_REG29) +#define MDIO_848xx_CMD_HDLR_DATA4 (MDIO_848xx_TOP_CFG_SCRATCH_REG30) +#define MDIO_848xx_CMD_HDLR_DATA5 (MDIO_848xx_TOP_CFG_SCRATCH_REG31) + +/* Mailbox command set used by 84833/84858 */ +#define PHY848xx_CMD_SET_PAIR_SWAP 0x8001 +#define PHY848xx_CMD_GET_EEE_MODE 0x8008 +#define PHY848xx_CMD_SET_EEE_MODE 0x8009 +#define PHY848xx_CMD_GET_CURRENT_TEMP 0x8031 +/* Mailbox status set used by 84833 only */ #define PHY84833_STATUS_CMD_RECEIVED 0x0001 #define PHY84833_STATUS_CMD_IN_PROGRESS 0x0002 #define PHY84833_STATUS_CMD_COMPLETE_PASS 0x0004 @@ -545,6 +546,19 @@ Theotherbitsarereservedandshouldbezero*/ #define PHY84833_STATUS_CMD_NOT_OPEN_FOR_CMDS 0x0040 #define PHY84833_STATUS_CMD_CLEAR_COMPLETE 0x0080 #define PHY84833_STATUS_CMD_OPEN_OVERRIDE 0xa5a5 +/* Mailbox Process */ +#define PHY84833_MB_PROCESS1 1 +#define PHY84833_MB_PROCESS2 2 +#define PHY84833_MB_PROCESS3 3 + + +/* Mailbox status set used by 84858 only */ +#define PHY84858_STATUS_CMD_RECEIVED 0x0001 +#define PHY84858_STATUS_CMD_IN_PROGRESS 0x0002 +#define PHY84858_STATUS_CMD_COMPLETE_PASS 0x0004 +#define PHY84858_STATUS_CMD_COMPLETE_ERROR 0x0008 +#define PHY84858_STATUS_CMD_SYSTEM_BUSY 0xbbbb + /* Warpcore clause 45 addressing */ #define MDIO_WC_DEVAD 0x3 @@ -553,8 +567,8 @@ Theotherbitsarereservedandshouldbezero*/ #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT0 0x10 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1 0x11 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2 0x12 -#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY 0x4000 -#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ 0x8000 + #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY 0x4000 + #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ 0x8000 #define MDIO_WC_REG_PCS_STATUS2 0x0021 #define MDIO_WC_REG_PMD_KR_CONTROL 0x0096 #define MDIO_WC_REG_XGXSBLK0_XGXSCONTROL 0x8000 @@ -570,6 +584,8 @@ Theotherbitsarereservedandshouldbezero*/ #define MDIO_WC_REG_TX2_ANA_CTRL0 0x8081 #define MDIO_WC_REG_TX3_ANA_CTRL0 0x8091 #define MDIO_WC_REG_TX0_TX_DRIVER 0x8067 +#define MDIO_WC_REG_TX0_TX_DRIVER_IFIR_OFFSET 0x01 +#define MDIO_WC_REG_TX0_TX_DRIVER_IFIR_MASK 0x000e #define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET 0x04 #define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_MASK 0x00f0 #define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET 0x08 @@ -585,7 +601,9 @@ Theotherbitsarereservedandshouldbezero*/ #define MDIO_WC_REG_RX1_PCI_CTRL 0x80ca #define MDIO_WC_REG_RX2_PCI_CTRL 0x80da #define MDIO_WC_REG_RX3_PCI_CTRL 0x80ea +#define MDIO_WC_REG_RXB_ANA_RX_CONTROL_PCI 0x80fa #define MDIO_WC_REG_XGXSBLK2_UNICORE_MODE_10G 0x8104 +#define MDIO_WC_REG_XGXSBLK2_LANE_RESET 0x810a #define MDIO_WC_REG_XGXS_STATUS3 0x8129 #define MDIO_WC_REG_PAR_DET_10G_STATUS 0x8130 #define MDIO_WC_REG_PAR_DET_10G_CTRL 0x8131 @@ -599,35 +617,35 @@ Theotherbitsarereservedandshouldbezero*/ #define MDIO_WC_REG_GP2_STATUS_GP_2_2 0x81d2 #define MDIO_WC_REG_GP2_STATUS_GP_2_3 0x81d3 #define MDIO_WC_REG_GP2_STATUS_GP_2_4 0x81d4 -#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL 0x1000 -#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CMPL 0x0100 -#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP 0x0010 -#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CAP 0x1 + #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL 0x1000 + #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CMPL 0x0100 + #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP 0x0010 + #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CAP 0x1 #define MDIO_WC_REG_UC_INFO_B0_DEAD_TRAP 0x81EE #define MDIO_WC_REG_UC_INFO_B1_VERSION 0x81F0 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE 0x81F2 -#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE0_OFFSET 0x0 -#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT 0x0 -#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_OPT_LR 0x1 -#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC 0x2 -#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_XLAUI 0x3 -#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_LONG_CH_6G 0x4 -#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE1_OFFSET 0x4 -#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE2_OFFSET 0x8 -#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE3_OFFSET 0xc + #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE0_OFFSET 0x0 + #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT 0x0 + #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_OPT_LR 0x1 + #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC 0x2 + #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_XLAUI 0x3 + #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_LONG_CH_6G 0x4 + #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE1_OFFSET 0x4 + #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE2_OFFSET 0x8 + #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE3_OFFSET 0xc #define MDIO_WC_REG_UC_INFO_B1_CRC 0x81FE #define MDIO_WC_REG_DSC1B0_UC_CTRL 0x820e #define MDIO_WC_REG_DSC1B0_UC_CTRL_RDY4CMD (1<<7) #define MDIO_WC_REG_DSC_SMC 0x8213 #define MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0 0x821e #define MDIO_WC_REG_TX_FIR_TAP 0x82e2 -#define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET 0x00 -#define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_MASK 0x000f -#define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET 0x04 -#define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_MASK 0x03f0 -#define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET 0x0a -#define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_MASK 0x7c00 -#define MDIO_WC_REG_TX_FIR_TAP_ENABLE 0x8000 + #define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET 0x00 + #define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_MASK 0x000f + #define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET 0x04 + #define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_MASK 0x03f0 + #define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET 0x0a + #define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_MASK 0x7c00 + #define MDIO_WC_REG_TX_FIR_TAP_ENABLE 0x8000 #define MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP 0x82e2 #define MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL 0x82e3 #define MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL 0x82e6 @@ -689,8 +707,8 @@ Theotherbitsarereservedandshouldbezero*/ #define MDIO_WC_REG_COMBO_IEEE0_MIIISTAT 0xffe1 #define MDIO_WC0_XGXS_BLK2_LANE_RESET 0x810A -#define MDIO_WC0_XGXS_BLK2_LANE_RESET_RX_BITSHIFT 0 -#define MDIO_WC0_XGXS_BLK2_LANE_RESET_TX_BITSHIFT 4 +#define MDIO_WC0_XGXS_BLK2_LANE_RESET_RX_BITSHIFT 0 +#define MDIO_WC0_XGXS_BLK2_LANE_RESET_TX_BITSHIFT 4 #define MDIO_WC0_XGXS_BLK6_XGXS_X2_CONTROL2 0x8141 @@ -700,33 +718,31 @@ Theotherbitsarereservedandshouldbezero*/ #define MDIO_REG_GPHY_MII_STATUS 0x1 #define MDIO_REG_GPHY_PHYID_LSB 0x3 #define MDIO_REG_GPHY_CL45_ADDR_REG 0xd -#define MDIO_REG_GPHY_CL45_REG_WRITE 0x4000 -#define MDIO_REG_GPHY_CL45_REG_READ 0xc000 + #define MDIO_REG_GPHY_CL45_REG_WRITE 0x4000 + #define MDIO_REG_GPHY_CL45_REG_READ 0xc000 #define MDIO_REG_GPHY_CL45_DATA_REG 0xe -#define MDIO_REG_GPHY_EEE_RESOLVED 0x803e + #define MDIO_REG_GPHY_EEE_RESOLVED 0x803e #define MDIO_REG_GPHY_EXP_ACCESS_GATE 0x15 #define MDIO_REG_GPHY_EXP_ACCESS 0x17 -#define MDIO_REG_GPHY_EXP_ACCESS_TOP 0xd00 -#define MDIO_REG_GPHY_EXP_TOP_2K_BUF 0x40 + #define MDIO_REG_GPHY_EXP_ACCESS_TOP 0xd00 + #define MDIO_REG_GPHY_EXP_TOP_2K_BUF 0x40 #define MDIO_REG_GPHY_AUX_STATUS 0x19 #define MDIO_REG_INTR_STATUS 0x1a #define MDIO_REG_INTR_MASK 0x1b -#define MDIO_REG_INTR_MASK_LINK_STATUS (0x1 << 1) + #define MDIO_REG_INTR_MASK_LINK_STATUS (0x1 << 1) #define MDIO_REG_GPHY_SHADOW 0x1c -#define MDIO_REG_GPHY_SHADOW_LED_SEL1 (0x0d << 10) -#define MDIO_REG_GPHY_SHADOW_LED_SEL2 (0x0e << 10) -#define MDIO_REG_GPHY_SHADOW_WR_ENA (0x1 << 15) -#define MDIO_REG_GPHY_SHADOW_AUTO_DET_MED (0x1e << 10) -#define MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD (0x1 << 8) - -typedef elink_status_t(*read_sfp_module_eeprom_func_p) (struct elink_phy * phy, - struct elink_params * - params, - uint8_t dev_addr, - uint16_t addr, - uint8_t byte_cnt, - uint8_t * o_buf, - uint8_t); + #define MDIO_REG_GPHY_SHADOW_LED_SEL1 (0x0d << 10) + #define MDIO_REG_GPHY_SHADOW_LED_SEL2 (0x0e << 10) + #define MDIO_REG_GPHY_SHADOW_WR_ENA (0x1 << 15) + #define MDIO_REG_GPHY_SHADOW_AUTO_DET_MED (0x1e << 10) + #define MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD (0x1 << 8) + + +typedef elink_status_t (*read_sfp_module_eeprom_func_p)(struct elink_phy *phy, + struct elink_params *params, + uint8_t dev_addr, uint16_t addr, + uint8_t byte_cnt, + uint8_t *o_buf, uint8_t); /********************************************************/ #define ELINK_ETH_HLEN 14 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */ @@ -850,21 +866,29 @@ typedef elink_status_t(*read_sfp_module_eeprom_func_p) (struct elink_phy * phy, LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE) #define ELINK_SFP_EEPROM_CON_TYPE_ADDR 0x2 -#define ELINK_SFP_EEPROM_CON_TYPE_VAL_LC 0x7 -#define ELINK_SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21 -#define ELINK_SFP_EEPROM_CON_TYPE_VAL_RJ45 0x22 + #define ELINK_SFP_EEPROM_CON_TYPE_VAL_UNKNOWN 0x0 + #define ELINK_SFP_EEPROM_CON_TYPE_VAL_LC 0x7 + #define ELINK_SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21 + #define ELINK_SFP_EEPROM_CON_TYPE_VAL_RJ45 0x22 + -#define ELINK_SFP_EEPROM_COMP_CODE_ADDR 0x3 -#define ELINK_SFP_EEPROM_COMP_CODE_SR_MASK (1<<4) -#define ELINK_SFP_EEPROM_COMP_CODE_LR_MASK (1<<5) -#define ELINK_SFP_EEPROM_COMP_CODE_LRM_MASK (1<<6) +#define ELINK_SFP_EEPROM_10G_COMP_CODE_ADDR 0x3 + #define ELINK_SFP_EEPROM_10G_COMP_CODE_SR_MASK (1 << 4) + #define ELINK_SFP_EEPROM_10G_COMP_CODE_LR_MASK (1 << 5) + #define ELINK_SFP_EEPROM_10G_COMP_CODE_LRM_MASK (1 << 6) + +#define ELINK_SFP_EEPROM_1G_COMP_CODE_ADDR 0x6 + #define ELINK_SFP_EEPROM_1G_COMP_CODE_SX (1 << 0) + #define ELINK_SFP_EEPROM_1G_COMP_CODE_LX (1 << 1) + #define ELINK_SFP_EEPROM_1G_COMP_CODE_CX (1 << 2) + #define ELINK_SFP_EEPROM_1G_COMP_CODE_BASE_T (1 << 3) #define ELINK_SFP_EEPROM_FC_TX_TECH_ADDR 0x8 -#define ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4 -#define ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8 + #define ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4 + #define ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8 #define ELINK_SFP_EEPROM_OPTIONS_ADDR 0x40 -#define ELINK_SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1 + #define ELINK_SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1 #define ELINK_SFP_EEPROM_OPTIONS_SIZE 2 #define ELINK_EDC_MODE_LINEAR 0x0022 @@ -883,6 +907,10 @@ typedef elink_status_t(*read_sfp_module_eeprom_func_p) (struct elink_phy * phy, #define ELINK_MAX_PACKET_SIZE (9700) #define MAX_KR_LINK_RETRY 4 +#define DEFAULT_TX_DRV_BRDCT 2 +#define DEFAULT_TX_DRV_IFIR 0 +#define DEFAULT_TX_DRV_POST2 3 +#define DEFAULT_TX_DRV_IPRE_DRIVER 6 /**********************************************************/ /* INTERFACE */ @@ -900,6 +928,11 @@ typedef elink_status_t(*read_sfp_module_eeprom_func_p) (struct elink_phy * phy, (_bank + (_addr & 0xf)), \ _val) +static elink_status_t elink_check_half_open_conn(struct elink_params *params, + struct elink_vars *vars, uint8_t notify); +static elink_status_t elink_sfp_module_detection(struct elink_phy *phy, + struct elink_params *params); + static uint32_t elink_bits_en(struct bnx2x_softc *sc, uint32_t reg, uint32_t bits) { uint32_t val = REG_RD(sc, reg); @@ -935,16 +968,16 @@ static int elink_check_lfa(struct elink_params *params) struct bnx2x_softc *sc = params->sc; additional_config = - REG_RD(sc, params->lfa_base + - offsetof(struct shmem_lfa, additional_config)); + REG_RD(sc, params->lfa_base + + offsetof(struct shmem_lfa, additional_config)); /* NOTE: must be first condition checked - - * to verify DCC bit is cleared in any case! - */ + * to verify DCC bit is cleared in any case! + */ if (additional_config & NO_LFA_DUE_TO_DCC_MASK) { - PMD_DRV_LOG(DEBUG, "No LFA due to DCC flap after clp exit"); + ELINK_DEBUG_P0(sc, "No LFA due to DCC flap after clp exit"); REG_WR(sc, params->lfa_base + - offsetof(struct shmem_lfa, additional_config), + offsetof(struct shmem_lfa, additional_config), additional_config & ~NO_LFA_DUE_TO_DCC_MASK); return LFA_DCC_LFA_DISABLED; } @@ -983,8 +1016,8 @@ static int elink_check_lfa(struct elink_params *params) offsetof(struct shmem_lfa, req_duplex)); req_val = params->req_duplex[0] | (params->req_duplex[1] << 16); if ((saved_val & lfa_mask) != (req_val & lfa_mask)) { - PMD_DRV_LOG(INFO, "Duplex mismatch %x vs. %x", - (saved_val & lfa_mask), (req_val & lfa_mask)); + ELINK_DEBUG_P2(sc, "Duplex mismatch %x vs. %x", + (saved_val & lfa_mask), (req_val & lfa_mask)); return LFA_DUPLEX_MISMATCH; } /* Compare Flow Control */ @@ -992,8 +1025,8 @@ static int elink_check_lfa(struct elink_params *params) offsetof(struct shmem_lfa, req_flow_ctrl)); req_val = params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16); if ((saved_val & lfa_mask) != (req_val & lfa_mask)) { - PMD_DRV_LOG(DEBUG, "Flow control mismatch %x vs. %x", - (saved_val & lfa_mask), (req_val & lfa_mask)); + ELINK_DEBUG_P2(sc, "Flow control mismatch %x vs. %x", + (saved_val & lfa_mask), (req_val & lfa_mask)); return LFA_FLOW_CTRL_MISMATCH; } /* Compare Link Speed */ @@ -1001,8 +1034,8 @@ static int elink_check_lfa(struct elink_params *params) offsetof(struct shmem_lfa, req_line_speed)); req_val = params->req_line_speed[0] | (params->req_line_speed[1] << 16); if ((saved_val & lfa_mask) != (req_val & lfa_mask)) { - PMD_DRV_LOG(DEBUG, "Link speed mismatch %x vs. %x", - (saved_val & lfa_mask), (req_val & lfa_mask)); + ELINK_DEBUG_P2(sc, "Link speed mismatch %x vs. %x", + (saved_val & lfa_mask), (req_val & lfa_mask)); return LFA_LINK_SPEED_MISMATCH; } @@ -1012,21 +1045,21 @@ static int elink_check_lfa(struct elink_params *params) speed_cap_mask[cfg_idx])); if (cur_speed_cap_mask != params->speed_cap_mask[cfg_idx]) { - PMD_DRV_LOG(DEBUG, "Speed Cap mismatch %x vs. %x", - cur_speed_cap_mask, - params->speed_cap_mask[cfg_idx]); + ELINK_DEBUG_P2(sc, "Speed Cap mismatch %x vs. %x", + cur_speed_cap_mask, + params->speed_cap_mask[cfg_idx]); return LFA_SPEED_CAP_MISMATCH; } } cur_req_fc_auto_adv = - REG_RD(sc, params->lfa_base + - offsetof(struct shmem_lfa, additional_config)) & - REQ_FC_AUTO_ADV_MASK; + REG_RD(sc, params->lfa_base + + offsetof(struct shmem_lfa, additional_config)) & + REQ_FC_AUTO_ADV_MASK; - if ((uint16_t) cur_req_fc_auto_adv != params->req_fc_auto_adv) { - PMD_DRV_LOG(DEBUG, "Flow Ctrl AN mismatch %x vs. %x", - cur_req_fc_auto_adv, params->req_fc_auto_adv); + if ((uint16_t)cur_req_fc_auto_adv != params->req_fc_auto_adv) { + ELINK_DEBUG_P2(sc, "Flow Ctrl AN mismatch %x vs. %x", + cur_req_fc_auto_adv, params->req_fc_auto_adv); return LFA_FLOW_CTRL_MISMATCH; } @@ -1038,26 +1071,25 @@ static int elink_check_lfa(struct elink_params *params) (params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI)) || ((eee_status & SHMEM_EEE_REQUESTED_BIT) ^ (params->eee_mode & ELINK_EEE_MODE_ADV_LPI))) { - PMD_DRV_LOG(DEBUG, "EEE mismatch %x vs. %x", params->eee_mode, - eee_status); + ELINK_DEBUG_P2(sc, "EEE mismatch %x vs. %x", params->eee_mode, + eee_status); return LFA_EEE_MISMATCH; } /* LFA conditions are met */ return 0; } - /******************************************************************/ /* EPIO/GPIO section */ /******************************************************************/ static void elink_get_epio(struct bnx2x_softc *sc, uint32_t epio_pin, - uint32_t * en) + uint32_t *en) { uint32_t epio_mask, gp_oenable; *en = 0; /* Sanity check */ if (epio_pin > 31) { - PMD_DRV_LOG(DEBUG, "Invalid EPIO pin %d to get", epio_pin); + ELINK_DEBUG_P1(sc, "Invalid EPIO pin %d to get", epio_pin); return; } @@ -1068,17 +1100,16 @@ static void elink_get_epio(struct bnx2x_softc *sc, uint32_t epio_pin, *en = (REG_RD(sc, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin; } - static void elink_set_epio(struct bnx2x_softc *sc, uint32_t epio_pin, uint32_t en) { uint32_t epio_mask, gp_output, gp_oenable; /* Sanity check */ if (epio_pin > 31) { - PMD_DRV_LOG(DEBUG, "Invalid EPIO pin %d to set", epio_pin); + ELINK_DEBUG_P1(sc, "Invalid EPIO pin %d to set", epio_pin); return; } - PMD_DRV_LOG(DEBUG, "Setting EPIO pin %d to %d", epio_pin, en); + ELINK_DEBUG_P2(sc, "Setting EPIO pin %d to %d", epio_pin, en); epio_mask = 1 << epio_pin; /* Set this EPIO to output */ gp_output = REG_RD(sc, MCP_REG_MCPR_GP_OUTPUTS); @@ -1104,12 +1135,12 @@ static void elink_set_cfg_pin(struct bnx2x_softc *sc, uint32_t pin_cfg, } else { uint8_t gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3; uint8_t gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2; - elink_cb_gpio_write(sc, gpio_num, (uint8_t) val, gpio_port); + elink_cb_gpio_write(sc, gpio_num, (uint8_t)val, gpio_port); } } static uint32_t elink_get_cfg_pin(struct bnx2x_softc *sc, uint32_t pin_cfg, - uint32_t * val) + uint32_t *val) { if (pin_cfg == PIN_CFG_NA) return ELINK_STATUS_ERROR; @@ -1121,14 +1152,939 @@ static uint32_t elink_get_cfg_pin(struct bnx2x_softc *sc, uint32_t pin_cfg, *val = elink_cb_gpio_read(sc, gpio_num, gpio_port); } return ELINK_STATUS_OK; +} + +/******************************************************************/ +/* ETS section */ +/******************************************************************/ +static void elink_ets_e2e3a0_disabled(struct elink_params *params) +{ + /* ETS disabled configuration*/ + struct bnx2x_softc *sc = params->sc; + + ELINK_DEBUG_P0(sc, "ETS E2E3 disabled configuration"); + + /* mapping between entry priority to client number (0,1,2 -debug and + * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST) + * 3bits client num. + * PRI4 | PRI3 | PRI2 | PRI1 | PRI0 + * cos1-100 cos0-011 dbg1-010 dbg0-001 MCP-000 + */ + + REG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688); + /* Bitmap of 5bits length. Each bit specifies whether the entry behaves + * as strict. Bits 0,1,2 - debug and management entries, 3 - + * COS0 entry, 4 - COS1 entry. + * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT + * bit4 bit3 bit2 bit1 bit0 + * MCP and debug are strict + */ + + REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7); + /* defines which entries (clients) are subjected to WFQ arbitration */ + REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0); + /* For strict priority entries defines the number of consecutive + * slots for the highest priority. + */ + REG_WR(sc, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); + /* mapping between the CREDIT_WEIGHT registers and actual client + * numbers + */ + REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0); + REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0); + REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0); + + REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0); + REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0); + REG_WR(sc, PBF_REG_HIGH_PRIORITY_COS_NUM, 0); + /* ETS mode disable */ + REG_WR(sc, PBF_REG_ETS_ENABLED, 0); + /* If ETS mode is enabled (there is no strict priority) defines a WFQ + * weight for COS0/COS1. + */ + REG_WR(sc, PBF_REG_COS0_WEIGHT, 0x2710); + REG_WR(sc, PBF_REG_COS1_WEIGHT, 0x2710); + /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */ + REG_WR(sc, PBF_REG_COS0_UPPER_BOUND, 0x989680); + REG_WR(sc, PBF_REG_COS1_UPPER_BOUND, 0x989680); + /* Defines the number of consecutive slots for the strict priority */ + REG_WR(sc, PBF_REG_NUM_STRICT_ARB_SLOTS, 0); +} +/****************************************************************************** + * Description: + * Getting min_w_val will be set according to line speed . + *. + ******************************************************************************/ +static uint32_t elink_ets_get_min_w_val_nig(const struct elink_vars *vars) +{ + uint32_t min_w_val = 0; + /* Calculate min_w_val.*/ + if (vars->link_up) { + if (vars->line_speed == ELINK_SPEED_20000) + min_w_val = ELINK_ETS_E3B0_NIG_MIN_W_VAL_20GBPS; + else + min_w_val = ELINK_ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS; + } else { + min_w_val = ELINK_ETS_E3B0_NIG_MIN_W_VAL_20GBPS; + } + /* If the link isn't up (static configuration for example ) The + * link will be according to 20GBPS. + */ + return min_w_val; +} +/****************************************************************************** + * Description: + * Getting credit upper bound form min_w_val. + *. + ******************************************************************************/ +static uint32_t elink_ets_get_credit_upper_bound(const uint32_t min_w_val) +{ + const uint32_t credit_upper_bound = (uint32_t) + ELINK_MAXVAL((150 * min_w_val), + ELINK_MAX_PACKET_SIZE); + return credit_upper_bound; +} +/****************************************************************************** + * Description: + * Set credit upper bound for NIG. + *. + ******************************************************************************/ +static void elink_ets_e3b0_set_credit_upper_bound_nig( + const struct elink_params *params, + const uint32_t min_w_val) +{ + struct bnx2x_softc *sc = params->sc; + const uint8_t port = params->port; + const uint32_t credit_upper_bound = + elink_ets_get_credit_upper_bound(min_w_val); + + REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 : + NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, credit_upper_bound); + REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 : + NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, credit_upper_bound); + REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 : + NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2, credit_upper_bound); + REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 : + NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3, credit_upper_bound); + REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 : + NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4, credit_upper_bound); + REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 : + NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5, credit_upper_bound); + + if (!port) { + REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6, + credit_upper_bound); + REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7, + credit_upper_bound); + REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8, + credit_upper_bound); + } +} +/****************************************************************************** + * Description: + * Will return the NIG ETS registers to init values.Except + * credit_upper_bound. + * That isn't used in this configuration (No WFQ is enabled) and will be + * configured according to spec + *. + ******************************************************************************/ +static void elink_ets_e3b0_nig_disabled(const struct elink_params *params, + const struct elink_vars *vars) +{ + struct bnx2x_softc *sc = params->sc; + const uint8_t port = params->port; + const uint32_t min_w_val = elink_ets_get_min_w_val_nig(vars); + /* Mapping between entry priority to client number (0,1,2 -debug and + * management clients, 3 - COS0 client, 4 - COS1, ... 8 - + * COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by + * reset value or init tool + */ + if (port) { + REG_WR(sc, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210); + REG_WR(sc, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0); + } else { + REG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210); + REG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8); + } + /* For strict priority entries defines the number of consecutive + * slots for the highest priority. + */ + REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS : + NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); + /* Mapping between the CREDIT_WEIGHT registers and actual client + * numbers + */ + if (port) { + /*Port 1 has 6 COS*/ + REG_WR(sc, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543); + REG_WR(sc, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0); + } else { + /*Port 0 has 9 COS*/ + REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB, + 0x43210876); + REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5); + } + + /* Bitmap of 5bits length. Each bit specifies whether the entry behaves + * as strict. Bits 0,1,2 - debug and management entries, 3 - + * COS0 entry, 4 - COS1 entry. + * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT + * bit4 bit3 bit2 bit1 bit0 + * MCP and debug are strict + */ + if (port) + REG_WR(sc, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f); + else + REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff); + /* defines which entries (clients) are subjected to WFQ arbitration */ + REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ : + NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0); + + /* Please notice the register address are note continuous and a + * for here is note appropriate.In 2 port mode port0 only COS0-5 + * can be used. DEBUG1,DEBUG1,MGMT are never used for WFQ* In 4 + * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT + * are never used for WFQ + */ + REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 : + NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0x0); + REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 : + NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0x0); + REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 : + NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2, 0x0); + REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 : + NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3, 0x0); + REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 : + NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4, 0x0); + REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 : + NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5, 0x0); + if (!port) { + REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0); + REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0); + REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0); + } + + elink_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val); +} +/****************************************************************************** + * Description: + * Set credit upper bound for PBF. + *. + ******************************************************************************/ +static void elink_ets_e3b0_set_credit_upper_bound_pbf( + const struct elink_params *params, + const uint32_t min_w_val) +{ + struct bnx2x_softc *sc = params->sc; + const uint32_t credit_upper_bound = + elink_ets_get_credit_upper_bound(min_w_val); + const uint8_t port = params->port; + uint32_t base_upper_bound = 0; + uint8_t max_cos = 0; + uint8_t i = 0; + /* In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4 + * port mode port1 has COS0-2 that can be used for WFQ. + */ + if (!port) { + base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P0; + max_cos = ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0; + } else { + base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P1; + max_cos = ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1; + } + + for (i = 0; i < max_cos; i++) + REG_WR(sc, base_upper_bound + (i << 2), credit_upper_bound); +} + +/****************************************************************************** + * Description: + * Will return the PBF ETS registers to init values.Except + * credit_upper_bound. + * That isn't used in this configuration (No WFQ is enabled) and will be + * configured according to spec + *. + ******************************************************************************/ +static void elink_ets_e3b0_pbf_disabled(const struct elink_params *params) +{ + struct bnx2x_softc *sc = params->sc; + const uint8_t port = params->port; + const uint32_t min_w_val_pbf = ELINK_ETS_E3B0_PBF_MIN_W_VAL; + uint8_t i = 0; + uint32_t base_weight = 0; + uint8_t max_cos = 0; + + /* Mapping between entry priority to client number 0 - COS0 + * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num. + * TODO_ETS - Should be done by reset value or init tool + */ + if (port) + /* 0x688 (|011|0 10|00 1|000) */ + REG_WR(sc, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1, 0x688); + else + /* (10 1|100 |011|0 10|00 1|000) */ + REG_WR(sc, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0, 0x2C688); + + /* TODO_ETS - Should be done by reset value or init tool */ + if (port) + /* 0x688 (|011|0 10|00 1|000)*/ + REG_WR(sc, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688); + else + /* 0x2C688 (10 1|100 |011|0 10|00 1|000) */ + REG_WR(sc, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688); + + REG_WR(sc, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 : + PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0, 0x100); + + + REG_WR(sc, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 : + PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0, 0); + + REG_WR(sc, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 : + PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0, 0); + /* In 2 port mode port0 has COS0-5 that can be used for WFQ. + * In 4 port mode port1 has COS0-2 that can be used for WFQ. + */ + if (!port) { + base_weight = PBF_REG_COS0_WEIGHT_P0; + max_cos = ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0; + } else { + base_weight = PBF_REG_COS0_WEIGHT_P1; + max_cos = ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1; + } + + for (i = 0; i < max_cos; i++) + REG_WR(sc, base_weight + (0x4 * i), 0); + + elink_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf); +} +/****************************************************************************** + * Description: + * E3B0 disable will return basicly the values to init values. + *. + ******************************************************************************/ +static elink_status_t elink_ets_e3b0_disabled(const struct elink_params *params, + const struct elink_vars *vars) +{ + struct bnx2x_softc *sc = params->sc; + + if (!CHIP_IS_E3B0(sc)) { + ELINK_DEBUG_P0(sc, + "elink_ets_e3b0_disabled the chip isn't E3B0"); + return ELINK_STATUS_ERROR; + } + + elink_ets_e3b0_nig_disabled(params, vars); + + elink_ets_e3b0_pbf_disabled(params); + + return ELINK_STATUS_OK; +} + +/****************************************************************************** + * Description: + * Disable will return basicly the values to init values. + * + ******************************************************************************/ +elink_status_t elink_ets_disabled(struct elink_params *params, + struct elink_vars *vars) +{ + struct bnx2x_softc *sc = params->sc; + elink_status_t elink_status = ELINK_STATUS_OK; + + if ((CHIP_IS_E2(sc)) || (CHIP_IS_E3A0(sc))) { + elink_ets_e2e3a0_disabled(params); + } else if (CHIP_IS_E3B0(sc)) { + elink_status = elink_ets_e3b0_disabled(params, vars); + } else { + ELINK_DEBUG_P0(sc, "elink_ets_disabled - chip not supported"); + return ELINK_STATUS_ERROR; + } + + return elink_status; +} + +/****************************************************************************** + * Description + * Set the COS mappimg to SP and BW until this point all the COS are not + * set as SP or BW. + ******************************************************************************/ +static elink_status_t elink_ets_e3b0_cli_map(const struct elink_params *params, + __rte_unused const struct elink_ets_params *ets_params, + const uint8_t cos_sp_bitmap, + const uint8_t cos_bw_bitmap) +{ + struct bnx2x_softc *sc = params->sc; + const uint8_t port = params->port; + const uint8_t nig_cli_sp_bitmap = 0x7 | (cos_sp_bitmap << 3); + const uint8_t pbf_cli_sp_bitmap = cos_sp_bitmap; + const uint8_t nig_cli_subject2wfq_bitmap = cos_bw_bitmap << 3; + const uint8_t pbf_cli_subject2wfq_bitmap = cos_bw_bitmap; + + REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT : + NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, nig_cli_sp_bitmap); + + REG_WR(sc, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 : + PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0, pbf_cli_sp_bitmap); + + REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ : + NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, + nig_cli_subject2wfq_bitmap); + + REG_WR(sc, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 : + PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0, + pbf_cli_subject2wfq_bitmap); + + return ELINK_STATUS_OK; +} + +/****************************************************************************** + * Description: + * This function is needed because NIG ARB_CREDIT_WEIGHT_X are + * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable. + ******************************************************************************/ +static elink_status_t elink_ets_e3b0_set_cos_bw(struct bnx2x_softc *sc, + const uint8_t cos_entry, + const uint32_t min_w_val_nig, + const uint32_t min_w_val_pbf, + const uint16_t total_bw, + const uint8_t bw, + const uint8_t port) +{ + uint32_t nig_reg_address_crd_weight = 0; + uint32_t pbf_reg_address_crd_weight = 0; + /* Calculate and set BW for this COS - use 1 instead of 0 for BW */ + const uint32_t cos_bw_nig = ((bw ? bw : 1) * min_w_val_nig) / total_bw; + const uint32_t cos_bw_pbf = ((bw ? bw : 1) * min_w_val_pbf) / total_bw; + + switch (cos_entry) { + case 0: + nig_reg_address_crd_weight = + (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 : + NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0; + pbf_reg_address_crd_weight = (port) ? + PBF_REG_COS0_WEIGHT_P1 : PBF_REG_COS0_WEIGHT_P0; + break; + case 1: + nig_reg_address_crd_weight = (port) ? + NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 : + NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1; + pbf_reg_address_crd_weight = (port) ? + PBF_REG_COS1_WEIGHT_P1 : PBF_REG_COS1_WEIGHT_P0; + break; + case 2: + nig_reg_address_crd_weight = (port) ? + NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 : + NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2; + + pbf_reg_address_crd_weight = (port) ? + PBF_REG_COS2_WEIGHT_P1 : PBF_REG_COS2_WEIGHT_P0; + break; + case 3: + if (port) + return ELINK_STATUS_ERROR; + nig_reg_address_crd_weight = + NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3; + pbf_reg_address_crd_weight = + PBF_REG_COS3_WEIGHT_P0; + break; + case 4: + if (port) + return ELINK_STATUS_ERROR; + nig_reg_address_crd_weight = + NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4; + pbf_reg_address_crd_weight = PBF_REG_COS4_WEIGHT_P0; + break; + case 5: + if (port) + return ELINK_STATUS_ERROR; + nig_reg_address_crd_weight = + NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5; + pbf_reg_address_crd_weight = PBF_REG_COS5_WEIGHT_P0; + break; + } + + REG_WR(sc, nig_reg_address_crd_weight, cos_bw_nig); + + REG_WR(sc, pbf_reg_address_crd_weight, cos_bw_pbf); + + return ELINK_STATUS_OK; +} +/****************************************************************************** + * Description: + * Calculate the total BW.A value of 0 isn't legal. + * + ******************************************************************************/ +static elink_status_t elink_ets_e3b0_get_total_bw( + const struct elink_params *params, + struct elink_ets_params *ets_params, + uint16_t *total_bw) +{ + struct bnx2x_softc *sc = params->sc; + uint8_t cos_idx = 0; + uint8_t is_bw_cos_exist = 0; + + *total_bw = 0; + /* Calculate total BW requested */ + for (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) { + if (ets_params->cos[cos_idx].state == elink_cos_state_bw) { + is_bw_cos_exist = 1; + if (!ets_params->cos[cos_idx].params.bw_params.bw) { + ELINK_DEBUG_P0(sc, "elink_ets_E3B0_config BW" + " was set to 0"); + /* This is to prevent a state when ramrods + * can't be sent + */ + ets_params->cos[cos_idx].params.bw_params.bw + = 1; + } + *total_bw += + ets_params->cos[cos_idx].params.bw_params.bw; + } + } + + /* Check total BW is valid */ + if ((is_bw_cos_exist == 1) && (*total_bw != 100)) { + if (*total_bw == 0) { + ELINK_DEBUG_P0(sc, + "elink_ets_E3B0_config total BW shouldn't be 0"); + return ELINK_STATUS_ERROR; + } + ELINK_DEBUG_P0(sc, + "elink_ets_E3B0_config total BW should be 100"); + /* We can handle a case whre the BW isn't 100 this can happen + * if the TC are joined. + */ + } + return ELINK_STATUS_OK; +} + +/****************************************************************************** + * Description: + * Invalidate all the sp_pri_to_cos. + * + ******************************************************************************/ +static void elink_ets_e3b0_sp_pri_to_cos_init(uint8_t *sp_pri_to_cos) +{ + uint8_t pri = 0; + for (pri = 0; pri < ELINK_DCBX_MAX_NUM_COS; pri++) + sp_pri_to_cos[pri] = DCBX_INVALID_COS; +} +/****************************************************************************** + * Description: + * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers + * according to sp_pri_to_cos. + * + ******************************************************************************/ +static elink_status_t elink_ets_e3b0_sp_pri_to_cos_set( + const struct elink_params *params, + uint8_t *sp_pri_to_cos, + const uint8_t pri, + const uint8_t cos_entry) +{ + struct bnx2x_softc *sc = params->sc; + const uint8_t port = params->port; + const uint8_t max_num_of_cos = (port) ? + ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1 : + ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0; + + if (pri >= max_num_of_cos) { + ELINK_DEBUG_P0(sc, "elink_ets_e3b0_sp_pri_to_cos_set invalid " + "parameter Illegal strict priority"); + return ELINK_STATUS_ERROR; + } + + if (sp_pri_to_cos[pri] != DCBX_INVALID_COS) { + ELINK_DEBUG_P0(sc, "elink_ets_e3b0_sp_pri_to_cos_set invalid " + "parameter There can't be two COS's with " + "the same strict pri"); + return ELINK_STATUS_ERROR; + } + + sp_pri_to_cos[pri] = cos_entry; + return ELINK_STATUS_OK; +} + +/****************************************************************************** + * Description: + * Returns the correct value according to COS and priority in + * the sp_pri_cli register. + * + ******************************************************************************/ +static uint64_t elink_e3b0_sp_get_pri_cli_reg(const uint8_t cos, + const uint8_t cos_offset, + const uint8_t pri_set, + const uint8_t pri_offset, + const uint8_t entry_size) +{ + uint64_t pri_cli_nig = 0; + pri_cli_nig = ((uint64_t)(cos + cos_offset)) << (entry_size * + (pri_set + pri_offset)); + + return pri_cli_nig; +} +/****************************************************************************** + * Description: + * Returns the correct value according to COS and priority in the + * sp_pri_cli register for NIG. + * + ******************************************************************************/ +static uint64_t elink_e3b0_sp_get_pri_cli_reg_nig(const uint8_t cos, + const uint8_t pri_set) +{ + /* MCP Dbg0 and dbg1 are always with higher strict pri*/ + const uint8_t nig_cos_offset = 3; + const uint8_t nig_pri_offset = 3; + + return elink_e3b0_sp_get_pri_cli_reg(cos, nig_cos_offset, pri_set, + nig_pri_offset, 4); +} +/****************************************************************************** + * Description: + * Returns the correct value according to COS and priority in the + * sp_pri_cli register for PBF. + * + ******************************************************************************/ +static uint64_t elink_e3b0_sp_get_pri_cli_reg_pbf(const uint8_t cos, + const uint8_t pri_set) +{ + const uint8_t pbf_cos_offset = 0; + const uint8_t pbf_pri_offset = 0; + + return elink_e3b0_sp_get_pri_cli_reg(cos, pbf_cos_offset, pri_set, + pbf_pri_offset, 3); +} + +/****************************************************************************** + * Description: + * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers + * according to sp_pri_to_cos.(which COS has higher priority) + * + ******************************************************************************/ +static elink_status_t elink_ets_e3b0_sp_set_pri_cli_reg( + const struct elink_params *params, + uint8_t *sp_pri_to_cos) +{ + struct bnx2x_softc *sc = params->sc; + uint8_t i = 0; + const uint8_t port = params->port; + /* MCP Dbg0 and dbg1 are always with higher strict pri*/ + uint64_t pri_cli_nig = 0x210; + uint32_t pri_cli_pbf = 0x0; + uint8_t pri_set = 0; + uint8_t pri_bitmask = 0; + const uint8_t max_num_of_cos = (port) ? + ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1 : + ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0; + + uint8_t cos_bit_to_set = (1 << max_num_of_cos) - 1; + + /* Set all the strict priority first */ + for (i = 0; i < max_num_of_cos; i++) { + if (sp_pri_to_cos[i] != DCBX_INVALID_COS) { + if (sp_pri_to_cos[i] >= ELINK_DCBX_MAX_NUM_COS) { + ELINK_DEBUG_P0(sc, + "elink_ets_e3b0_sp_set_pri_cli_reg " + "invalid cos entry"); + return ELINK_STATUS_ERROR; + } + + pri_cli_nig |= elink_e3b0_sp_get_pri_cli_reg_nig( + sp_pri_to_cos[i], pri_set); + + pri_cli_pbf |= elink_e3b0_sp_get_pri_cli_reg_pbf( + sp_pri_to_cos[i], pri_set); + pri_bitmask = 1 << sp_pri_to_cos[i]; + /* COS is used remove it from bitmap.*/ + if (!(pri_bitmask & cos_bit_to_set)) { + ELINK_DEBUG_P0(sc, + "elink_ets_e3b0_sp_set_pri_cli_reg " + "invalid There can't be two COS's with" + " the same strict pri"); + return ELINK_STATUS_ERROR; + } + cos_bit_to_set &= ~pri_bitmask; + pri_set++; + } + } + + /* Set all the Non strict priority i= COS*/ + for (i = 0; i < max_num_of_cos; i++) { + pri_bitmask = 1 << i; + /* Check if COS was already used for SP */ + if (pri_bitmask & cos_bit_to_set) { + /* COS wasn't used for SP */ + pri_cli_nig |= elink_e3b0_sp_get_pri_cli_reg_nig( + i, pri_set); + + pri_cli_pbf |= elink_e3b0_sp_get_pri_cli_reg_pbf( + i, pri_set); + /* COS is used remove it from bitmap.*/ + cos_bit_to_set &= ~pri_bitmask; + pri_set++; + } + } + + if (pri_set != max_num_of_cos) { + ELINK_DEBUG_P0(sc, "elink_ets_e3b0_sp_set_pri_cli_reg not all " + "entries were set"); + return ELINK_STATUS_ERROR; + } + + if (port) { + /* Only 6 usable clients*/ + REG_WR(sc, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, + (uint32_t)pri_cli_nig); + + REG_WR(sc, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1, pri_cli_pbf); + } else { + /* Only 9 usable clients*/ + const uint32_t pri_cli_nig_lsb = (uint32_t)(pri_cli_nig); + const uint32_t pri_cli_nig_msb = (uint32_t) + ((pri_cli_nig >> 32) & 0xF); + + REG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, + pri_cli_nig_lsb); + REG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, + pri_cli_nig_msb); + + REG_WR(sc, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0, pri_cli_pbf); + } + return ELINK_STATUS_OK; +} + +/****************************************************************************** + * Description: + * Configure the COS to ETS according to BW and SP settings. + ******************************************************************************/ +elink_status_t elink_ets_e3b0_config(const struct elink_params *params, + const struct elink_vars *vars, + struct elink_ets_params *ets_params) +{ + struct bnx2x_softc *sc = params->sc; + elink_status_t elink_status = ELINK_STATUS_OK; + const uint8_t port = params->port; + uint16_t total_bw = 0; + const uint32_t min_w_val_nig = elink_ets_get_min_w_val_nig(vars); + const uint32_t min_w_val_pbf = ELINK_ETS_E3B0_PBF_MIN_W_VAL; + uint8_t cos_bw_bitmap = 0; + uint8_t cos_sp_bitmap = 0; + uint8_t sp_pri_to_cos[ELINK_DCBX_MAX_NUM_COS] = {0}; + const uint8_t max_num_of_cos = (port) ? + ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1 : + ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0; + uint8_t cos_entry = 0; + + if (!CHIP_IS_E3B0(sc)) { + ELINK_DEBUG_P0(sc, + "elink_ets_e3b0_disabled the chip isn't E3B0"); + return ELINK_STATUS_ERROR; + } + + if (ets_params->num_of_cos > max_num_of_cos) { + ELINK_DEBUG_P0(sc, "elink_ets_E3B0_config the number of COS " + "isn't supported"); + return ELINK_STATUS_ERROR; + } + + /* Prepare sp strict priority parameters*/ + elink_ets_e3b0_sp_pri_to_cos_init(sp_pri_to_cos); + + /* Prepare BW parameters*/ + elink_status = elink_ets_e3b0_get_total_bw(params, ets_params, + &total_bw); + if (elink_status != ELINK_STATUS_OK) { + ELINK_DEBUG_P0(sc, + "elink_ets_E3B0_config get_total_bw failed"); + return ELINK_STATUS_ERROR; + } + + /* Upper bound is set according to current link speed (min_w_val + * should be the same for upper bound and COS credit val). + */ + elink_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val_nig); + elink_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf); + + + for (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) { + if (elink_cos_state_bw == ets_params->cos[cos_entry].state) { + cos_bw_bitmap |= (1 << cos_entry); + /* The function also sets the BW in HW(not the mappin + * yet) + */ + elink_status = elink_ets_e3b0_set_cos_bw( + sc, cos_entry, min_w_val_nig, min_w_val_pbf, + total_bw, + ets_params->cos[cos_entry].params.bw_params.bw, + port); + } else if (elink_cos_state_strict == + ets_params->cos[cos_entry].state){ + cos_sp_bitmap |= (1 << cos_entry); + + elink_status = elink_ets_e3b0_sp_pri_to_cos_set( + params, + sp_pri_to_cos, + ets_params->cos[cos_entry].params.sp_params.pri, + cos_entry); + + } else { + ELINK_DEBUG_P0(sc, + "elink_ets_e3b0_config cos state not valid"); + return ELINK_STATUS_ERROR; + } + if (elink_status != ELINK_STATUS_OK) { + ELINK_DEBUG_P0(sc, + "elink_ets_e3b0_config set cos bw failed"); + return elink_status; + } + } + + /* Set SP register (which COS has higher priority) */ + elink_status = elink_ets_e3b0_sp_set_pri_cli_reg(params, + sp_pri_to_cos); + + if (elink_status != ELINK_STATUS_OK) { + ELINK_DEBUG_P0(sc, + "elink_ets_E3B0_config set_pri_cli_reg failed"); + return elink_status; + } + + /* Set client mapping of BW and strict */ + elink_status = elink_ets_e3b0_cli_map(params, ets_params, + cos_sp_bitmap, + cos_bw_bitmap); + + if (elink_status != ELINK_STATUS_OK) { + ELINK_DEBUG_P0(sc, "elink_ets_E3B0_config SP failed"); + return elink_status; + } + return ELINK_STATUS_OK; +} +static void elink_ets_bw_limit_common(const struct elink_params *params) +{ + /* ETS disabled configuration */ + struct bnx2x_softc *sc = params->sc; + ELINK_DEBUG_P0(sc, "ETS enabled BW limit configuration"); + /* Defines which entries (clients) are subjected to WFQ arbitration + * COS0 0x8 + * COS1 0x10 + */ + REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18); + /* Mapping between the ARB_CREDIT_WEIGHT registers and actual + * client numbers (WEIGHT_0 does not actually have to represent + * client 0) + * PRI4 | PRI3 | PRI2 | PRI1 | PRI0 + * cos1-001 cos0-000 dbg1-100 dbg0-011 MCP-010 + */ + REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A); + + REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, + ELINK_ETS_BW_LIMIT_CREDIT_UPPER_BOUND); + REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, + ELINK_ETS_BW_LIMIT_CREDIT_UPPER_BOUND); + + /* ETS mode enabled*/ + REG_WR(sc, PBF_REG_ETS_ENABLED, 1); + + /* Defines the number of consecutive slots for the strict priority */ + REG_WR(sc, PBF_REG_NUM_STRICT_ARB_SLOTS, 0); + /* Bitmap of 5bits length. Each bit specifies whether the entry behaves + * as strict. Bits 0,1,2 - debug and management entries, 3 - COS0 + * entry, 4 - COS1 entry. + * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT + * bit4 bit3 bit2 bit1 bit0 + * MCP and debug are strict + */ + REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7); + + /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/ + REG_WR(sc, PBF_REG_COS0_UPPER_BOUND, + ELINK_ETS_BW_LIMIT_CREDIT_UPPER_BOUND); + REG_WR(sc, PBF_REG_COS1_UPPER_BOUND, + ELINK_ETS_BW_LIMIT_CREDIT_UPPER_BOUND); +} + +void elink_ets_bw_limit(const struct elink_params *params, + const uint32_t cos0_bw, + const uint32_t cos1_bw) +{ + /* ETS disabled configuration*/ + struct bnx2x_softc *sc = params->sc; + const uint32_t total_bw = cos0_bw + cos1_bw; + uint32_t cos0_credit_weight = 0; + uint32_t cos1_credit_weight = 0; + + ELINK_DEBUG_P0(sc, "ETS enabled BW limit configuration"); + + if ((!total_bw) || + (!cos0_bw) || + (!cos1_bw)) { + ELINK_DEBUG_P0(sc, "Total BW can't be zero"); + return; + } + + cos0_credit_weight = (cos0_bw * ELINK_ETS_BW_LIMIT_CREDIT_WEIGHT) / + total_bw; + cos1_credit_weight = (cos1_bw * ELINK_ETS_BW_LIMIT_CREDIT_WEIGHT) / + total_bw; + + elink_ets_bw_limit_common(params); + + REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight); + REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight); + + REG_WR(sc, PBF_REG_COS0_WEIGHT, cos0_credit_weight); + REG_WR(sc, PBF_REG_COS1_WEIGHT, cos1_credit_weight); +} + +elink_status_t elink_ets_strict(const struct elink_params *params, + const uint8_t strict_cos) +{ + /* ETS disabled configuration*/ + struct bnx2x_softc *sc = params->sc; + uint32_t val = 0; + + ELINK_DEBUG_P0(sc, "ETS enabled strict configuration"); + /* Bitmap of 5bits length. Each bit specifies whether the entry behaves + * as strict. Bits 0,1,2 - debug and management entries, + * 3 - COS0 entry, 4 - COS1 entry. + * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT + * bit4 bit3 bit2 bit1 bit0 + * MCP and debug are strict + */ + REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F); + /* For strict priority entries defines the number of consecutive slots + * for the highest priority. + */ + REG_WR(sc, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); + /* ETS mode disable */ + REG_WR(sc, PBF_REG_ETS_ENABLED, 0); + /* Defines the number of consecutive slots for the strict priority */ + REG_WR(sc, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100); + + /* Defines the number of consecutive slots for the strict priority */ + REG_WR(sc, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos); + + /* Mapping between entry priority to client number (0,1,2 -debug and + * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST) + * 3bits client num. + * PRI4 | PRI3 | PRI2 | PRI1 | PRI0 + * dbg0-010 dbg1-001 cos1-100 cos0-011 MCP-000 + * dbg0-010 dbg1-001 cos0-011 cos1-100 MCP-000 + */ + val = (!strict_cos) ? 0x2318 : 0x22E0; + REG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val); + + return ELINK_STATUS_OK; } /******************************************************************/ /* PFC section */ /******************************************************************/ static void elink_update_pfc_xmac(struct elink_params *params, - struct elink_vars *vars) + struct elink_vars *vars, + __rte_unused uint8_t is_lb) { struct bnx2x_softc *sc = params->sc; uint32_t xmac_base; @@ -1143,7 +2099,8 @@ static void elink_update_pfc_xmac(struct elink_params *params, pfc1_val = 0x2; /* No PFC support */ - if (!(params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)) { + if (!(params->feature_config_flags & + ELINK_FEATURE_CONFIG_PFC_ENABLED)) { /* RX flow control - Process pause frame in receive direction */ @@ -1153,12 +2110,12 @@ static void elink_update_pfc_xmac(struct elink_params *params, /* TX flow control - Send pause packet when buffer is full */ if (vars->flow_ctrl & ELINK_FLOW_CTRL_TX) pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN; - } else { /* PFC support */ + } else {/* PFC support */ pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN | - XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN | - XMAC_PFC_CTRL_HI_REG_RX_PFC_EN | - XMAC_PFC_CTRL_HI_REG_TX_PFC_EN | - XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON; + XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN | + XMAC_PFC_CTRL_HI_REG_RX_PFC_EN | + XMAC_PFC_CTRL_HI_REG_TX_PFC_EN | + XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON; /* Write pause and PFC registers */ REG_WR(sc, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val); REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val); @@ -1172,21 +2129,76 @@ static void elink_update_pfc_xmac(struct elink_params *params, REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val); REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val); + /* Set MAC address for source TX Pause/PFC frames */ REG_WR(sc, xmac_base + XMAC_REG_CTRL_SA_LO, ((params->mac_addr[2] << 24) | (params->mac_addr[3] << 16) | - (params->mac_addr[4] << 8) | (params->mac_addr[5]))); + (params->mac_addr[4] << 8) | + (params->mac_addr[5]))); REG_WR(sc, xmac_base + XMAC_REG_CTRL_SA_HI, - ((params->mac_addr[0] << 8) | (params->mac_addr[1]))); + ((params->mac_addr[0] << 8) | + (params->mac_addr[1]))); DELAY(30); } +static void elink_emac_get_pfc_stat(struct elink_params *params, + uint32_t pfc_frames_sent[2], + uint32_t pfc_frames_received[2]) +{ + /* Read pfc statistic */ + struct bnx2x_softc *sc = params->sc; + uint32_t emac_base = params->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; + uint32_t val_xon = 0; + uint32_t val_xoff = 0; + + ELINK_DEBUG_P0(sc, "pfc statistic read from EMAC"); + + /* PFC received frames */ + val_xoff = REG_RD(sc, emac_base + + EMAC_REG_RX_PFC_STATS_XOFF_RCVD); + val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT; + val_xon = REG_RD(sc, emac_base + EMAC_REG_RX_PFC_STATS_XON_RCVD); + val_xon &= EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT; + + pfc_frames_received[0] = val_xon + val_xoff; + + /* PFC received sent */ + val_xoff = REG_RD(sc, emac_base + + EMAC_REG_RX_PFC_STATS_XOFF_SENT); + val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT; + val_xon = REG_RD(sc, emac_base + EMAC_REG_RX_PFC_STATS_XON_SENT); + val_xon &= EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT; + + pfc_frames_sent[0] = val_xon + val_xoff; +} + +/* Read pfc statistic*/ +void elink_pfc_statistic(struct elink_params *params, struct elink_vars *vars, + uint32_t pfc_frames_sent[2], + uint32_t pfc_frames_received[2]) +{ + /* Read pfc statistic */ + struct bnx2x_softc *sc = params->sc; + + ELINK_DEBUG_P0(sc, "pfc statistic"); + + if (!vars->link_up) + return; + + if (vars->mac_type == ELINK_MAC_TYPE_EMAC) { + ELINK_DEBUG_P0(sc, "About to read PFC stats from EMAC"); + elink_emac_get_pfc_stat(params, pfc_frames_sent, + pfc_frames_received); + } +} /******************************************************************/ /* MAC/PBF section */ /******************************************************************/ -static void elink_set_mdio_clk(struct bnx2x_softc *sc, uint32_t emac_base) +static void elink_set_mdio_clk(struct bnx2x_softc *sc, + __rte_unused uint32_t chip_id, + uint32_t emac_base) { uint32_t new_mode, cur_mode; uint32_t clc_cnt; @@ -1205,26 +2217,16 @@ static void elink_set_mdio_clk(struct bnx2x_softc *sc, uint32_t emac_base) return; new_mode = cur_mode & - ~(EMAC_MDIO_MODE_AUTO_POLL | EMAC_MDIO_MODE_CLOCK_CNT); + ~(EMAC_MDIO_MODE_AUTO_POLL | EMAC_MDIO_MODE_CLOCK_CNT); new_mode |= clc_cnt; new_mode |= (EMAC_MDIO_MODE_CLAUSE_45); - PMD_DRV_LOG(DEBUG, "Changing emac_mode from 0x%x to 0x%x", - cur_mode, new_mode); + ELINK_DEBUG_P2(sc, "Changing emac_mode from 0x%x to 0x%x", + cur_mode, new_mode); REG_WR(sc, emac_base + EMAC_REG_EMAC_MDIO_MODE, new_mode); DELAY(40); } -static void elink_set_mdio_emac_per_phy(struct bnx2x_softc *sc, - struct elink_params *params) -{ - uint8_t phy_index; - /* Set mdio clock per phy */ - for (phy_index = ELINK_INT_PHY; phy_index < params->num_phys; - phy_index++) - elink_set_mdio_clk(sc, params->phy[phy_index].mdio_ctrl); -} - static uint8_t elink_is_4_port_mode(struct bnx2x_softc *sc) { uint32_t port4mode_ovwr_val; @@ -1232,13 +2234,26 @@ static uint8_t elink_is_4_port_mode(struct bnx2x_softc *sc) port4mode_ovwr_val = REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR); if (port4mode_ovwr_val & (1 << 0)) { /* Return 4-port mode override value */ - return (port4mode_ovwr_val & (1 << 1)) == (1 << 1); + return ((port4mode_ovwr_val & (1 << 1)) == (1 << 1)); } /* Return 4-port mode from input pin */ - return (uint8_t) REG_RD(sc, MISC_REG_PORT4MODE_EN); + return (uint8_t)REG_RD(sc, MISC_REG_PORT4MODE_EN); +} + +static void elink_set_mdio_emac_per_phy(struct bnx2x_softc *sc, + struct elink_params *params) +{ + uint8_t phy_index; + + /* Set mdio clock per phy */ + for (phy_index = ELINK_INT_PHY; phy_index < params->num_phys; + phy_index++) + elink_set_mdio_clk(sc, params->chip_id, + params->phy[phy_index].mdio_ctrl); } -static void elink_emac_init(struct elink_params *params) +static void elink_emac_init(struct elink_params *params, + __rte_unused struct elink_vars *vars) { /* reset and unreset the emac core */ struct bnx2x_softc *sc = params->sc; @@ -1262,9 +2277,9 @@ static void elink_emac_init(struct elink_params *params) timeout = 200; do { val = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE); - PMD_DRV_LOG(DEBUG, "EMAC reset reg is %u", val); + ELINK_DEBUG_P1(sc, "EMAC reset reg is %u", val); if (!timeout) { - PMD_DRV_LOG(DEBUG, "EMAC timeout!"); + ELINK_DEBUG_P0(sc, "EMAC timeout!"); return; } timeout--; @@ -1272,17 +2287,20 @@ static void elink_emac_init(struct elink_params *params) elink_set_mdio_emac_per_phy(sc, params); /* Set mac address */ - val = ((params->mac_addr[0] << 8) | params->mac_addr[1]); + val = ((params->mac_addr[0] << 8) | + params->mac_addr[1]); elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MAC_MATCH, val); val = ((params->mac_addr[2] << 24) | (params->mac_addr[3] << 16) | - (params->mac_addr[4] << 8) | params->mac_addr[5]); + (params->mac_addr[4] << 8) | + params->mac_addr[5]); elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MAC_MATCH + 4, val); } static void elink_set_xumac_nig(struct elink_params *params, - uint16_t tx_pause_en, uint8_t enable) + uint16_t tx_pause_en, + uint8_t enable) { struct bnx2x_softc *sc = params->sc; @@ -1300,7 +2318,7 @@ static void elink_set_umac_rxtx(struct elink_params *params, uint8_t en) uint32_t val; struct bnx2x_softc *sc = params->sc; if (!(REG_RD(sc, MISC_REG_RESET_REG_2) & - (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port))) + (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port))) return; val = REG_RD(sc, umac_base + UMAC_REG_COMMAND_CONFIG); if (en) @@ -1314,7 +2332,7 @@ static void elink_set_umac_rxtx(struct elink_params *params, uint8_t en) } static void elink_umac_enable(struct elink_params *params, - struct elink_vars *vars, uint8_t lb) + struct elink_vars *vars, uint8_t lb) { uint32_t val; uint32_t umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; @@ -1327,15 +2345,15 @@ static void elink_umac_enable(struct elink_params *params, REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)); - PMD_DRV_LOG(DEBUG, "enabling UMAC"); + ELINK_DEBUG_P0(sc, "enabling UMAC"); /* This register opens the gate for the UMAC despite its name */ REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port * 4, 1); val = UMAC_COMMAND_CONFIG_REG_PROMIS_EN | - UMAC_COMMAND_CONFIG_REG_PAD_EN | - UMAC_COMMAND_CONFIG_REG_SW_RESET | - UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK; + UMAC_COMMAND_CONFIG_REG_PAD_EN | + UMAC_COMMAND_CONFIG_REG_SW_RESET | + UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK; switch (vars->line_speed) { case ELINK_SPEED_10: val |= (0 << 2); @@ -1350,8 +2368,8 @@ static void elink_umac_enable(struct elink_params *params, val |= (3 << 2); break; default: - PMD_DRV_LOG(DEBUG, "Invalid speed for UMAC %d", - vars->line_speed); + ELINK_DEBUG_P1(sc, "Invalid speed for UMAC %d", + vars->line_speed); break; } if (!(vars->flow_ctrl & ELINK_FLOW_CTRL_TX)) @@ -1368,7 +2386,7 @@ static void elink_umac_enable(struct elink_params *params, /* Configure UMAC for EEE */ if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) { - PMD_DRV_LOG(DEBUG, "configured UMAC for EEE"); + ELINK_DEBUG_P0(sc, "configured UMAC for EEE"); REG_WR(sc, umac_base + UMAC_REG_UMAC_EEE_CTRL, UMAC_UMAC_EEE_CTRL_REG_EEE_EN); REG_WR(sc, umac_base + UMAC_REG_EEE_WAKE_TIMER, 0x11); @@ -1380,13 +2398,16 @@ static void elink_umac_enable(struct elink_params *params, REG_WR(sc, umac_base + UMAC_REG_MAC_ADDR0, ((params->mac_addr[2] << 24) | (params->mac_addr[3] << 16) | - (params->mac_addr[4] << 8) | (params->mac_addr[5]))); + (params->mac_addr[4] << 8) | + (params->mac_addr[5]))); REG_WR(sc, umac_base + UMAC_REG_MAC_ADDR1, - ((params->mac_addr[0] << 8) | (params->mac_addr[1]))); + ((params->mac_addr[0] << 8) | + (params->mac_addr[1]))); /* Enable RX and TX */ val &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN; - val |= UMAC_COMMAND_CONFIG_REG_TX_ENA | UMAC_COMMAND_CONFIG_REG_RX_ENA; + val |= UMAC_COMMAND_CONFIG_REG_TX_ENA | + UMAC_COMMAND_CONFIG_REG_RX_ENA; REG_WR(sc, umac_base + UMAC_REG_COMMAND_CONFIG, val); DELAY(50); @@ -1426,7 +2447,8 @@ static void elink_xmac_init(struct elink_params *params, uint32_t max_speed) is_port4mode && (REG_RD(sc, MISC_REG_RESET_REG_2) & MISC_REGISTERS_RESET_REG_2_XMAC)) { - PMD_DRV_LOG(DEBUG, "XMAC already out of reset in 4-port mode"); + ELINK_DEBUG_P0(sc, + "XMAC already out of reset in 4-port mode"); return; } @@ -1438,7 +2460,7 @@ static void elink_xmac_init(struct elink_params *params, uint32_t max_speed) REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, MISC_REGISTERS_RESET_REG_2_XMAC); if (is_port4mode) { - PMD_DRV_LOG(DEBUG, "Init XMAC to 2 ports x 10G per path"); + ELINK_DEBUG_P0(sc, "Init XMAC to 2 ports x 10G per path"); /* Set the number of ports on the system side to up to 2 */ REG_WR(sc, MISC_REG_XMAC_CORE_PORT_MODE, 1); @@ -1449,13 +2471,13 @@ static void elink_xmac_init(struct elink_params *params, uint32_t max_speed) /* Set the number of ports on the system side to 1 */ REG_WR(sc, MISC_REG_XMAC_CORE_PORT_MODE, 0); if (max_speed == ELINK_SPEED_10000) { - PMD_DRV_LOG(DEBUG, - "Init XMAC to 10G x 1 port per path"); + ELINK_DEBUG_P0(sc, + "Init XMAC to 10G x 1 port per path"); /* Set the number of ports on the Warp Core to 10G */ REG_WR(sc, MISC_REG_XMAC_PHY_PORT_MODE, 3); } else { - PMD_DRV_LOG(DEBUG, - "Init XMAC to 20G x 2 ports per path"); + ELINK_DEBUG_P0(sc, + "Init XMAC to 20G x 2 ports per path"); /* Set the number of ports on the Warp Core to 20G */ REG_WR(sc, MISC_REG_XMAC_PHY_PORT_MODE, 1); } @@ -1477,7 +2499,8 @@ static void elink_set_xmac_rxtx(struct elink_params *params, uint8_t en) uint32_t pfc_ctrl, xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; uint32_t val; - if (REG_RD(sc, MISC_REG_RESET_REG_2) & MISC_REGISTERS_RESET_REG_2_XMAC) { + if (REG_RD(sc, MISC_REG_RESET_REG_2) & + MISC_REGISTERS_RESET_REG_2_XMAC) { /* Send an indication to change the state in the NIG back to XON * Clearing this bit enables the next set of this bit to get * rising edge @@ -1487,7 +2510,7 @@ static void elink_set_xmac_rxtx(struct elink_params *params, uint8_t en) (pfc_ctrl & ~(1 << 1))); REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL_HI, (pfc_ctrl | (1 << 1))); - PMD_DRV_LOG(DEBUG, "Disable XMAC on port %x", port); + ELINK_DEBUG_P1(sc, "Disable XMAC on port %x", port); val = REG_RD(sc, xmac_base + XMAC_REG_CTRL); if (en) val |= (XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN); @@ -1498,11 +2521,11 @@ static void elink_set_xmac_rxtx(struct elink_params *params, uint8_t en) } static elink_status_t elink_xmac_enable(struct elink_params *params, - struct elink_vars *vars, uint8_t lb) + struct elink_vars *vars, uint8_t lb) { uint32_t val, xmac_base; struct bnx2x_softc *sc = params->sc; - PMD_DRV_LOG(DEBUG, "enabling XMAC"); + ELINK_DEBUG_P0(sc, "enabling XMAC"); xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; @@ -1536,10 +2559,10 @@ static elink_status_t elink_xmac_enable(struct elink_params *params, REG_WR(sc, xmac_base + XMAC_REG_TX_CTRL, 0xC800); /* update PFC */ - elink_update_pfc_xmac(params, vars); + elink_update_pfc_xmac(params, vars, 0); if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) { - PMD_DRV_LOG(DEBUG, "Setting XMAC for EEE"); + ELINK_DEBUG_P0(sc, "Setting XMAC for EEE"); REG_WR(sc, xmac_base + XMAC_REG_EEE_TIMERS_HI, 0x1380008); REG_WR(sc, xmac_base + XMAC_REG_EEE_CTRL, 0x1); } else { @@ -1568,14 +2591,14 @@ static elink_status_t elink_xmac_enable(struct elink_params *params, } static elink_status_t elink_emac_enable(struct elink_params *params, - struct elink_vars *vars, uint8_t lb) + struct elink_vars *vars, uint8_t lb) { struct bnx2x_softc *sc = params->sc; uint8_t port = params->port; uint32_t emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; uint32_t val; - PMD_DRV_LOG(DEBUG, "enabling EMAC"); + ELINK_DEBUG_P0(sc, "enabling EMAC"); /* Disable BMAC */ REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, @@ -1584,19 +2607,39 @@ static elink_status_t elink_emac_enable(struct elink_params *params, /* enable emac and not bmac */ REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + port * 4, 1); +#ifdef ELINK_INCLUDE_EMUL + /* for paladium */ + if (CHIP_REV_IS_EMUL(sc)) { + /* Use lane 1 (of lanes 0-3) */ + REG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port * 4, 1); + REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 1); + } + /* for fpga */ + else +#endif +#ifdef ELINK_INCLUDE_FPGA + if (CHIP_REV_IS_FPGA(sc)) { + /* Use lane 1 (of lanes 0-3) */ + ELINK_DEBUG_P0(sc, "elink_emac_enable: Setting FPGA"); + + REG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port * 4, 1); + REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 0); + } else +#endif + /* ASIC */ if (vars->phy_flags & PHY_XGXS_FLAG) { uint32_t ser_lane = ((params->lane_config & - PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> - PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); + PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> + PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); - PMD_DRV_LOG(DEBUG, "XGXS"); + ELINK_DEBUG_P0(sc, "XGXS"); /* select the master lanes (out of 0-3) */ REG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port * 4, ser_lane); /* select XGXS */ REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 1); - } else { /* SerDes */ - PMD_DRV_LOG(DEBUG, "SerDes"); + } else { /* SerDes */ + ELINK_DEBUG_P0(sc, "SerDes"); /* select SerDes */ REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 0); } @@ -1606,28 +2649,39 @@ static elink_status_t elink_emac_enable(struct elink_params *params, elink_bits_en(sc, emac_base + EMAC_REG_EMAC_TX_MODE, EMAC_TX_MODE_RESET); - /* pause enable/disable */ - elink_bits_dis(sc, emac_base + EMAC_REG_EMAC_RX_MODE, - EMAC_RX_MODE_FLOW_EN); - - elink_bits_dis(sc, emac_base + EMAC_REG_EMAC_TX_MODE, - (EMAC_TX_MODE_EXT_PAUSE_EN | - EMAC_TX_MODE_FLOW_EN)); - if (!(params->feature_config_flags & - ELINK_FEATURE_CONFIG_PFC_ENABLED)) { - if (vars->flow_ctrl & ELINK_FLOW_CTRL_RX) - elink_bits_en(sc, emac_base + - EMAC_REG_EMAC_RX_MODE, - EMAC_RX_MODE_FLOW_EN); +#if defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA) + if (CHIP_REV_IS_SLOW(sc)) { + /* config GMII mode */ + val = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE); + elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MODE, + (val | EMAC_MODE_PORT_GMII)); + } else { /* ASIC */ +#endif + /* pause enable/disable */ + elink_bits_dis(sc, emac_base + EMAC_REG_EMAC_RX_MODE, + EMAC_RX_MODE_FLOW_EN); - if (vars->flow_ctrl & ELINK_FLOW_CTRL_TX) - elink_bits_en(sc, emac_base + - EMAC_REG_EMAC_TX_MODE, - (EMAC_TX_MODE_EXT_PAUSE_EN | - EMAC_TX_MODE_FLOW_EN)); - } else - elink_bits_en(sc, emac_base + EMAC_REG_EMAC_TX_MODE, - EMAC_TX_MODE_FLOW_EN); + elink_bits_dis(sc, emac_base + EMAC_REG_EMAC_TX_MODE, + (EMAC_TX_MODE_EXT_PAUSE_EN | + EMAC_TX_MODE_FLOW_EN)); + if (!(params->feature_config_flags & + ELINK_FEATURE_CONFIG_PFC_ENABLED)) { + if (vars->flow_ctrl & ELINK_FLOW_CTRL_RX) + elink_bits_en(sc, emac_base + + EMAC_REG_EMAC_RX_MODE, + EMAC_RX_MODE_FLOW_EN); + + if (vars->flow_ctrl & ELINK_FLOW_CTRL_TX) + elink_bits_en(sc, emac_base + + EMAC_REG_EMAC_TX_MODE, + (EMAC_TX_MODE_EXT_PAUSE_EN | + EMAC_TX_MODE_FLOW_EN)); + } else + elink_bits_en(sc, emac_base + EMAC_REG_EMAC_TX_MODE, + EMAC_TX_MODE_FLOW_EN); +#if defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA) + } +#endif /* KEEP_VLAN_TAG, promiscuous */ val = REG_RD(sc, emac_base + EMAC_REG_EMAC_RX_MODE); @@ -1642,18 +2696,18 @@ static elink_status_t elink_emac_enable(struct elink_params *params, */ elink_cb_reg_write(sc, emac_base + EMAC_REG_RX_PFC_MODE, 0); if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) { - PMD_DRV_LOG(DEBUG, "PFC is enabled"); + ELINK_DEBUG_P0(sc, "PFC is enabled"); /* Enable PFC again */ elink_cb_reg_write(sc, emac_base + EMAC_REG_RX_PFC_MODE, - EMAC_REG_RX_PFC_MODE_RX_EN | - EMAC_REG_RX_PFC_MODE_TX_EN | - EMAC_REG_RX_PFC_MODE_PRIORITIES); + EMAC_REG_RX_PFC_MODE_RX_EN | + EMAC_REG_RX_PFC_MODE_TX_EN | + EMAC_REG_RX_PFC_MODE_PRIORITIES); elink_cb_reg_write(sc, emac_base + EMAC_REG_RX_PFC_PARAM, - ((0x0101 << - EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) | - (0x00ff << - EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT))); + ((0x0101 << + EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) | + (0x00ff << + EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT))); val |= EMAC_RX_MODE_KEEP_MAC_CONTROL; } elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_RX_MODE, val); @@ -1671,9 +2725,8 @@ static elink_status_t elink_emac_enable(struct elink_params *params, /* Enable emac for jumbo packets */ elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_RX_MTU_SIZE, - (EMAC_RX_MTU_SIZE_JUMBO_ENA | - (ELINK_ETH_MAX_JUMBO_PACKET_SIZE + - ELINK_ETH_OVREHEAD))); + (EMAC_RX_MTU_SIZE_JUMBO_ENA | + (ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD))); /* Strip CRC */ REG_WR(sc, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port * 4, 0x1); @@ -1687,13 +2740,23 @@ static elink_status_t elink_emac_enable(struct elink_params *params, REG_WR(sc, NIG_REG_EMAC0_IN_EN + port * 4, 0x1); val = 0; if ((params->feature_config_flags & - ELINK_FEATURE_CONFIG_PFC_ENABLED) || + ELINK_FEATURE_CONFIG_PFC_ENABLED) || (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)) val = 1; REG_WR(sc, NIG_REG_EMAC0_PAUSE_OUT_EN + port * 4, val); REG_WR(sc, NIG_REG_EGRESS_EMAC0_OUT_EN + port * 4, 0x1); +#ifdef ELINK_INCLUDE_EMUL + if (CHIP_REV_IS_EMUL(sc)) { + /* Take the BigMac out of reset */ + REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, + (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); + + /* Enable access for bmac registers */ + REG_WR(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4, 0x1); + } else +#endif REG_WR(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4, 0x0); vars->mac_type = ELINK_MAC_TYPE_EMAC; @@ -1705,13 +2768,13 @@ static void elink_update_pfc_bmac1(struct elink_params *params, { uint32_t wb_data[2]; struct bnx2x_softc *sc = params->sc; - uint32_t bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM : - NIG_REG_INGRESS_BMAC0_MEM; + uint32_t bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM : + NIG_REG_INGRESS_BMAC0_MEM; uint32_t val = 0x14; if ((!(params->feature_config_flags & - ELINK_FEATURE_CONFIG_PFC_ENABLED)) && - (vars->flow_ctrl & ELINK_FLOW_CTRL_RX)) + ELINK_FEATURE_CONFIG_PFC_ENABLED)) && + (vars->flow_ctrl & ELINK_FLOW_CTRL_RX)) /* Enable BigMAC to react on received Pause packets */ val |= (1 << 5); wb_data[0] = val; @@ -1722,7 +2785,7 @@ static void elink_update_pfc_bmac1(struct elink_params *params, val = 0xc0; if (!(params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) && - (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)) + (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)) val |= 0x800000; wb_data[0] = val; wb_data[1] = 0; @@ -1730,7 +2793,8 @@ static void elink_update_pfc_bmac1(struct elink_params *params, } static void elink_update_pfc_bmac2(struct elink_params *params, - struct elink_vars *vars, uint8_t is_lb) + struct elink_vars *vars, + uint8_t is_lb) { /* Set rx control: Strip CRC and enable BigMAC to relay * control packets to the system as well @@ -1738,12 +2802,12 @@ static void elink_update_pfc_bmac2(struct elink_params *params, uint32_t wb_data[2]; struct bnx2x_softc *sc = params->sc; uint32_t bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM : - NIG_REG_INGRESS_BMAC0_MEM; + NIG_REG_INGRESS_BMAC0_MEM; uint32_t val = 0x14; if ((!(params->feature_config_flags & - ELINK_FEATURE_CONFIG_PFC_ENABLED)) && - (vars->flow_ctrl & ELINK_FLOW_CTRL_RX)) + ELINK_FEATURE_CONFIG_PFC_ENABLED)) && + (vars->flow_ctrl & ELINK_FLOW_CTRL_RX)) /* Enable BigMAC to react on received Pause packets */ val |= (1 << 5); wb_data[0] = val; @@ -1754,7 +2818,7 @@ static void elink_update_pfc_bmac2(struct elink_params *params, /* Tx control */ val = 0xc0; if (!(params->feature_config_flags & - ELINK_FEATURE_CONFIG_PFC_ENABLED) && + ELINK_FEATURE_CONFIG_PFC_ENABLED) && (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)) val |= 0x800000; wb_data[0] = val; @@ -1762,21 +2826,21 @@ static void elink_update_pfc_bmac2(struct elink_params *params, REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2); if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) { - PMD_DRV_LOG(DEBUG, "PFC is enabled"); + ELINK_DEBUG_P0(sc, "PFC is enabled"); /* Enable PFC RX & TX & STATS and set 8 COS */ wb_data[0] = 0x0; - wb_data[0] |= (1 << 0); /* RX */ - wb_data[0] |= (1 << 1); /* TX */ - wb_data[0] |= (1 << 2); /* Force initial Xon */ - wb_data[0] |= (1 << 3); /* 8 cos */ - wb_data[0] |= (1 << 5); /* STATS */ + wb_data[0] |= (1 << 0); /* RX */ + wb_data[0] |= (1 << 1); /* TX */ + wb_data[0] |= (1 << 2); /* Force initial Xon */ + wb_data[0] |= (1 << 3); /* 8 cos */ + wb_data[0] |= (1 << 5); /* STATS */ wb_data[1] = 0; REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2); /* Clear the force Xon */ wb_data[0] &= ~(1 << 2); } else { - PMD_DRV_LOG(DEBUG, "PFC is disabled"); + ELINK_DEBUG_P0(sc, "PFC is disabled"); /* Disable PFC RX & TX & STATS and set 8 COS */ wb_data[0] = 0x8; wb_data[1] = 0; @@ -1791,7 +2855,7 @@ static void elink_update_pfc_bmac2(struct elink_params *params, */ val = 0x8000; if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) - val |= (1 << 16); /* enable automatic re-send */ + val |= (1 << 16); /* enable automatic re-send */ wb_data[0] = val; wb_data[1] = 0; @@ -1799,10 +2863,10 @@ static void elink_update_pfc_bmac2(struct elink_params *params, wb_data, 2); /* mac control */ - val = 0x3; /* Enable RX and TX */ + val = 0x3; /* Enable RX and TX */ if (is_lb) { - val |= 0x4; /* Local loopback */ - PMD_DRV_LOG(DEBUG, "enable bmac loopback"); + val |= 0x4; /* Local loopback */ + ELINK_DEBUG_P0(sc, "enable bmac loopback"); } /* When PFC enabled, Pass pause frames towards the NIG. */ if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) @@ -1814,47 +2878,46 @@ static void elink_update_pfc_bmac2(struct elink_params *params, } /****************************************************************************** -* Description: -* This function is needed because NIG ARB_CREDIT_WEIGHT_X are -* not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable. -******************************************************************************/ + * Description: + * This function is needed because NIG ARB_CREDIT_WEIGHT_X are + * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable. + ******************************************************************************/ static elink_status_t elink_pfc_nig_rx_priority_mask(struct bnx2x_softc *sc, - uint8_t cos_entry, - uint32_t priority_mask, - uint8_t port) + uint8_t cos_entry, + uint32_t priority_mask, uint8_t port) { uint32_t nig_reg_rx_priority_mask_add = 0; switch (cos_entry) { case 0: - nig_reg_rx_priority_mask_add = (port) ? - NIG_REG_P1_RX_COS0_PRIORITY_MASK : - NIG_REG_P0_RX_COS0_PRIORITY_MASK; + nig_reg_rx_priority_mask_add = (port) ? + NIG_REG_P1_RX_COS0_PRIORITY_MASK : + NIG_REG_P0_RX_COS0_PRIORITY_MASK; break; case 1: - nig_reg_rx_priority_mask_add = (port) ? - NIG_REG_P1_RX_COS1_PRIORITY_MASK : - NIG_REG_P0_RX_COS1_PRIORITY_MASK; + nig_reg_rx_priority_mask_add = (port) ? + NIG_REG_P1_RX_COS1_PRIORITY_MASK : + NIG_REG_P0_RX_COS1_PRIORITY_MASK; break; case 2: - nig_reg_rx_priority_mask_add = (port) ? - NIG_REG_P1_RX_COS2_PRIORITY_MASK : - NIG_REG_P0_RX_COS2_PRIORITY_MASK; + nig_reg_rx_priority_mask_add = (port) ? + NIG_REG_P1_RX_COS2_PRIORITY_MASK : + NIG_REG_P0_RX_COS2_PRIORITY_MASK; break; case 3: if (port) - return ELINK_STATUS_ERROR; - nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK; + return ELINK_STATUS_ERROR; + nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK; break; case 4: if (port) - return ELINK_STATUS_ERROR; - nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK; + return ELINK_STATUS_ERROR; + nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK; break; case 5: if (port) - return ELINK_STATUS_ERROR; - nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK; + return ELINK_STATUS_ERROR; + nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK; break; } @@ -1862,7 +2925,6 @@ static elink_status_t elink_pfc_nig_rx_priority_mask(struct bnx2x_softc *sc, return ELINK_STATUS_OK; } - static void elink_update_mng(struct elink_params *params, uint32_t link_status) { struct bnx2x_softc *sc = params->sc; @@ -1872,31 +2934,20 @@ static void elink_update_mng(struct elink_params *params, uint32_t link_status) port_mb[params->port].link_status), link_status); } -static void elink_update_link_attr(struct elink_params *params, - uint32_t link_attr) -{ - struct bnx2x_softc *sc = params->sc; - - if (SHMEM2_HAS(sc, link_attr_sync)) - REG_WR(sc, params->shmem2_base + - offsetof(struct shmem2_region, - link_attr_sync[params->port]), link_attr); -} - static void elink_update_pfc_nig(struct elink_params *params, - struct elink_nig_brb_pfc_port_params - *nig_params) + __rte_unused struct elink_vars *vars, + struct elink_nig_brb_pfc_port_params *nig_params) { - uint32_t xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = - 0; + uint32_t xcm_mask = 0, ppp_enable = 0, pause_enable = 0; + uint32_t llfc_out_en = 0; uint32_t llfc_enable = 0, xcm_out_en = 0, hwpfc_enable = 0; uint32_t pkt_priority_to_cos = 0; struct bnx2x_softc *sc = params->sc; uint8_t port = params->port; int set_pfc = params->feature_config_flags & - ELINK_FEATURE_CONFIG_PFC_ENABLED; - PMD_DRV_LOG(DEBUG, "updating pfc nig parameters"); + ELINK_FEATURE_CONFIG_PFC_ENABLED; + ELINK_DEBUG_P0(sc, "updating pfc nig parameters"); /* When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set * MAC control frames (that are not pause packets) @@ -1916,19 +2967,19 @@ static void elink_update_pfc_nig(struct elink_params *params, else ppp_enable = 1; xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN : - NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN); + NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN); xcm_out_en = 0; hwpfc_enable = 1; - } else { + } else { if (nig_params) { llfc_out_en = nig_params->llfc_out_en; llfc_enable = nig_params->llfc_enable; pause_enable = nig_params->pause_enable; - } else /* Default non PFC mode - PAUSE */ + } else /* Default non PFC mode - PAUSE */ pause_enable = 1; xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN : - NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN); + NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN); xcm_out_en = 1; } @@ -1965,9 +3016,7 @@ static void elink_update_pfc_nig(struct elink_params *params, for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++) elink_pfc_nig_rx_priority_mask(sc, i, - nig_params-> - rx_cos_priority_mask[i], - port); + nig_params->rx_cos_priority_mask[i], port); REG_WR(sc, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 : NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0, @@ -1978,13 +3027,13 @@ static void elink_update_pfc_nig(struct elink_params *params, nig_params->llfc_low_priority_classes); } REG_WR(sc, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS : - NIG_REG_P0_PKT_PRIORITY_TO_COS, pkt_priority_to_cos); + NIG_REG_P0_PKT_PRIORITY_TO_COS, + pkt_priority_to_cos); } elink_status_t elink_update_pfc(struct elink_params *params, - struct elink_vars *vars, - struct elink_nig_brb_pfc_port_params - *pfc_params) + struct elink_vars *vars, + struct elink_nig_brb_pfc_port_params *pfc_params) { /* The PFC and pause are orthogonal to one another, meaning when * PFC is enabled, the pause are disabled, and when PFC is @@ -1992,7 +3041,6 @@ elink_status_t elink_update_pfc(struct elink_params *params, */ uint32_t val; struct bnx2x_softc *sc = params->sc; - elink_status_t elink_status = ELINK_STATUS_OK; uint8_t bmac_loopback = (params->loopback_mode == ELINK_LOOPBACK_BMAC); if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) @@ -2003,24 +3051,24 @@ elink_status_t elink_update_pfc(struct elink_params *params, elink_update_mng(params, vars->link_status); /* Update NIG params */ - elink_update_pfc_nig(params, pfc_params); + elink_update_pfc_nig(params, vars, pfc_params); if (!vars->link_up) - return elink_status; + return ELINK_STATUS_OK; - PMD_DRV_LOG(DEBUG, "About to update PFC in BMAC"); + ELINK_DEBUG_P0(sc, "About to update PFC in BMAC"); if (CHIP_IS_E3(sc)) { if (vars->mac_type == ELINK_MAC_TYPE_XMAC) - elink_update_pfc_xmac(params, vars); + elink_update_pfc_xmac(params, vars, 0); } else { val = REG_RD(sc, MISC_REG_RESET_REG_2); if ((val & (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) == 0) { - PMD_DRV_LOG(DEBUG, "About to update PFC in EMAC"); + ELINK_DEBUG_P0(sc, "About to update PFC in EMAC"); elink_emac_enable(params, vars, 0); - return elink_status; + return ELINK_STATUS_OK; } if (CHIP_IS_E2(sc)) elink_update_pfc_bmac2(params, vars, bmac_loopback); @@ -2034,20 +3082,21 @@ elink_status_t elink_update_pfc(struct elink_params *params, val = 1; REG_WR(sc, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port * 4, val); } - return elink_status; + return ELINK_STATUS_OK; } static elink_status_t elink_bmac1_enable(struct elink_params *params, - struct elink_vars *vars, uint8_t is_lb) + struct elink_vars *vars, + uint8_t is_lb) { struct bnx2x_softc *sc = params->sc; uint8_t port = params->port; uint32_t bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : - NIG_REG_INGRESS_BMAC0_MEM; + NIG_REG_INGRESS_BMAC0_MEM; uint32_t wb_data[2]; uint32_t val; - PMD_DRV_LOG(DEBUG, "Enabling BigMAC1"); + ELINK_DEBUG_P0(sc, "Enabling BigMAC1"); /* XGXS control */ wb_data[0] = 0x3c; @@ -2057,16 +3106,18 @@ static elink_status_t elink_bmac1_enable(struct elink_params *params, /* TX MAC SA */ wb_data[0] = ((params->mac_addr[2] << 24) | - (params->mac_addr[3] << 16) | - (params->mac_addr[4] << 8) | params->mac_addr[5]); - wb_data[1] = ((params->mac_addr[0] << 8) | params->mac_addr[1]); + (params->mac_addr[3] << 16) | + (params->mac_addr[4] << 8) | + params->mac_addr[5]); + wb_data[1] = ((params->mac_addr[0] << 8) | + params->mac_addr[1]); REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2); /* MAC control */ val = 0x3; if (is_lb) { val |= 0x4; - PMD_DRV_LOG(DEBUG, "enable bmac loopback"); + ELINK_DEBUG_P0(sc, "enable bmac loopback"); } wb_data[0] = val; wb_data[1] = 0; @@ -2094,20 +3145,30 @@ static elink_status_t elink_bmac1_enable(struct elink_params *params, wb_data[1] = 0; REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS, wb_data, 2); +#ifdef ELINK_INCLUDE_EMUL + /* Fix for emulation */ + if (CHIP_REV_IS_EMUL(sc)) { + wb_data[0] = 0xf000; + wb_data[1] = 0; + REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_TX_PAUSE_THRESHOLD, + wb_data, 2); + } +#endif return ELINK_STATUS_OK; } static elink_status_t elink_bmac2_enable(struct elink_params *params, - struct elink_vars *vars, uint8_t is_lb) + struct elink_vars *vars, + uint8_t is_lb) { struct bnx2x_softc *sc = params->sc; uint8_t port = params->port; uint32_t bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : - NIG_REG_INGRESS_BMAC0_MEM; + NIG_REG_INGRESS_BMAC0_MEM; uint32_t wb_data[2]; - PMD_DRV_LOG(DEBUG, "Enabling BigMAC2"); + ELINK_DEBUG_P0(sc, "Enabling BigMAC2"); wb_data[0] = 0; wb_data[1] = 0; @@ -2124,9 +3185,11 @@ static elink_status_t elink_bmac2_enable(struct elink_params *params, /* TX MAC SA */ wb_data[0] = ((params->mac_addr[2] << 24) | - (params->mac_addr[3] << 16) | - (params->mac_addr[4] << 8) | params->mac_addr[5]); - wb_data[1] = ((params->mac_addr[0] << 8) | params->mac_addr[1]); + (params->mac_addr[3] << 16) | + (params->mac_addr[4] << 8) | + params->mac_addr[5]); + wb_data[1] = ((params->mac_addr[0] << 8) | + params->mac_addr[1]); REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR, wb_data, 2); @@ -2161,8 +3224,8 @@ static elink_status_t elink_bmac2_enable(struct elink_params *params, } static elink_status_t elink_bmac_enable(struct elink_params *params, - struct elink_vars *vars, - uint8_t is_lb, uint8_t reset_bmac) + struct elink_vars *vars, + uint8_t is_lb, uint8_t reset_bmac) { elink_status_t rc = ELINK_STATUS_OK; uint8_t port = params->port; @@ -2181,7 +3244,7 @@ static elink_status_t elink_bmac_enable(struct elink_params *params, /* Enable access for bmac registers */ REG_WR(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4, 0x1); - /* Enable BMAC according to BMAC type */ + /* Enable BMAC according to BMAC type*/ if (CHIP_IS_E2(sc)) rc = elink_bmac2_enable(params, vars, is_lb); else @@ -2191,7 +3254,7 @@ static elink_status_t elink_bmac_enable(struct elink_params *params, REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + port * 4, 0x0); val = 0; if ((params->feature_config_flags & - ELINK_FEATURE_CONFIG_PFC_ENABLED) || + ELINK_FEATURE_CONFIG_PFC_ENABLED) || (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)) val = 1; REG_WR(sc, NIG_REG_BMAC0_PAUSE_OUT_EN + port * 4, val); @@ -2205,13 +3268,15 @@ static elink_status_t elink_bmac_enable(struct elink_params *params, return rc; } -static void elink_set_bmac_rx(struct bnx2x_softc *sc, uint8_t port, uint8_t en) +static void elink_set_bmac_rx(struct bnx2x_softc *sc, + __rte_unused uint32_t chip_id, + uint8_t port, uint8_t en) { uint32_t bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : - NIG_REG_INGRESS_BMAC0_MEM; + NIG_REG_INGRESS_BMAC0_MEM; uint32_t wb_data[2]; - uint32_t nig_bmac_enable = - REG_RD(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4); + uint32_t nig_bmac_enable = REG_RD(sc, NIG_REG_BMAC0_REGS_OUT_EN + + port * 4); if (CHIP_IS_E2(sc)) bmac_addr += BIGMAC2_REGISTER_BMAC_CONTROL; @@ -2219,7 +3284,8 @@ static void elink_set_bmac_rx(struct bnx2x_softc *sc, uint8_t port, uint8_t en) bmac_addr += BIGMAC_REGISTER_BMAC_CONTROL; /* Only if the bmac is out of reset */ if (REG_RD(sc, MISC_REG_RESET_REG_2) & - (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) && nig_bmac_enable) { + (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) && + nig_bmac_enable) { /* Clear Rx Enable bit in BMAC_CONTROL register */ REG_RD_DMAE(sc, bmac_addr, wb_data, 2); if (en) @@ -2232,7 +3298,8 @@ static void elink_set_bmac_rx(struct bnx2x_softc *sc, uint8_t port, uint8_t en) } static elink_status_t elink_pbf_update(struct elink_params *params, - uint32_t flow_ctrl, uint32_t line_speed) + uint32_t flow_ctrl, + uint32_t line_speed) { struct bnx2x_softc *sc = params->sc; uint8_t port = params->port; @@ -2245,7 +3312,7 @@ static elink_status_t elink_pbf_update(struct elink_params *params, /* Wait for init credit */ init_crd = REG_RD(sc, PBF_REG_P0_INIT_CRD + port * 4); crd = REG_RD(sc, PBF_REG_P0_CREDIT + port * 8); - PMD_DRV_LOG(DEBUG, "init_crd 0x%x crd 0x%x", init_crd, crd); + ELINK_DEBUG_P2(sc, "init_crd 0x%x crd 0x%x", init_crd, crd); while ((init_crd != crd) && count) { DELAY(1000 * 5); @@ -2254,24 +3321,25 @@ static elink_status_t elink_pbf_update(struct elink_params *params, } crd = REG_RD(sc, PBF_REG_P0_CREDIT + port * 8); if (init_crd != crd) { - PMD_DRV_LOG(DEBUG, "BUG! init_crd 0x%x != crd 0x%x", - init_crd, crd); + ELINK_DEBUG_P2(sc, "BUG! init_crd 0x%x != crd 0x%x", + init_crd, crd); return ELINK_STATUS_ERROR; } if (flow_ctrl & ELINK_FLOW_CTRL_RX || line_speed == ELINK_SPEED_10 || line_speed == ELINK_SPEED_100 || - line_speed == ELINK_SPEED_1000 || line_speed == ELINK_SPEED_2500) { + line_speed == ELINK_SPEED_1000 || + line_speed == ELINK_SPEED_2500) { REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port * 4, 1); /* Update threshold */ REG_WR(sc, PBF_REG_P0_ARB_THRSH + port * 4, 0); /* Update init credit */ - init_crd = 778; /* (800-18-4) */ + init_crd = 778; /* (800-18-4) */ } else { uint32_t thresh = (ELINK_ETH_MAX_JUMBO_PACKET_SIZE + - ELINK_ETH_OVREHEAD) / 16; + ELINK_ETH_OVREHEAD) / 16; REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port * 4, 0); /* Update threshold */ REG_WR(sc, PBF_REG_P0_ARB_THRSH + port * 4, thresh); @@ -2281,14 +3349,14 @@ static elink_status_t elink_pbf_update(struct elink_params *params, init_crd = thresh + 553 - 22; break; default: - PMD_DRV_LOG(DEBUG, "Invalid line_speed 0x%x", - line_speed); + ELINK_DEBUG_P1(sc, "Invalid line_speed 0x%x", + line_speed); return ELINK_STATUS_ERROR; } } REG_WR(sc, PBF_REG_P0_INIT_CRD + port * 4, init_crd); - PMD_DRV_LOG(DEBUG, "PBF updated to speed %d credit %d", - line_speed, init_crd); + ELINK_DEBUG_P2(sc, "PBF updated to speed %d credit %d", + line_speed, init_crd); /* Probe the credit changes */ REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 0x1); @@ -2316,7 +3384,7 @@ static elink_status_t elink_pbf_update(struct elink_params *params, * the emac_base for the CL45 read/writes operations */ static uint32_t elink_get_emac_base(struct bnx2x_softc *sc, - uint32_t mdc_mdio_access, uint8_t port) + uint32_t mdc_mdio_access, uint8_t port) { uint32_t emac_base = 0; switch (mdc_mdio_access) { @@ -2364,7 +3432,8 @@ static elink_status_t elink_cl22_write(struct bnx2x_softc *sc, /* Address */ tmp = ((phy->addr << 21) | (reg << 16) | val | - EMAC_MDIO_COMM_COMMAND_WRITE_22 | EMAC_MDIO_COMM_START_BUSY); + EMAC_MDIO_COMM_COMMAND_WRITE_22 | + EMAC_MDIO_COMM_START_BUSY); REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); for (i = 0; i < 50; i++) { @@ -2377,7 +3446,7 @@ static elink_status_t elink_cl22_write(struct bnx2x_softc *sc, } } if (tmp & EMAC_MDIO_COMM_START_BUSY) { - PMD_DRV_LOG(DEBUG, "write phy register failed"); + ELINK_DEBUG_P0(sc, "write phy register failed"); rc = ELINK_STATUS_TIMEOUT; } REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode); @@ -2386,7 +3455,7 @@ static elink_status_t elink_cl22_write(struct bnx2x_softc *sc, static elink_status_t elink_cl22_read(struct bnx2x_softc *sc, struct elink_phy *phy, - uint16_t reg, uint16_t * ret_val) + uint16_t reg, uint16_t *ret_val) { uint32_t val, mode; uint16_t i; @@ -2399,7 +3468,8 @@ static elink_status_t elink_cl22_read(struct bnx2x_softc *sc, /* Address */ val = ((phy->addr << 21) | (reg << 16) | - EMAC_MDIO_COMM_COMMAND_READ_22 | EMAC_MDIO_COMM_START_BUSY); + EMAC_MDIO_COMM_COMMAND_READ_22 | + EMAC_MDIO_COMM_START_BUSY); REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); for (i = 0; i < 50; i++) { @@ -2407,13 +3477,13 @@ static elink_status_t elink_cl22_read(struct bnx2x_softc *sc, val = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); if (!(val & EMAC_MDIO_COMM_START_BUSY)) { - *ret_val = (uint16_t) (val & EMAC_MDIO_COMM_DATA); + *ret_val = (uint16_t)(val & EMAC_MDIO_COMM_DATA); DELAY(5); break; } } if (val & EMAC_MDIO_COMM_START_BUSY) { - PMD_DRV_LOG(DEBUG, "read phy register failed"); + ELINK_DEBUG_P0(sc, "read phy register failed"); *ret_val = 0; rc = ELINK_STATUS_TIMEOUT; @@ -2426,14 +3496,17 @@ static elink_status_t elink_cl22_read(struct bnx2x_softc *sc, /* CL45 access functions */ /******************************************************************/ static elink_status_t elink_cl45_read(struct bnx2x_softc *sc, - struct elink_phy *phy, uint8_t devad, - uint16_t reg, uint16_t * ret_val) + struct elink_phy *phy, + uint8_t devad, uint16_t reg, uint16_t *ret_val) { uint32_t val; uint16_t i; elink_status_t rc = ELINK_STATUS_OK; + uint32_t chip_id; if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_G) { - elink_set_mdio_clk(sc, phy->mdio_ctrl); + chip_id = (REG_RD(sc, MISC_REG_CHIP_NUM) << 16) | + ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12); + elink_set_mdio_clk(sc, chip_id, phy->mdio_ctrl); } if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0) @@ -2441,7 +3514,8 @@ static elink_status_t elink_cl45_read(struct bnx2x_softc *sc, EMAC_MDIO_STATUS_10MB); /* Address */ val = ((phy->addr << 21) | (devad << 16) | reg | - EMAC_MDIO_COMM_COMMAND_ADDRESS | EMAC_MDIO_COMM_START_BUSY); + EMAC_MDIO_COMM_COMMAND_ADDRESS | + EMAC_MDIO_COMM_START_BUSY); REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); for (i = 0; i < 50; i++) { @@ -2454,8 +3528,9 @@ static elink_status_t elink_cl45_read(struct bnx2x_softc *sc, } } if (val & EMAC_MDIO_COMM_START_BUSY) { - PMD_DRV_LOG(DEBUG, "read phy register failed"); - elink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout" + ELINK_DEBUG_P0(sc, "read phy register failed"); + elink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); + /* "MDC/MDIO access timeout" */ *ret_val = 0; rc = ELINK_STATUS_TIMEOUT; @@ -2472,14 +3547,16 @@ static elink_status_t elink_cl45_read(struct bnx2x_softc *sc, val = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); if (!(val & EMAC_MDIO_COMM_START_BUSY)) { - *ret_val = - (uint16_t) (val & EMAC_MDIO_COMM_DATA); + *ret_val = (uint16_t) + (val & EMAC_MDIO_COMM_DATA); break; } } if (val & EMAC_MDIO_COMM_START_BUSY) { - PMD_DRV_LOG(DEBUG, "read phy register failed"); - elink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout" + ELINK_DEBUG_P0(sc, "read phy register failed"); + elink_cb_event_log(sc, + ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); + /* "MDC/MDIO access timeout" */ *ret_val = 0; rc = ELINK_STATUS_TIMEOUT; @@ -2501,14 +3578,17 @@ static elink_status_t elink_cl45_read(struct bnx2x_softc *sc, } static elink_status_t elink_cl45_write(struct bnx2x_softc *sc, - struct elink_phy *phy, uint8_t devad, - uint16_t reg, uint16_t val) + struct elink_phy *phy, + uint8_t devad, uint16_t reg, uint16_t val) { uint32_t tmp; uint8_t i; elink_status_t rc = ELINK_STATUS_OK; + uint32_t chip_id; if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_G) { - elink_set_mdio_clk(sc, phy->mdio_ctrl); + chip_id = (REG_RD(sc, MISC_REG_CHIP_NUM) << 16) | + ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12); + elink_set_mdio_clk(sc, chip_id, phy->mdio_ctrl); } if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0) @@ -2517,7 +3597,8 @@ static elink_status_t elink_cl45_write(struct bnx2x_softc *sc, /* Address */ tmp = ((phy->addr << 21) | (devad << 16) | reg | - EMAC_MDIO_COMM_COMMAND_ADDRESS | EMAC_MDIO_COMM_START_BUSY); + EMAC_MDIO_COMM_COMMAND_ADDRESS | + EMAC_MDIO_COMM_START_BUSY); REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); for (i = 0; i < 50; i++) { @@ -2530,8 +3611,9 @@ static elink_status_t elink_cl45_write(struct bnx2x_softc *sc, } } if (tmp & EMAC_MDIO_COMM_START_BUSY) { - PMD_DRV_LOG(DEBUG, "write phy register failed"); - elink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout" + ELINK_DEBUG_P0(sc, "write phy register failed"); + elink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); + /* "MDC/MDIO access timeout" */ rc = ELINK_STATUS_TIMEOUT; } else { @@ -2552,8 +3634,10 @@ static elink_status_t elink_cl45_write(struct bnx2x_softc *sc, } } if (tmp & EMAC_MDIO_COMM_START_BUSY) { - PMD_DRV_LOG(DEBUG, "write phy register failed"); - elink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout" + ELINK_DEBUG_P0(sc, "write phy register failed"); + elink_cb_event_log(sc, + ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); + /* "MDC/MDIO access timeout" */ rc = ELINK_STATUS_TIMEOUT; } @@ -2580,14 +3664,14 @@ static uint8_t elink_eee_has_cap(struct elink_params *params) struct bnx2x_softc *sc = params->sc; if (REG_RD(sc, params->shmem2_base) <= - offsetof(struct shmem2_region, eee_status[params->port])) - return 0; + offsetof(struct shmem2_region, eee_status[params->port])) + return 0; return 1; } static elink_status_t elink_eee_nvram_to_time(uint32_t nvram_mode, - uint32_t * idle_timer) + uint32_t *idle_timer) { switch (nvram_mode) { case PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED: @@ -2608,7 +3692,7 @@ static elink_status_t elink_eee_nvram_to_time(uint32_t nvram_mode, } static elink_status_t elink_eee_time_to_nvram(uint32_t idle_timer, - uint32_t * nvram_mode) + uint32_t *nvram_mode) { switch (idle_timer) { case ELINK_EEE_MODE_NVRAM_BALANCED_TIME: @@ -2635,7 +3719,7 @@ static uint32_t elink_eee_calc_timer(struct elink_params *params) if (params->eee_mode & ELINK_EEE_MODE_OVERRIDE_NVRAM) { if (params->eee_mode & ELINK_EEE_MODE_OUTPUT_TIME) { - /* time value in eee_mode --> used directly */ + /* time value in eee_mode --> used directly*/ eee_idle = params->eee_mode & ELINK_EEE_MODE_TIMER_MASK; } else { /* hsi value in eee_mode --> time */ @@ -2645,12 +3729,11 @@ static uint32_t elink_eee_calc_timer(struct elink_params *params) return 0; } } else { - /* hsi values in nvram --> time */ + /* hsi values in nvram --> time*/ eee_mode = ((REG_RD(sc, params->shmem_base + - offsetof(struct shmem_region, - dev_info.port_feature_config - [params-> - port].eee_power_mode)) & + offsetof(struct shmem_region, dev_info. + port_feature_config[params->port]. + eee_power_mode)) & PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >> PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT); @@ -2662,7 +3745,7 @@ static uint32_t elink_eee_calc_timer(struct elink_params *params) } static elink_status_t elink_eee_set_timers(struct elink_params *params, - struct elink_vars *vars) + struct elink_vars *vars) { uint32_t eee_idle = 0, eee_mode; struct bnx2x_softc *sc = params->sc; @@ -2675,7 +3758,7 @@ static elink_status_t elink_eee_set_timers(struct elink_params *params, } else if ((params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI) && (params->eee_mode & ELINK_EEE_MODE_OVERRIDE_NVRAM) && (params->eee_mode & ELINK_EEE_MODE_OUTPUT_TIME)) { - PMD_DRV_LOG(DEBUG, "Error: Tx LPI is enabled with timer 0"); + ELINK_DEBUG_P0(sc, "Error: Tx LPI is enabled with timer 0"); return ELINK_STATUS_ERROR; } @@ -2684,7 +3767,7 @@ static elink_status_t elink_eee_set_timers(struct elink_params *params, /* eee_idle in 1u --> eee_status in 16u */ eee_idle >>= 4; vars->eee_status |= (eee_idle & SHMEM_EEE_TIMER_MASK) | - SHMEM_EEE_TIME_OUTPUT_BIT; + SHMEM_EEE_TIME_OUTPUT_BIT; } else { if (elink_eee_time_to_nvram(eee_idle, &eee_mode)) return ELINK_STATUS_ERROR; @@ -2695,8 +3778,7 @@ static elink_status_t elink_eee_set_timers(struct elink_params *params, } static elink_status_t elink_eee_initial_config(struct elink_params *params, - struct elink_vars *vars, - uint8_t mode) + struct elink_vars *vars, uint8_t mode) { vars->eee_status |= ((uint32_t) mode) << SHMEM_EEE_SUPPORTED_SHIFT; @@ -2715,8 +3797,8 @@ static elink_status_t elink_eee_initial_config(struct elink_params *params, } static elink_status_t elink_eee_disable(struct elink_phy *phy, - struct elink_params *params, - struct elink_vars *vars) + struct elink_params *params, + struct elink_vars *vars) { struct bnx2x_softc *sc = params->sc; @@ -2731,9 +3813,8 @@ static elink_status_t elink_eee_disable(struct elink_phy *phy, } static elink_status_t elink_eee_advertise(struct elink_phy *phy, - struct elink_params *params, - struct elink_vars *vars, - uint8_t modes) + struct elink_params *params, + struct elink_vars *vars, uint8_t modes) { struct bnx2x_softc *sc = params->sc; uint16_t val = 0; @@ -2742,11 +3823,11 @@ static elink_status_t elink_eee_advertise(struct elink_phy *phy, REG_WR(sc, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20); if (modes & SHMEM_EEE_10G_ADV) { - PMD_DRV_LOG(DEBUG, "Advertise 10GBase-T EEE"); + ELINK_DEBUG_P0(sc, "Advertise 10GBase-T EEE"); val |= 0x8; } if (modes & SHMEM_EEE_1G_ADV) { - PMD_DRV_LOG(DEBUG, "Advertise 1GBase-T EEE"); + ELINK_DEBUG_P0(sc, "Advertise 1GBase-T EEE"); val |= 0x4; } @@ -2770,8 +3851,8 @@ static void elink_update_mng_eee(struct elink_params *params, } static void elink_eee_an_resolve(struct elink_phy *phy, - struct elink_params *params, - struct elink_vars *vars) + struct elink_params *params, + struct elink_vars *vars) { struct bnx2x_softc *sc = params->sc; uint16_t adv = 0, lp = 0; @@ -2786,7 +3867,7 @@ static void elink_eee_an_resolve(struct elink_phy *phy, if (adv & 0x2) { if (vars->line_speed == ELINK_SPEED_100) neg = 1; - PMD_DRV_LOG(DEBUG, "EEE negotiated - 100M"); + ELINK_DEBUG_P0(sc, "EEE negotiated - 100M"); } } if (lp & 0x14) { @@ -2794,7 +3875,7 @@ static void elink_eee_an_resolve(struct elink_phy *phy, if (adv & 0x14) { if (vars->line_speed == ELINK_SPEED_1000) neg = 1; - PMD_DRV_LOG(DEBUG, "EEE negotiated - 1G"); + ELINK_DEBUG_P0(sc, "EEE negotiated - 1G"); } } if (lp & 0x68) { @@ -2802,7 +3883,7 @@ static void elink_eee_an_resolve(struct elink_phy *phy, if (adv & 0x68) { if (vars->line_speed == ELINK_SPEED_10000) neg = 1; - PMD_DRV_LOG(DEBUG, "EEE negotiated - 10G"); + ELINK_DEBUG_P0(sc, "EEE negotiated - 10G"); } } @@ -2810,7 +3891,7 @@ static void elink_eee_an_resolve(struct elink_phy *phy, vars->eee_status |= (lp_adv << SHMEM_EEE_LP_ADV_STATUS_SHIFT); if (neg) { - PMD_DRV_LOG(DEBUG, "EEE is active"); + ELINK_DEBUG_P0(sc, "EEE is active"); vars->eee_status |= SHMEM_EEE_ACTIVE_BIT; } } @@ -2831,37 +3912,34 @@ static void elink_bsc_module_sel(struct elink_params *params) dev_info.shared_hw_config.board)); i2c_pins[I2C_BSC0] = board_cfg & SHARED_HW_CFG_E3_I2C_MUX0_MASK; i2c_pins[I2C_BSC1] = (board_cfg & SHARED_HW_CFG_E3_I2C_MUX1_MASK) >> - SHARED_HW_CFG_E3_I2C_MUX1_SHIFT; + SHARED_HW_CFG_E3_I2C_MUX1_SHIFT; /* Read I2C output value */ sfp_ctrl = REG_RD(sc, params->shmem_base + offsetof(struct shmem_region, - dev_info.port_hw_config[port]. - e3_cmn_pin_cfg)); + dev_info.port_hw_config[port].e3_cmn_pin_cfg)); i2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0; i2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0; - PMD_DRV_LOG(DEBUG, "Setting BSC switch"); + ELINK_DEBUG_P0(sc, "Setting BSC switch"); for (idx = 0; idx < I2C_SWITCH_WIDTH; idx++) elink_set_cfg_pin(sc, i2c_pins[idx], i2c_val[idx]); } -static elink_status_t elink_bsc_read(struct elink_params *params, - struct bnx2x_softc *sc, - uint8_t sl_devid, - uint16_t sl_addr, - uint8_t lc_addr, - uint8_t xfer_cnt, uint32_t * data_array) +static elink_status_t elink_bsc_read(struct bnx2x_softc *sc, + uint8_t sl_devid, + uint16_t sl_addr, + uint8_t lc_addr, + uint8_t xfer_cnt, + uint32_t *data_array) { uint32_t val, i; elink_status_t rc = ELINK_STATUS_OK; if (xfer_cnt > 16) { - PMD_DRV_LOG(DEBUG, "invalid xfer_cnt %d. Max is 16 bytes", - xfer_cnt); + ELINK_DEBUG_P1(sc, "invalid xfer_cnt %d. Max is 16 bytes", + xfer_cnt); return ELINK_STATUS_ERROR; } - if (params) - elink_bsc_module_sel(params); xfer_cnt = 16 - lc_addr; @@ -2874,11 +3952,11 @@ static elink_status_t elink_bsc_read(struct elink_params *params, val = (sl_devid << 16) | sl_addr; REG_WR(sc, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val); - /* Start xfer with 0 byte to update the address pointer ??? */ + /* Start xfer with 0 byte to update the address pointer ???*/ val = (MCPR_IMC_COMMAND_ENABLE) | - (MCPR_IMC_COMMAND_WRITE_OP << - MCPR_IMC_COMMAND_OPERATION_BITSHIFT) | - (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0); + (MCPR_IMC_COMMAND_WRITE_OP << + MCPR_IMC_COMMAND_OPERATION_BITSHIFT) | + (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0); REG_WR(sc, MCP_REG_MCPR_IMC_COMMAND, val); /* Poll for completion */ @@ -2888,8 +3966,8 @@ static elink_status_t elink_bsc_read(struct elink_params *params, DELAY(10); val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND); if (i++ > 1000) { - PMD_DRV_LOG(DEBUG, "wr 0 byte timed out after %d try", - i); + ELINK_DEBUG_P1(sc, "wr 0 byte timed out after %d try", + i); rc = ELINK_STATUS_TIMEOUT; break; } @@ -2899,10 +3977,10 @@ static elink_status_t elink_bsc_read(struct elink_params *params, /* Start xfer with read op */ val = (MCPR_IMC_COMMAND_ENABLE) | - (MCPR_IMC_COMMAND_READ_OP << - MCPR_IMC_COMMAND_OPERATION_BITSHIFT) | - (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | - (xfer_cnt); + (MCPR_IMC_COMMAND_READ_OP << + MCPR_IMC_COMMAND_OPERATION_BITSHIFT) | + (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | + (xfer_cnt); REG_WR(sc, MCP_REG_MCPR_IMC_COMMAND, val); /* Poll for completion */ @@ -2912,7 +3990,7 @@ static elink_status_t elink_bsc_read(struct elink_params *params, DELAY(10); val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND); if (i++ > 1000) { - PMD_DRV_LOG(DEBUG, "rd op timed out after %d try", i); + ELINK_DEBUG_P1(sc, "rd op timed out after %d try", i); rc = ELINK_STATUS_TIMEOUT; break; } @@ -2924,17 +4002,18 @@ static elink_status_t elink_bsc_read(struct elink_params *params, data_array[i] = REG_RD(sc, (MCP_REG_MCPR_IMC_DATAREG0 + i * 4)); #ifdef __BIG_ENDIAN data_array[i] = ((data_array[i] & 0x000000ff) << 24) | - ((data_array[i] & 0x0000ff00) << 8) | - ((data_array[i] & 0x00ff0000) >> 8) | - ((data_array[i] & 0xff000000) >> 24); + ((data_array[i] & 0x0000ff00) << 8) | + ((data_array[i] & 0x00ff0000) >> 8) | + ((data_array[i] & 0xff000000) >> 24); #endif } return rc; } static void elink_cl45_read_or_write(struct bnx2x_softc *sc, - struct elink_phy *phy, uint8_t devad, - uint16_t reg, uint16_t or_val) + struct elink_phy *phy, + uint8_t devad, uint16_t reg, + uint16_t or_val) { uint16_t val; elink_cl45_read(sc, phy, devad, reg, &val); @@ -2951,7 +4030,42 @@ static void elink_cl45_read_and_write(struct bnx2x_softc *sc, elink_cl45_write(sc, phy, devad, reg, val & and_val); } -static uint8_t elink_get_warpcore_lane(struct elink_params *params) +elink_status_t elink_phy_read(struct elink_params *params, uint8_t phy_addr, + uint8_t devad, uint16_t reg, uint16_t *ret_val) +{ + uint8_t phy_index; + /* Probe for the phy according to the given phy_addr, and execute + * the read request on it + */ + for (phy_index = 0; phy_index < params->num_phys; phy_index++) { + if (params->phy[phy_index].addr == phy_addr) { + return elink_cl45_read(params->sc, + ¶ms->phy[phy_index], devad, + reg, ret_val); + } + } + return ELINK_STATUS_ERROR; +} + +elink_status_t elink_phy_write(struct elink_params *params, uint8_t phy_addr, + uint8_t devad, uint16_t reg, uint16_t val) +{ + uint8_t phy_index; + /* Probe for the phy according to the given phy_addr, and execute + * the write request on it + */ + for (phy_index = 0; phy_index < params->num_phys; phy_index++) { + if (params->phy[phy_index].addr == phy_addr) { + return elink_cl45_write(params->sc, + ¶ms->phy[phy_index], devad, + reg, val); + } + } + return ELINK_STATUS_ERROR; +} + +static uint8_t elink_get_warpcore_lane(__rte_unused struct elink_phy *phy, + struct elink_params *params) { uint8_t lane = 0; struct bnx2x_softc *sc = params->sc; @@ -2985,14 +4099,16 @@ static uint8_t elink_get_warpcore_lane(struct elink_params *params) port = port ^ 1; lane = (port << 1) + path; - } else { /* Two port mode - no port swap */ + } else { /* Two port mode - no port swap */ /* Figure out path swap value */ - path_swap_ovr = REG_RD(sc, MISC_REG_TWO_PORT_PATH_SWAP_OVWR); + path_swap_ovr = + REG_RD(sc, MISC_REG_TWO_PORT_PATH_SWAP_OVWR); if (path_swap_ovr & 0x1) { path_swap = (path_swap_ovr & 0x2); } else { - path_swap = REG_RD(sc, MISC_REG_TWO_PORT_PATH_SWAP); + path_swap = + REG_RD(sc, MISC_REG_TWO_PORT_PATH_SWAP); } if (path_swap) path = path ^ 1; @@ -3002,6 +4118,7 @@ static uint8_t elink_get_warpcore_lane(struct elink_params *params) return lane; } + static void elink_set_aer_mmd(struct elink_params *params, struct elink_phy *phy) { @@ -3010,13 +4127,13 @@ static void elink_set_aer_mmd(struct elink_params *params, struct bnx2x_softc *sc = params->sc; ser_lane = ((params->lane_config & PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> - PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); + PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ? - (phy->addr + ser_lane) : 0; + (phy->addr + ser_lane) : 0; if (USES_WARPCORE(sc)) { - aer_val = elink_get_warpcore_lane(params); + aer_val = elink_get_warpcore_lane(phy, params); /* In Dual-lane mode, two lanes are joined together, * so in order to configure them, the AER broadcast method is * used here. @@ -3049,7 +4166,7 @@ static void elink_set_serdes_access(struct bnx2x_softc *sc, uint8_t port) DELAY(500); REG_WR(sc, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f); DELAY(500); - /* Set Clause 45 */ + /* Set Clause 45 */ REG_WR(sc, NIG_REG_SERDES0_CTRL_MD_ST + port * 0x10, 0); } @@ -3057,7 +4174,7 @@ static void elink_serdes_deassert(struct bnx2x_softc *sc, uint8_t port) { uint32_t val; - PMD_DRV_LOG(DEBUG, "elink_serdes_deassert"); + ELINK_DEBUG_P0(sc, "elink_serdes_deassert"); val = ELINK_SERDES_RESET_BITS << (port * 16); @@ -3092,7 +4209,7 @@ static void elink_xgxs_deassert(struct elink_params *params) struct bnx2x_softc *sc = params->sc; uint8_t port; uint32_t val; - PMD_DRV_LOG(DEBUG, "elink_xgxs_deassert"); + ELINK_DEBUG_P0(sc, "elink_xgxs_deassert"); port = params->port; val = ELINK_XGXS_RESET_BITS << (port * 16); @@ -3107,8 +4224,9 @@ static void elink_xgxs_deassert(struct elink_params *params) static void elink_calc_ieee_aneg_adv(struct elink_phy *phy, struct elink_params *params, - uint16_t * ieee_fc) + uint16_t *ieee_fc) { + struct bnx2x_softc *sc = params->sc; *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX; /* Resolve pause mode and advertisement Please refer to Table * 28B-3 of the 802.3ab-1999 spec @@ -3118,12 +4236,12 @@ static void elink_calc_ieee_aneg_adv(struct elink_phy *phy, case ELINK_FLOW_CTRL_AUTO: switch (params->req_fc_auto_adv) { case ELINK_FLOW_CTRL_BOTH: + case ELINK_FLOW_CTRL_RX: *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; break; - case ELINK_FLOW_CTRL_RX: case ELINK_FLOW_CTRL_TX: *ieee_fc |= - MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; + MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; break; default: break; @@ -3143,16 +4261,18 @@ static void elink_calc_ieee_aneg_adv(struct elink_phy *phy, *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE; break; } - PMD_DRV_LOG(DEBUG, "ieee_fc = 0x%x", *ieee_fc); + ELINK_DEBUG_P1(sc, "ieee_fc = 0x%x", *ieee_fc); } -static void set_phy_vars(struct elink_params *params, struct elink_vars *vars) +static void set_phy_vars(struct elink_params *params, + struct elink_vars *vars) { + struct bnx2x_softc *sc = params->sc; uint8_t actual_phy_idx, phy_index, link_cfg_idx; uint8_t phy_config_swapped = params->multi_phy_config & - PORT_HW_CFG_PHY_SWAPPED_ENABLED; + PORT_HW_CFG_PHY_SWAPPED_ENABLED; for (phy_index = ELINK_INT_PHY; phy_index < params->num_phys; - phy_index++) { + phy_index++) { link_cfg_idx = ELINK_LINK_CONFIG_IDX(phy_index); actual_phy_idx = phy_index; if (phy_config_swapped) { @@ -3162,26 +4282,26 @@ static void set_phy_vars(struct elink_params *params, struct elink_vars *vars) actual_phy_idx = ELINK_EXT_PHY1; } params->phy[actual_phy_idx].req_flow_ctrl = - params->req_flow_ctrl[link_cfg_idx]; + params->req_flow_ctrl[link_cfg_idx]; params->phy[actual_phy_idx].req_line_speed = - params->req_line_speed[link_cfg_idx]; + params->req_line_speed[link_cfg_idx]; params->phy[actual_phy_idx].speed_cap_mask = - params->speed_cap_mask[link_cfg_idx]; + params->speed_cap_mask[link_cfg_idx]; params->phy[actual_phy_idx].req_duplex = - params->req_duplex[link_cfg_idx]; + params->req_duplex[link_cfg_idx]; if (params->req_line_speed[link_cfg_idx] == ELINK_SPEED_AUTO_NEG) vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED; - PMD_DRV_LOG(DEBUG, "req_flow_ctrl %x, req_line_speed %x," - " speed_cap_mask %x", - params->phy[actual_phy_idx].req_flow_ctrl, - params->phy[actual_phy_idx].req_line_speed, - params->phy[actual_phy_idx].speed_cap_mask); + ELINK_DEBUG_P3(sc, "req_flow_ctrl %x, req_line_speed %x," + " speed_cap_mask %x", + params->phy[actual_phy_idx].req_flow_ctrl, + params->phy[actual_phy_idx].req_line_speed, + params->phy[actual_phy_idx].speed_cap_mask); } } @@ -3199,38 +4319,57 @@ static void elink_ext_phy_set_pause(struct elink_params *params, /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); if ((vars->ieee_fc & - MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) == + MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) == MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) { val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC; } if ((vars->ieee_fc & - MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) == + MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) == MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) { val |= MDIO_AN_REG_ADV_PAUSE_PAUSE; } - PMD_DRV_LOG(DEBUG, "Ext phy AN advertize 0x%x", val); + ELINK_DEBUG_P1(sc, "Ext phy AN advertize 0x%x", val); elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val); } -static void elink_pause_resolve(struct elink_vars *vars, uint32_t pause_result) -{ /* LD LP */ - switch (pause_result) { /* ASYM P ASYM P */ - case 0xb: /* 1 0 1 1 */ +static void elink_pause_resolve(__rte_unused struct elink_phy *phy, + struct elink_params *params, + struct elink_vars *vars, + uint32_t pause_result) +{ + struct bnx2x_softc *sc = params->sc; + /* LD LP */ + switch (pause_result) { /* ASYM P ASYM P */ + case 0xb: /* 1 0 1 1 */ + ELINK_DEBUG_P0(sc, "Flow Control: TX only"); vars->flow_ctrl = ELINK_FLOW_CTRL_TX; break; - case 0xe: /* 1 1 1 0 */ + case 0xe: /* 1 1 1 0 */ + ELINK_DEBUG_P0(sc, "Flow Control: RX only"); vars->flow_ctrl = ELINK_FLOW_CTRL_RX; break; - case 0x5: /* 0 1 0 1 */ - case 0x7: /* 0 1 1 1 */ - case 0xd: /* 1 1 0 1 */ - case 0xf: /* 1 1 1 1 */ + case 0x5: /* 0 1 0 1 */ + case 0x7: /* 0 1 1 1 */ + case 0xd: /* 1 1 0 1 */ + case 0xf: /* 1 1 1 1 */ + /* If the user selected to advertise RX ONLY, + * although we advertised both, need to enable + * RX only. + */ + + if (params->req_fc_auto_adv == ELINK_FLOW_CTRL_BOTH) { + ELINK_DEBUG_P0(sc, "Flow Control: RX & TX"); vars->flow_ctrl = ELINK_FLOW_CTRL_BOTH; + } else { + ELINK_DEBUG_P0(sc, "Flow Control: RX only"); + vars->flow_ctrl = ELINK_FLOW_CTRL_RX; + } break; - default: + ELINK_DEBUG_P0(sc, "Flow Control: None"); + vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; break; } if (pause_result & (1 << 0)) @@ -3244,22 +4383,23 @@ static void elink_ext_phy_update_adv_fc(struct elink_phy *phy, struct elink_params *params, struct elink_vars *vars) { - uint16_t ld_pause; /* local */ - uint16_t lp_pause; /* link partner */ + uint16_t ld_pause; /* local */ + uint16_t lp_pause; /* link partner */ uint16_t pause_result; struct bnx2x_softc *sc = params->sc; - if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE) { + if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X54618SE) { elink_cl22_read(sc, phy, 0x4, &ld_pause); elink_cl22_read(sc, phy, 0x5, &lp_pause); - } else if (CHIP_IS_E3(sc) && ELINK_SINGLE_MEDIA_DIRECT(params)) { - uint8_t lane = elink_get_warpcore_lane(params); + } else if (CHIP_IS_E3(sc) && + ELINK_SINGLE_MEDIA_DIRECT(params)) { + uint8_t lane = elink_get_warpcore_lane(phy, params); uint16_t gp_status, gp_mask; elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_4, &gp_status); gp_mask = (MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL | MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP) << - lane; + lane; if ((gp_status & gp_mask) == gp_mask) { elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &ld_pause); @@ -3285,16 +4425,18 @@ static void elink_ext_phy_update_adv_fc(struct elink_phy *phy, MDIO_AN_DEVAD, MDIO_AN_REG_LP_AUTO_NEG, &lp_pause); } - pause_result = (ld_pause & MDIO_AN_REG_ADV_PAUSE_MASK) >> 8; - pause_result |= (lp_pause & MDIO_AN_REG_ADV_PAUSE_MASK) >> 10; - PMD_DRV_LOG(DEBUG, "Ext PHY pause result 0x%x", pause_result); - elink_pause_resolve(vars, pause_result); + pause_result = (ld_pause & + MDIO_AN_REG_ADV_PAUSE_MASK) >> 8; + pause_result |= (lp_pause & + MDIO_AN_REG_ADV_PAUSE_MASK) >> 10; + ELINK_DEBUG_P1(sc, "Ext PHY pause result 0x%x", pause_result); + elink_pause_resolve(phy, params, vars, pause_result); } static uint8_t elink_ext_phy_resolve_fc(struct elink_phy *phy, - struct elink_params *params, - struct elink_vars *vars) + struct elink_params *params, + struct elink_vars *vars) { uint8_t ret = 0; vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; @@ -3312,7 +4454,6 @@ static uint8_t elink_ext_phy_resolve_fc(struct elink_phy *phy, } return ret; } - /******************************************************************/ /* Warpcore section */ /******************************************************************/ @@ -3321,19 +4462,31 @@ static uint8_t elink_ext_phy_resolve_fc(struct elink_phy *phy, * init configuration, and set/clear SGMII flag. Internal * phy init is done purely in phy_init stage. */ -#define WC_TX_DRIVER(post2, idriver, ipre) \ +#define WC_TX_DRIVER(post2, idriver, ipre, ifir) \ ((post2 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | \ (idriver << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | \ - (ipre << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)) + (ipre << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET) | \ + (ifir << MDIO_WC_REG_TX0_TX_DRIVER_IFIR_OFFSET)) #define WC_TX_FIR(post, main, pre) \ ((post << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) | \ (main << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) | \ (pre << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET)) +static void elink_update_link_attr(struct elink_params *params, + uint32_t link_attr) +{ + struct bnx2x_softc *sc = params->sc; + + if (SHMEM2_HAS(sc, link_attr_sync)) + REG_WR(sc, params->shmem2_base + + offsetof(struct shmem2_region, + link_attr_sync[params->port]), link_attr); +} + static void elink_warpcore_enable_AN_KR2(struct elink_phy *phy, struct elink_params *params, - struct elink_vars *vars) + __rte_unused struct elink_vars *vars) { struct bnx2x_softc *sc = params->sc; uint16_t i; @@ -3356,7 +4509,7 @@ static void elink_warpcore_enable_AN_KR2(struct elink_phy *phy, {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0157}, {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0620} }; - PMD_DRV_LOG(DEBUG, "Enabling 20G-KR2"); + ELINK_DEBUG_P0(sc, "Enabling 20G-KR2"); elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_CL49_USERB0_CTRL, (3 << 6)); @@ -3366,15 +4519,16 @@ static void elink_warpcore_enable_AN_KR2(struct elink_phy *phy, reg_set[i].val); /* Start KR2 work-around timer which handles BNX2X8073 link-parner */ - vars->link_attr_sync |= LINK_ATTR_SYNC_KR2_ENABLE; - elink_update_link_attr(params, vars->link_attr_sync); + params->link_attr_sync |= LINK_ATTR_SYNC_KR2_ENABLE; + elink_update_link_attr(params, params->link_attr_sync); } static void elink_disable_kr2(struct elink_params *params, - struct elink_vars *vars, struct elink_phy *phy) + struct elink_vars *vars, + struct elink_phy *phy) { struct bnx2x_softc *sc = params->sc; - uint32_t i; + int i; static struct elink_reg_set reg_set[] = { /* Step 1 - Program the TX/RX alignment markers */ {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0x7690}, @@ -3393,13 +4547,13 @@ static void elink_disable_kr2(struct elink_params *params, {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0002}, {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0000} }; - PMD_DRV_LOG(DEBUG, "Disabling 20G-KR2"); + ELINK_DEBUG_P0(sc, "Disabling 20G-KR2"); - for (i = 0; i < ARRAY_SIZE(reg_set); i++) + for (i = 0; i < (int)ARRAY_SIZE(reg_set); i++) elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg, reg_set[i].val); - vars->link_attr_sync &= ~LINK_ATTR_SYNC_KR2_ENABLE; - elink_update_link_attr(params, vars->link_attr_sync); + params->link_attr_sync &= ~LINK_ATTR_SYNC_KR2_ENABLE; + elink_update_link_attr(params, params->link_attr_sync); vars->check_kr2_recovery_cnt = ELINK_CHECK_KR2_RECOVERY_CNT; } @@ -3409,7 +4563,7 @@ static void elink_warpcore_set_lpi_passthrough(struct elink_phy *phy, { struct bnx2x_softc *sc = params->sc; - PMD_DRV_LOG(DEBUG, "Configure WC for LPI pass through"); + ELINK_DEBUG_P0(sc, "Configure WC for LPI pass through"); elink_cl45_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_EEE_COMBO_CONTROL0, 0x7c); elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, @@ -3421,7 +4575,7 @@ static void elink_warpcore_restart_AN_KR(struct elink_phy *phy, { /* Restart autoneg on the leading lane only */ struct bnx2x_softc *sc = params->sc; - uint16_t lane = elink_get_warpcore_lane(params); + uint16_t lane = elink_get_warpcore_lane(phy, params); CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK, MDIO_AER_BLOCK_AER_REG, lane); elink_cl45_write(sc, phy, MDIO_AN_DEVAD, @@ -3433,9 +4587,9 @@ static void elink_warpcore_restart_AN_KR(struct elink_phy *phy, static void elink_warpcore_enable_AN_KR(struct elink_phy *phy, struct elink_params *params, - struct elink_vars *vars) -{ - uint16_t lane, i, cl72_ctrl, an_adv = 0; + struct elink_vars *vars) { + uint16_t lane, i, cl72_ctrl, an_adv = 0, val; + uint32_t wc_lane_config; struct bnx2x_softc *sc = params->sc; static struct elink_reg_set reg_set[] = { {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7}, @@ -3447,7 +4601,7 @@ static void elink_warpcore_enable_AN_KR(struct elink_phy *phy, {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2}, {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0}, }; - PMD_DRV_LOG(DEBUG, "Enable Auto Negotiation for KR"); + ELINK_DEBUG_P0(sc, "Enable Auto Negotiation for KR"); /* Set to default registers that may be overridden by 10G force */ for (i = 0; i < ARRAY_SIZE(reg_set); i++) elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg, @@ -3469,11 +4623,11 @@ static void elink_warpcore_enable_AN_KR(struct elink_phy *phy, /* Enable CL37 1G Parallel Detect */ elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, addr, 0x1); - PMD_DRV_LOG(DEBUG, "Advertize 1G"); + ELINK_DEBUG_P0(sc, "Advertize 1G"); } if (((vars->line_speed == ELINK_SPEED_AUTO_NEG) && (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) || - (vars->line_speed == ELINK_SPEED_10000)) { + (vars->line_speed == ELINK_SPEED_10000)) { /* Check adding advertisement for 10G KR */ an_adv |= (1 << 7); /* Enable 10G Parallel Detect */ @@ -3483,23 +4637,25 @@ static void elink_warpcore_enable_AN_KR(struct elink_phy *phy, elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_WC_REG_PAR_DET_10G_CTRL, 1); elink_set_aer_mmd(params, phy); - PMD_DRV_LOG(DEBUG, "Advertize 10G"); + ELINK_DEBUG_P0(sc, "Advertize 10G"); } /* Set Transmit PMD settings */ - lane = elink_get_warpcore_lane(params); + lane = elink_get_warpcore_lane(phy, params); elink_cl45_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_TX0_TX_DRIVER + 0x10 * lane, - WC_TX_DRIVER(0x02, 0x06, 0x09)); + WC_TX_DRIVER(0x02, 0x06, 0x09, 0)); /* Configure the next lane if dual mode */ if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE) elink_cl45_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_TX0_TX_DRIVER + 0x10 * (lane + 1), - WC_TX_DRIVER(0x02, 0x06, 0x09)); + WC_TX_DRIVER(0x02, 0x06, 0x09, 0)); elink_cl45_write(sc, phy, MDIO_WC_DEVAD, - MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL, 0x03f0); + MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL, + 0x03f0); elink_cl45_write(sc, phy, MDIO_WC_DEVAD, - MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL, 0x03f0); + MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL, + 0x03f0); /* Advertised speeds */ elink_cl45_write(sc, phy, MDIO_AN_DEVAD, @@ -3513,14 +4669,13 @@ static void elink_warpcore_enable_AN_KR(struct elink_phy *phy, /* Enable CL37 BAM */ if (REG_RD(sc, params->shmem_base + - offsetof(struct shmem_region, - dev_info.port_hw_config[params->port]. - default_cfg)) & + offsetof(struct shmem_region, dev_info. + port_hw_config[params->port].default_cfg)) & PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) { elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL, 1); - PMD_DRV_LOG(DEBUG, "Enable CL37 BAM on KR"); + ELINK_DEBUG_P0(sc, "Enable CL37 BAM on KR"); } /* Advertise pause */ @@ -3531,7 +4686,7 @@ static void elink_warpcore_enable_AN_KR(struct elink_phy *phy, /* Over 1G - AN local device user page 1 */ elink_cl45_write(sc, phy, MDIO_WC_DEVAD, - MDIO_WC_REG_DIGITAL3_UP1, 0x1f); + MDIO_WC_REG_DIGITAL3_UP1, 0x1f); if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) && (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) || @@ -3542,7 +4697,8 @@ static void elink_warpcore_enable_AN_KR(struct elink_phy *phy, elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_RX1_PCI_CTRL + - (0x10 * lane), (1 << 11)); + (0x10 * lane), + (1 << 11)); elink_cl45_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_XGXS_X2_CONTROL3, 0x7); @@ -3550,6 +4706,31 @@ static void elink_warpcore_enable_AN_KR(struct elink_phy *phy, elink_warpcore_enable_AN_KR2(phy, params, vars); } else { + /* Enable Auto-Detect to support 1G over CL37 as well */ + elink_cl45_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0x10); + wc_lane_config = REG_RD(sc, params->shmem_base + + offsetof(struct shmem_region, dev_info. + shared_hw_config.wc_lane_config)); + elink_cl45_read(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_RX0_PCI_CTRL + (lane << 4), &val); + /* Force cl48 sync_status LOW to avoid getting stuck in CL73 + * parallel-detect loop when CL73 and CL37 are enabled. + */ + val |= 1 << 11; + + /* Restore Polarity settings in case it was run over by + * previous link owner + */ + if (wc_lane_config & + (SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED << lane)) + val |= 3 << 2; + else + val &= ~(3 << 2); + elink_cl45_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_RX0_PCI_CTRL + (lane << 4), + val); + elink_disable_kr2(params, vars, phy); } @@ -3558,7 +4739,8 @@ static void elink_warpcore_enable_AN_KR(struct elink_phy *phy, } static void elink_warpcore_set_10G_KR(struct elink_phy *phy, - struct elink_params *params) + struct elink_params *params, + __rte_unused struct elink_vars *vars) { struct bnx2x_softc *sc = params->sc; uint16_t val16, i, lane; @@ -3566,7 +4748,7 @@ static void elink_warpcore_set_10G_KR(struct elink_phy *phy, /* Disable Autoneg */ {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7}, {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, - 0x3f00}, + 0x3f00}, {MDIO_AN_DEVAD, MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0}, {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0}, {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL3_UP1, 0x1}, @@ -3579,7 +4761,7 @@ static void elink_warpcore_set_10G_KR(struct elink_phy *phy, elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg, reg_set[i].val); - lane = elink_get_warpcore_lane(params); + lane = elink_get_warpcore_lane(phy, params); /* Global registers */ CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK, MDIO_AER_BLOCK_AER_REG, 0); @@ -3609,7 +4791,8 @@ static void elink_warpcore_set_10G_KR(struct elink_phy *phy, MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30); /* Turn TX scramble payload only the 64/66 scrambler */ - elink_cl45_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_TX66_CONTROL, 0x9); + elink_cl45_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_TX66_CONTROL, 0x9); /* Turn RX scramble payload only the 64/66 scrambler */ elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, @@ -3630,7 +4813,7 @@ static void elink_warpcore_set_10G_XFI(struct elink_phy *phy, struct bnx2x_softc *sc = params->sc; uint16_t misc1_val, tap_val, tx_driver_val, lane, val; uint32_t cfg_tap_val, tx_drv_brdct, tx_equal; - + uint32_t ifir_val, ipost2_val, ipre_driver_val; /* Hold rxSeqStart */ elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x8000); @@ -3675,38 +4858,59 @@ static void elink_warpcore_set_10G_XFI(struct elink_phy *phy, if (is_xfi) { misc1_val |= 0x5; tap_val = WC_TX_FIR(0x08, 0x37, 0x00); - tx_driver_val = WC_TX_DRIVER(0x00, 0x02, 0x03); + tx_driver_val = WC_TX_DRIVER(0x00, 0x02, 0x03, 0); } else { cfg_tap_val = REG_RD(sc, params->shmem_base + - offsetof(struct shmem_region, - dev_info.port_hw_config[params-> - port].sfi_tap_values)); + offsetof(struct shmem_region, dev_info. + port_hw_config[params->port]. + sfi_tap_values)); tx_equal = cfg_tap_val & PORT_HW_CFG_TX_EQUALIZATION_MASK; - tx_drv_brdct = (cfg_tap_val & - PORT_HW_CFG_TX_DRV_BROADCAST_MASK) >> - PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT; - misc1_val |= 0x9; /* TAP values are controlled by nvram, if value there isn't 0 */ if (tx_equal) - tap_val = (uint16_t) tx_equal; + tap_val = (uint16_t)tx_equal; else tap_val = WC_TX_FIR(0x0f, 0x2b, 0x02); - if (tx_drv_brdct) - tx_driver_val = - WC_TX_DRIVER(0x03, (uint16_t) tx_drv_brdct, 0x06); - else - tx_driver_val = WC_TX_DRIVER(0x03, 0x02, 0x06); + ifir_val = DEFAULT_TX_DRV_IFIR; + ipost2_val = DEFAULT_TX_DRV_POST2; + ipre_driver_val = DEFAULT_TX_DRV_IPRE_DRIVER; + tx_drv_brdct = DEFAULT_TX_DRV_BRDCT; + + /* If any of the IFIR/IPRE_DRIVER/POST@ is set, apply all + * configuration. + */ + if (cfg_tap_val & (PORT_HW_CFG_TX_DRV_IFIR_MASK | + PORT_HW_CFG_TX_DRV_IPREDRIVER_MASK | + PORT_HW_CFG_TX_DRV_POST2_MASK)) { + ifir_val = (cfg_tap_val & + PORT_HW_CFG_TX_DRV_IFIR_MASK) >> + PORT_HW_CFG_TX_DRV_IFIR_SHIFT; + ipre_driver_val = (cfg_tap_val & + PORT_HW_CFG_TX_DRV_IPREDRIVER_MASK) + >> PORT_HW_CFG_TX_DRV_IPREDRIVER_SHIFT; + ipost2_val = (cfg_tap_val & + PORT_HW_CFG_TX_DRV_POST2_MASK) >> + PORT_HW_CFG_TX_DRV_POST2_SHIFT; + } + + if (cfg_tap_val & PORT_HW_CFG_TX_DRV_BROADCAST_MASK) { + tx_drv_brdct = (cfg_tap_val & + PORT_HW_CFG_TX_DRV_BROADCAST_MASK) >> + PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT; + } + + tx_driver_val = WC_TX_DRIVER(ipost2_val, tx_drv_brdct, + ipre_driver_val, ifir_val); } elink_cl45_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val); /* Set Transmit PMD settings */ - lane = elink_get_warpcore_lane(params); + lane = elink_get_warpcore_lane(phy, params); elink_cl45_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_TX_FIR_TAP, tap_val | MDIO_WC_REG_TX_FIR_TAP_ENABLE); @@ -3754,7 +4958,8 @@ static void elink_warpcore_set_20G_force_KR2(struct elink_phy *phy, elink_cl45_read_and_write(sc, phy, MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, ~(1 << 1)); - elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0); + elink_cl45_write(sc, phy, MDIO_AN_DEVAD, + MDIO_AN_REG_CTRL, 0); /* Turn off CL73 */ elink_cl45_read(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, &val); @@ -3790,7 +4995,8 @@ static void elink_warpcore_set_20G_force_KR2(struct elink_phy *phy, } static void elink_warpcore_set_20G_DXGXS(struct bnx2x_softc *sc, - struct elink_phy *phy, uint16_t lane) + struct elink_phy *phy, + uint16_t lane) { /* Rx0 anaRxControl1G */ elink_cl45_write(sc, phy, MDIO_WC_DEVAD, @@ -3800,13 +5006,17 @@ static void elink_warpcore_set_20G_DXGXS(struct bnx2x_softc *sc, elink_cl45_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_RX2_ANARXCONTROL1G, 0x90); - elink_cl45_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_RX66_SCW0, 0xE070); + elink_cl45_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_RX66_SCW0, 0xE070); - elink_cl45_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_RX66_SCW1, 0xC0D0); + elink_cl45_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_RX66_SCW1, 0xC0D0); - elink_cl45_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_RX66_SCW2, 0xA0B0); + elink_cl45_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_RX66_SCW2, 0xA0B0); - elink_cl45_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_RX66_SCW3, 0x8090); + elink_cl45_write(sc, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_RX66_SCW3, 0x8090); elink_cl45_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_RX66_SCW0_MASK, 0xF0F0); @@ -3835,7 +5045,7 @@ static void elink_warpcore_set_20G_DXGXS(struct bnx2x_softc *sc, MDIO_WC_REG_TX_FIR_TAP_ENABLE)); elink_cl45_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_TX0_TX_DRIVER + 0x10 * lane, - WC_TX_DRIVER(0x02, 0x02, 0x02)); + WC_TX_DRIVER(0x02, 0x02, 0x02, 0)); } static void elink_warpcore_set_sgmii_speed(struct elink_phy *phy, @@ -3857,7 +5067,7 @@ static void elink_warpcore_set_sgmii_speed(struct elink_phy *phy, elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x1000); - PMD_DRV_LOG(DEBUG, "set SGMII AUTONEG"); + ELINK_DEBUG_P0(sc, "set SGMII AUTONEG"); } else { elink_cl45_read(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16); @@ -3872,9 +5082,8 @@ static void elink_warpcore_set_sgmii_speed(struct elink_phy *phy, val16 |= 0x0040; break; default: - PMD_DRV_LOG(DEBUG, - "Speed not supported: 0x%x", - phy->req_line_speed); + ELINK_DEBUG_P1(sc, + "Speed not supported: 0x%x", phy->req_line_speed); return; } @@ -3882,13 +5091,13 @@ static void elink_warpcore_set_sgmii_speed(struct elink_phy *phy, val16 |= 0x0100; elink_cl45_write(sc, phy, MDIO_WC_DEVAD, - MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16); + MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16); - PMD_DRV_LOG(DEBUG, "set SGMII force speed %d", - phy->req_line_speed); + ELINK_DEBUG_P1(sc, "set SGMII force speed %d", + phy->req_line_speed); elink_cl45_read(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16); - PMD_DRV_LOG(DEBUG, " (readback) %x", val16); + ELINK_DEBUG_P1(sc, " (readback) %x", val16); } /* SGMII Slave mode and disable signal detect */ @@ -3900,28 +5109,31 @@ static void elink_warpcore_set_sgmii_speed(struct elink_phy *phy, digctrl_kx1 &= 0xff4a; elink_cl45_write(sc, phy, MDIO_WC_DEVAD, - MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, digctrl_kx1); + MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, + digctrl_kx1); /* Turn off parallel detect */ elink_cl45_read(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &digctrl_kx2); elink_cl45_write(sc, phy, MDIO_WC_DEVAD, - MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, - (digctrl_kx2 & ~(1 << 2))); + MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, + (digctrl_kx2 & ~(1 << 2))); /* Re-enable parallel detect */ elink_cl45_write(sc, phy, MDIO_WC_DEVAD, - MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, - (digctrl_kx2 | (1 << 2))); + MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, + (digctrl_kx2 | (1 << 2))); /* Enable autodet */ elink_cl45_write(sc, phy, MDIO_WC_DEVAD, - MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, - (digctrl_kx1 | 0x10)); + MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, + (digctrl_kx1 | 0x10)); } + static void elink_warpcore_reset_lane(struct bnx2x_softc *sc, - struct elink_phy *phy, uint8_t reset) + struct elink_phy *phy, + uint8_t reset) { uint16_t val; /* Take lane out of reset after configuration is finished */ @@ -3934,7 +5146,7 @@ static void elink_warpcore_reset_lane(struct bnx2x_softc *sc, elink_cl45_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL5_MISC6, val); elink_cl45_read(sc, phy, MDIO_WC_DEVAD, - MDIO_WC_REG_DIGITAL5_MISC6, &val); + MDIO_WC_REG_DIGITAL5_MISC6, &val); } /* Clear SFI/XFI link settings registers */ @@ -3950,11 +5162,11 @@ static void elink_warpcore_clear_regs(struct elink_phy *phy, {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL3, 0x0800}, {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL4_MISC3, 0x8008}, {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, - 0x0195}, + 0x0195}, {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, - 0x0007}, + 0x0007}, {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, - 0x0002}, + 0x0002}, {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000}, {MDIO_WC_DEVAD, MDIO_WC_REG_TX_FIR_TAP, 0x0000}, {MDIO_WC_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040}, @@ -3968,40 +5180,41 @@ static void elink_warpcore_clear_regs(struct elink_phy *phy, elink_cl45_write(sc, phy, wc_regs[i].devad, wc_regs[i].reg, wc_regs[i].val); - lane = elink_get_warpcore_lane(params); + lane = elink_get_warpcore_lane(phy, params); elink_cl45_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_TX0_TX_DRIVER + 0x10 * lane, 0x0990); } static elink_status_t elink_get_mod_abs_int_cfg(struct bnx2x_softc *sc, + __rte_unused uint32_t chip_id, uint32_t shmem_base, uint8_t port, - uint8_t * gpio_num, - uint8_t * gpio_port) + uint8_t *gpio_num, + uint8_t *gpio_port) { uint32_t cfg_pin; *gpio_num = 0; *gpio_port = 0; if (CHIP_IS_E3(sc)) { cfg_pin = (REG_RD(sc, shmem_base + - offsetof(struct shmem_region, - dev_info.port_hw_config[port]. - e3_sfp_ctrl)) & - PORT_HW_CFG_E3_MOD_ABS_MASK) >> - PORT_HW_CFG_E3_MOD_ABS_SHIFT; - - /* Should not happen. This function called upon interrupt - * triggered by GPIO ( since EPIO can only generate interrupts - * to MCP). + offsetof(struct shmem_region, + dev_info.port_hw_config[port].e3_sfp_ctrl)) & + PORT_HW_CFG_E3_MOD_ABS_MASK) >> + PORT_HW_CFG_E3_MOD_ABS_SHIFT; + + /* + * This should not happen since this function is called + * from interrupt triggered by GPIO (since EPIO can only + * generate interrupts to MCP). * So if this function was called and none of the GPIOs was set, - * it means the shit hit the fan. + * it means something disastrous has already happened. */ if ((cfg_pin < PIN_CFG_GPIO0_P0) || (cfg_pin > PIN_CFG_GPIO3_P1)) { - PMD_DRV_LOG(DEBUG, - "No cfg pin %x for module detect indication", - cfg_pin); + ELINK_DEBUG_P1(sc, + "No cfg pin %x for module detect indication", + cfg_pin); return ELINK_STATUS_ERROR; } @@ -4015,12 +5228,13 @@ static elink_status_t elink_get_mod_abs_int_cfg(struct bnx2x_softc *sc, return ELINK_STATUS_OK; } -static int elink_is_sfp_module_plugged(struct elink_params *params) +static int elink_is_sfp_module_plugged(__rte_unused struct elink_phy *phy, + struct elink_params *params) { struct bnx2x_softc *sc = params->sc; uint8_t gpio_num, gpio_port; uint32_t gpio_val; - if (elink_get_mod_abs_int_cfg(sc, + if (elink_get_mod_abs_int_cfg(sc, params->chip_id, params->shmem_base, params->port, &gpio_num, &gpio_port) != ELINK_STATUS_OK) return 0; @@ -4032,17 +5246,16 @@ static int elink_is_sfp_module_plugged(struct elink_params *params) else return 0; } - static int elink_warpcore_get_sigdet(struct elink_phy *phy, struct elink_params *params) { uint16_t gp2_status_reg0, lane; struct bnx2x_softc *sc = params->sc; - lane = elink_get_warpcore_lane(params); + lane = elink_get_warpcore_lane(phy, params); elink_cl45_read(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0, - &gp2_status_reg0); + &gp2_status_reg0); return (gp2_status_reg0 >> (8 + lane)) & 0x1; } @@ -4061,38 +5274,35 @@ static void elink_warpcore_config_runtime(struct elink_phy *phy, return; if (vars->rx_tx_asic_rst) { - uint16_t lane = elink_get_warpcore_lane(params); + uint16_t lane = elink_get_warpcore_lane(phy, params); serdes_net_if = (REG_RD(sc, params->shmem_base + - offsetof(struct shmem_region, - dev_info.port_hw_config - [params->port]. - default_cfg)) & - PORT_HW_CFG_NET_SERDES_IF_MASK); + offsetof(struct shmem_region, dev_info. + port_hw_config[params->port].default_cfg)) & + PORT_HW_CFG_NET_SERDES_IF_MASK); switch (serdes_net_if) { case PORT_HW_CFG_NET_SERDES_IF_KR: /* Do we get link yet? */ elink_cl45_read(sc, phy, MDIO_WC_DEVAD, 0x81d1, &gp_status1); - lnkup = (gp_status1 >> (8 + lane)) & 0x1; /* 1G */ - /*10G KR */ + lnkup = (gp_status1 >> (8 + lane)) & 0x1;/* 1G */ + /*10G KR*/ lnkup_kr = (gp_status1 >> (12 + lane)) & 0x1; if (lnkup_kr || lnkup) { vars->rx_tx_asic_rst = 0; } else { - /* Reset the lane to see if link comes up. */ + /* Reset the lane to see if link comes up.*/ elink_warpcore_reset_lane(sc, phy, 1); elink_warpcore_reset_lane(sc, phy, 0); /* Restart Autoneg */ elink_cl45_write(sc, phy, MDIO_AN_DEVAD, - MDIO_WC_REG_IEEE0BLK_MIICNTL, - 0x1200); + MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200); vars->rx_tx_asic_rst--; - PMD_DRV_LOG(DEBUG, "0x%x retry left", - vars->rx_tx_asic_rst); + ELINK_DEBUG_P1(sc, "0x%x retry left", + vars->rx_tx_asic_rst); } break; @@ -4100,29 +5310,29 @@ static void elink_warpcore_config_runtime(struct elink_phy *phy, break; } - } - /*params->rx_tx_asic_rst */ + } /*params->rx_tx_asic_rst*/ } static void elink_warpcore_config_sfi(struct elink_phy *phy, struct elink_params *params) { - uint16_t lane = elink_get_warpcore_lane(params); - + uint16_t lane = elink_get_warpcore_lane(phy, params); + struct bnx2x_softc *sc = params->sc; elink_warpcore_clear_regs(phy, params, lane); if ((params->req_line_speed[ELINK_LINK_CONFIG_IDX(ELINK_INT_PHY)] == ELINK_SPEED_10000) && (phy->media_type != ELINK_ETH_PHY_SFP_1G_FIBER)) { - PMD_DRV_LOG(DEBUG, "Setting 10G SFI"); + ELINK_DEBUG_P0(sc, "Setting 10G SFI"); elink_warpcore_set_10G_XFI(phy, params, 0); } else { - PMD_DRV_LOG(DEBUG, "Setting 1G Fiber"); + ELINK_DEBUG_P0(sc, "Setting 1G Fiber"); elink_warpcore_set_sgmii_speed(phy, params, 1, 0); } } static void elink_sfp_e3_set_transmitter(struct elink_params *params, - struct elink_phy *phy, uint8_t tx_en) + struct elink_phy *phy, + uint8_t tx_en) { struct bnx2x_softc *sc = params->sc; uint32_t cfg_pin; @@ -4131,9 +5341,9 @@ static void elink_sfp_e3_set_transmitter(struct elink_params *params, cfg_pin = REG_RD(sc, params->shmem_base + offsetof(struct shmem_region, dev_info.port_hw_config[port].e3_sfp_ctrl)) & - PORT_HW_CFG_E3_TX_LASER_MASK; + PORT_HW_CFG_E3_TX_LASER_MASK; /* Set the !tx_en since this pin is DISABLE_TX_LASER */ - PMD_DRV_LOG(DEBUG, "Setting WC TX to %d", tx_en); + ELINK_DEBUG_P1(sc, "Setting WC TX to %d", tx_en); /* For 20G, the expected pin to be used is 3 pins after the current */ elink_set_cfg_pin(sc, cfg_pin, tx_en ^ 1); @@ -4142,21 +5352,20 @@ static void elink_sfp_e3_set_transmitter(struct elink_params *params, } static uint8_t elink_warpcore_config_init(struct elink_phy *phy, - struct elink_params *params, - struct elink_vars *vars) + struct elink_params *params, + struct elink_vars *vars) { struct bnx2x_softc *sc = params->sc; uint32_t serdes_net_if; uint8_t fiber_mode; - uint16_t lane = elink_get_warpcore_lane(params); + uint16_t lane = elink_get_warpcore_lane(phy, params); serdes_net_if = (REG_RD(sc, params->shmem_base + - offsetof(struct shmem_region, - dev_info.port_hw_config[params->port]. - default_cfg)) & + offsetof(struct shmem_region, dev_info. + port_hw_config[params->port].default_cfg)) & PORT_HW_CFG_NET_SERDES_IF_MASK); - PMD_DRV_LOG(DEBUG, - "Begin Warpcore init, link_speed %d, " - "serdes_net_if = 0x%x", vars->line_speed, serdes_net_if); + ELINK_DEBUG_P2(sc, "Begin Warpcore init, link_speed %d, " + "serdes_net_if = 0x%x", + vars->line_speed, serdes_net_if); elink_set_aer_mmd(params, phy); elink_warpcore_reset_lane(sc, phy, 1); vars->phy_flags |= PHY_XGXS_FLAG; @@ -4165,7 +5374,7 @@ static uint8_t elink_warpcore_config_init(struct elink_phy *phy, ((phy->req_line_speed == ELINK_SPEED_100) || (phy->req_line_speed == ELINK_SPEED_10)))) { vars->phy_flags |= PHY_SGMII_FLAG; - PMD_DRV_LOG(DEBUG, "Setting SGMII mode"); + ELINK_DEBUG_P0(sc, "Setting SGMII mode"); elink_warpcore_clear_regs(phy, params, lane); elink_warpcore_set_sgmii_speed(phy, params, 0, 1); } else { @@ -4175,27 +5384,28 @@ static uint8_t elink_warpcore_config_init(struct elink_phy *phy, if (params->loopback_mode != ELINK_LOOPBACK_EXT) elink_warpcore_enable_AN_KR(phy, params, vars); else { - PMD_DRV_LOG(DEBUG, "Setting KR 10G-Force"); - elink_warpcore_set_10G_KR(phy, params); + ELINK_DEBUG_P0(sc, "Setting KR 10G-Force"); + elink_warpcore_set_10G_KR(phy, params, vars); } break; case PORT_HW_CFG_NET_SERDES_IF_XFI: elink_warpcore_clear_regs(phy, params, lane); if (vars->line_speed == ELINK_SPEED_10000) { - PMD_DRV_LOG(DEBUG, "Setting 10G XFI"); + ELINK_DEBUG_P0(sc, "Setting 10G XFI"); elink_warpcore_set_10G_XFI(phy, params, 1); } else { if (ELINK_SINGLE_MEDIA_DIRECT(params)) { - PMD_DRV_LOG(DEBUG, "1G Fiber"); + ELINK_DEBUG_P0(sc, "1G Fiber"); fiber_mode = 1; } else { - PMD_DRV_LOG(DEBUG, "10/100/1G SGMII"); + ELINK_DEBUG_P0(sc, "10/100/1G SGMII"); fiber_mode = 0; } elink_warpcore_set_sgmii_speed(phy, - params, - fiber_mode, 0); + params, + fiber_mode, + 0); } break; @@ -4207,7 +5417,7 @@ static uint8_t elink_warpcore_config_init(struct elink_phy *phy, */ if ((params->loopback_mode == ELINK_LOOPBACK_NONE) || (params->loopback_mode == ELINK_LOOPBACK_EXT)) { - if (elink_is_sfp_module_plugged(params)) + if (elink_is_sfp_module_plugged(phy, params)) elink_sfp_module_detection(phy, params); else elink_sfp_e3_set_transmitter(params, @@ -4219,10 +5429,10 @@ static uint8_t elink_warpcore_config_init(struct elink_phy *phy, case PORT_HW_CFG_NET_SERDES_IF_DXGXS: if (vars->line_speed != ELINK_SPEED_20000) { - PMD_DRV_LOG(DEBUG, "Speed not supported yet"); + ELINK_DEBUG_P0(sc, "Speed not supported yet"); return 0; } - PMD_DRV_LOG(DEBUG, "Setting 20G DXGXS"); + ELINK_DEBUG_P0(sc, "Setting 20G DXGXS"); elink_warpcore_set_20G_DXGXS(sc, phy, lane); /* Issue Module detection */ @@ -4232,21 +5442,21 @@ static uint8_t elink_warpcore_config_init(struct elink_phy *phy, if (!params->loopback_mode) { elink_warpcore_enable_AN_KR(phy, params, vars); } else { - PMD_DRV_LOG(DEBUG, "Setting KR 20G-Force"); + ELINK_DEBUG_P0(sc, "Setting KR 20G-Force"); elink_warpcore_set_20G_force_KR2(phy, params); } break; default: - PMD_DRV_LOG(DEBUG, - "Unsupported Serdes Net Interface 0x%x", - serdes_net_if); + ELINK_DEBUG_P1(sc, + "Unsupported Serdes Net Interface 0x%x", + serdes_net_if); return 0; } } /* Take lane out of reset after configuration is finished */ elink_warpcore_reset_lane(sc, phy, 0); - PMD_DRV_LOG(DEBUG, "Exit config init"); + ELINK_DEBUG_P0(sc, "Exit config init"); return 0; } @@ -4275,11 +5485,12 @@ static void elink_warpcore_link_reset(struct elink_phy *phy, MDIO_AER_BLOCK_AER_REG, 0); /* Enable 1G MDIO (1-copy) */ elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD, - MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, ~0x10); + MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, + ~0x10); elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_XGXSBLK1_LANECTRL2, 0xff00); - lane = elink_get_warpcore_lane(params); + lane = elink_get_warpcore_lane(phy, params); /* Disable CL36 PCS Tx */ elink_cl45_read(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16); @@ -4311,8 +5522,8 @@ static void elink_set_warpcore_loopback(struct elink_phy *phy, struct bnx2x_softc *sc = params->sc; uint16_t val16; uint32_t lane; - PMD_DRV_LOG(DEBUG, "Setting Warpcore loopback type %x, speed %d", - params->loopback_mode, phy->req_line_speed); + ELINK_DEBUG_P2(sc, "Setting Warpcore loopback type %x, speed %d", + params->loopback_mode, phy->req_line_speed); if (phy->req_line_speed < ELINK_SPEED_10000 || phy->supported & ELINK_SUPPORTED_20000baseKR2_Full) { @@ -4326,14 +5537,15 @@ static void elink_set_warpcore_loopback(struct elink_phy *phy, MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, 0x10); /* Set 1G loopback based on lane (1-copy) */ - lane = elink_get_warpcore_lane(params); + lane = elink_get_warpcore_lane(phy, params); elink_cl45_read(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16); val16 |= (1 << lane); if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE) val16 |= (2 << lane); elink_cl45_write(sc, phy, MDIO_WC_DEVAD, - MDIO_WC_REG_XGXSBLK1_LANECTRL2, val16); + MDIO_WC_REG_XGXSBLK1_LANECTRL2, + val16); /* Switch back to 4-copy registers */ elink_set_aer_mmd(params, phy); @@ -4347,8 +5559,10 @@ static void elink_set_warpcore_loopback(struct elink_phy *phy, } } + + static void elink_sync_link(struct elink_params *params, - struct elink_vars *vars) + struct elink_vars *vars) { struct bnx2x_softc *sc = params->sc; uint8_t link_10g_plus; @@ -4356,21 +5570,23 @@ static void elink_sync_link(struct elink_params *params, vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG; vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP); if (vars->link_up) { - PMD_DRV_LOG(DEBUG, "phy link up"); + ELINK_DEBUG_P0(sc, "phy link up"); + ELINK_DEBUG_P1(sc, "link status = %x", vars->link_status); vars->phy_link_up = 1; vars->duplex = DUPLEX_FULL; - switch (vars->link_status & LINK_STATUS_SPEED_AND_DUPLEX_MASK) { + switch (vars->link_status & + LINK_STATUS_SPEED_AND_DUPLEX_MASK) { case ELINK_LINK_10THD: vars->duplex = DUPLEX_HALF; - /* Fall through */ + /* Fall thru */ case ELINK_LINK_10TFD: vars->line_speed = ELINK_SPEED_10; break; case ELINK_LINK_100TXHD: vars->duplex = DUPLEX_HALF; - /* Fall through */ + /* Fall thru */ case ELINK_LINK_100T4: case ELINK_LINK_100TXFD: vars->line_speed = ELINK_SPEED_100; @@ -4378,14 +5594,14 @@ static void elink_sync_link(struct elink_params *params, case ELINK_LINK_1000THD: vars->duplex = DUPLEX_HALF; - /* Fall through */ + /* Fall thru */ case ELINK_LINK_1000TFD: vars->line_speed = ELINK_SPEED_1000; break; case ELINK_LINK_2500THD: vars->duplex = DUPLEX_HALF; - /* Fall through */ + /* Fall thru */ case ELINK_LINK_2500TFD: vars->line_speed = ELINK_SPEED_2500; break; @@ -4417,7 +5633,8 @@ static void elink_sync_link(struct elink_params *params, vars->phy_flags &= ~PHY_SGMII_FLAG; } if (vars->line_speed && - USES_WARPCORE(sc) && (vars->line_speed == ELINK_SPEED_1000)) + USES_WARPCORE(sc) && + (vars->line_speed == ELINK_SPEED_1000)) vars->phy_flags |= PHY_SGMII_FLAG; /* Anything 10 and over uses the bmac */ link_10g_plus = (vars->line_speed >= ELINK_SPEED_10000); @@ -4433,8 +5650,8 @@ static void elink_sync_link(struct elink_params *params, else vars->mac_type = ELINK_MAC_TYPE_EMAC; } - } else { /* Link down */ - PMD_DRV_LOG(DEBUG, "phy link down"); + } else { /* Link down */ + ELINK_DEBUG_P0(sc, "phy link down"); vars->phy_link_up = 0; @@ -4478,44 +5695,44 @@ void elink_link_status_update(struct elink_params *params, elink_sync_link(params, vars); /* Sync media type */ sync_offset = params->shmem_base + - offsetof(struct shmem_region, - dev_info.port_hw_config[port].media_type); + offsetof(struct shmem_region, + dev_info.port_hw_config[port].media_type); media_types = REG_RD(sc, sync_offset); params->phy[ELINK_INT_PHY].media_type = - (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >> - PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT; + (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >> + PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT; params->phy[ELINK_EXT_PHY1].media_type = - (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >> - PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT; + (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >> + PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT; params->phy[ELINK_EXT_PHY2].media_type = - (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >> - PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT; - PMD_DRV_LOG(DEBUG, "media_types = 0x%x", media_types); + (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >> + PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT; + ELINK_DEBUG_P1(sc, "media_types = 0x%x", media_types); /* Sync AEU offset */ sync_offset = params->shmem_base + - offsetof(struct shmem_region, - dev_info.port_hw_config[port].aeu_int_mask); + offsetof(struct shmem_region, + dev_info.port_hw_config[port].aeu_int_mask); vars->aeu_int_mask = REG_RD(sc, sync_offset); /* Sync PFC status */ if (vars->link_status & LINK_STATUS_PFC_ENABLED) params->feature_config_flags |= - ELINK_FEATURE_CONFIG_PFC_ENABLED; + ELINK_FEATURE_CONFIG_PFC_ENABLED; else params->feature_config_flags &= - ~ELINK_FEATURE_CONFIG_PFC_ENABLED; + ~ELINK_FEATURE_CONFIG_PFC_ENABLED; if (SHMEM2_HAS(sc, link_attr_sync)) - vars->link_attr_sync = SHMEM2_RD(sc, + params->link_attr_sync = SHMEM2_RD(sc, link_attr_sync[params->port]); - PMD_DRV_LOG(DEBUG, "link_status 0x%x phy_link_up %x int_mask 0x%x", - vars->link_status, vars->phy_link_up, vars->aeu_int_mask); - PMD_DRV_LOG(DEBUG, "line_speed %x duplex %x flow_ctrl 0x%x", - vars->line_speed, vars->duplex, vars->flow_ctrl); + ELINK_DEBUG_P3(sc, "link_status 0x%x phy_link_up %x int_mask 0x%x", + vars->link_status, vars->phy_link_up, vars->aeu_int_mask); + ELINK_DEBUG_P3(sc, "line_speed %x duplex %x flow_ctrl 0x%x", + vars->line_speed, vars->duplex, vars->flow_ctrl); } static void elink_set_master_ln(struct elink_params *params, @@ -4530,7 +5747,8 @@ static void elink_set_master_ln(struct elink_params *params, /* Set the master_ln for AN */ CL22_RD_OVER_CL45(sc, phy, MDIO_REG_BANK_XGXS_BLOCK2, - MDIO_XGXS_BLOCK2_TEST_MODE_LANE, &new_master_ln); + MDIO_XGXS_BLOCK2_TEST_MODE_LANE, + &new_master_ln); CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_XGXS_BLOCK2, @@ -4539,8 +5757,8 @@ static void elink_set_master_ln(struct elink_params *params, } static elink_status_t elink_reset_unicore(struct elink_params *params, - struct elink_phy *phy, - uint8_t set_serdes) + struct elink_phy *phy, + uint8_t set_serdes) { struct bnx2x_softc *sc = params->sc; uint16_t mii_control; @@ -4553,7 +5771,8 @@ static elink_status_t elink_reset_unicore(struct elink_params *params, CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_COMBO_IEEE0, MDIO_COMBO_IEEE0_MII_CONTROL, - (mii_control | MDIO_COMBO_IEEO_MII_CONTROL_RESET)); + (mii_control | + MDIO_COMBO_IEEO_MII_CONTROL_RESET)); if (set_serdes) elink_set_serdes_access(sc, params->port); @@ -4564,7 +5783,8 @@ static elink_status_t elink_reset_unicore(struct elink_params *params, /* The reset erased the previous bank value */ CL22_RD_OVER_CL45(sc, phy, MDIO_REG_BANK_COMBO_IEEE0, - MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control); + MDIO_COMBO_IEEE0_MII_CONTROL, + &mii_control); if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) { DELAY(5); @@ -4572,10 +5792,12 @@ static elink_status_t elink_reset_unicore(struct elink_params *params, } } - elink_cb_event_log(sc, ELINK_LOG_ID_PHY_UNINITIALIZED, params->port); // "Warning: PHY was not initialized," - // " Port %d", + elink_cb_event_log(sc, ELINK_LOG_ID_PHY_UNINITIALIZED, params->port); + /* "Warning: PHY was not initialized," + * " Port %d", + */ - PMD_DRV_LOG(DEBUG, "BUG! XGXS is still in reset!"); + ELINK_DEBUG_P0(sc, "BUG! XGXS is still in reset!"); return ELINK_STATUS_ERROR; } @@ -4629,31 +5851,35 @@ static void elink_set_parallel_detection(struct elink_phy *phy, uint16_t control2; CL22_RD_OVER_CL45(sc, phy, MDIO_REG_BANK_SERDES_DIGITAL, - MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, &control2); + MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, + &control2); if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN; else control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN; - PMD_DRV_LOG(DEBUG, "phy->speed_cap_mask = 0x%x, control2 = 0x%x", - phy->speed_cap_mask, control2); + ELINK_DEBUG_P2(sc, "phy->speed_cap_mask = 0x%x, control2 = 0x%x", + phy->speed_cap_mask, control2); CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_SERDES_DIGITAL, - MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, control2); + MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, + control2); if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) && - (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { - PMD_DRV_LOG(DEBUG, "XGXS"); + (phy->speed_cap_mask & + PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { + ELINK_DEBUG_P0(sc, "XGXS"); CL22_WR_OVER_CL45(sc, phy, - MDIO_REG_BANK_10G_PARALLEL_DETECT, - MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK, - MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT); + MDIO_REG_BANK_10G_PARALLEL_DETECT, + MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK, + MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT); CL22_RD_OVER_CL45(sc, phy, MDIO_REG_BANK_10G_PARALLEL_DETECT, MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL, &control2); + control2 |= MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN; @@ -4673,7 +5899,8 @@ static void elink_set_parallel_detection(struct elink_phy *phy, static void elink_set_autoneg(struct elink_phy *phy, struct elink_params *params, - struct elink_vars *vars, uint8_t enable_cl73) + struct elink_vars *vars, + uint8_t enable_cl73) { struct bnx2x_softc *sc = params->sc; uint16_t reg_val; @@ -4686,7 +5913,7 @@ static void elink_set_autoneg(struct elink_phy *phy, /* CL37 Autoneg Enabled */ if (vars->line_speed == ELINK_SPEED_AUTO_NEG) reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN; - else /* CL37 Autoneg Disabled */ + else /* CL37 Autoneg Disabled */ reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN); @@ -4700,7 +5927,7 @@ static void elink_set_autoneg(struct elink_phy *phy, MDIO_REG_BANK_SERDES_DIGITAL, MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, ®_val); reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN | - MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT); + MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT); reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE; if (vars->line_speed == ELINK_SPEED_AUTO_NEG) reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET; @@ -4714,7 +5941,8 @@ static void elink_set_autoneg(struct elink_phy *phy, /* Enable TetonII and BAM autoneg */ CL22_RD_OVER_CL45(sc, phy, MDIO_REG_BANK_BAM_NEXT_PAGE, - MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL, ®_val); + MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL, + ®_val); if (vars->line_speed == ELINK_SPEED_AUTO_NEG) { /* Enable BAM aneg Mode and TetonII aneg Mode */ reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE | @@ -4726,40 +5954,45 @@ static void elink_set_autoneg(struct elink_phy *phy, } CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_BAM_NEXT_PAGE, - MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL, reg_val); + MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL, + reg_val); if (enable_cl73) { /* Enable Cl73 FSM status bits */ CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_CL73_USERB0, - MDIO_CL73_USERB0_CL73_UCTRL, 0xe); + MDIO_CL73_USERB0_CL73_UCTRL, + 0xe); - /* Enable BAM Station Manager */ + /* Enable BAM Station Manager*/ CL22_WR_OVER_CL45(sc, phy, - MDIO_REG_BANK_CL73_USERB0, - MDIO_CL73_USERB0_CL73_BAM_CTRL1, - MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN | - MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN - | - MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN); + MDIO_REG_BANK_CL73_USERB0, + MDIO_CL73_USERB0_CL73_BAM_CTRL1, + MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN | + MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN | + MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN); /* Advertise CL73 link speeds */ CL22_RD_OVER_CL45(sc, phy, MDIO_REG_BANK_CL73_IEEEB1, - MDIO_CL73_IEEEB1_AN_ADV2, ®_val); - if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) + MDIO_CL73_IEEEB1_AN_ADV2, + ®_val); + if (phy->speed_cap_mask & + PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4; - if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) + if (phy->speed_cap_mask & + PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX; CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_CL73_IEEEB1, - MDIO_CL73_IEEEB1_AN_ADV2, reg_val); + MDIO_CL73_IEEEB1_AN_ADV2, + reg_val); /* CL73 Autoneg Enabled */ reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN; - } else /* CL73 Autoneg Disabled */ + } else /* CL73 Autoneg Disabled */ reg_val = 0; CL22_WR_OVER_CL45(sc, phy, @@ -4775,7 +6008,7 @@ static void elink_program_serdes(struct elink_phy *phy, struct bnx2x_softc *sc = params->sc; uint16_t reg_val; - /* Program duplex, disable autoneg and sgmii */ + /* Program duplex, disable autoneg and sgmii*/ CL22_RD_OVER_CL45(sc, phy, MDIO_REG_BANK_COMBO_IEEE0, MDIO_COMBO_IEEE0_MII_CONTROL, ®_val); @@ -4795,7 +6028,7 @@ static void elink_program_serdes(struct elink_phy *phy, MDIO_REG_BANK_SERDES_DIGITAL, MDIO_SERDES_DIGITAL_MISC1, ®_val); /* Clearing the speed value before setting the right speed */ - PMD_DRV_LOG(DEBUG, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x", reg_val); + ELINK_DEBUG_P1(sc, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x", reg_val); reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK | MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL); @@ -4808,7 +6041,7 @@ static void elink_program_serdes(struct elink_phy *phy, MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL); if (vars->line_speed == ELINK_SPEED_10000) reg_val |= - MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4; + MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4; } CL22_WR_OVER_CL45(sc, phy, @@ -4829,10 +6062,12 @@ static void elink_set_brcm_cl37_advertisement(struct elink_phy *phy, if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) val |= MDIO_OVER_1G_UP1_10G; CL22_WR_OVER_CL45(sc, phy, - MDIO_REG_BANK_OVER_1G, MDIO_OVER_1G_UP1, val); + MDIO_REG_BANK_OVER_1G, + MDIO_OVER_1G_UP1, val); CL22_WR_OVER_CL45(sc, phy, - MDIO_REG_BANK_OVER_1G, MDIO_OVER_1G_UP3, 0x400); + MDIO_REG_BANK_OVER_1G, + MDIO_OVER_1G_UP3, 0x400); } static void elink_set_ieee_aneg_advertisement(struct elink_phy *phy, @@ -4863,7 +6098,7 @@ static void elink_restart_autoneg(struct elink_phy *phy, struct bnx2x_softc *sc = params->sc; uint16_t mii_control; - PMD_DRV_LOG(DEBUG, "elink_restart_autoneg"); + ELINK_DEBUG_P0(sc, "elink_restart_autoneg"); /* Enable and restart BAM/CL37 aneg */ if (enable_cl73) { @@ -4876,16 +6111,17 @@ static void elink_restart_autoneg(struct elink_phy *phy, MDIO_REG_BANK_CL73_IEEEB0, MDIO_CL73_IEEEB0_CL73_AN_CONTROL, (mii_control | - MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN | - MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN)); + MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN | + MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN)); } else { CL22_RD_OVER_CL45(sc, phy, MDIO_REG_BANK_COMBO_IEEE0, - MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control); - PMD_DRV_LOG(DEBUG, - "elink_restart_autoneg mii_control before = 0x%x", - mii_control); + MDIO_COMBO_IEEE0_MII_CONTROL, + &mii_control); + ELINK_DEBUG_P1(sc, + "elink_restart_autoneg mii_control before = 0x%x", + mii_control); CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_COMBO_IEEE0, MDIO_COMBO_IEEE0_MII_CONTROL, @@ -4906,7 +6142,8 @@ static void elink_initialize_sgmii_process(struct elink_phy *phy, CL22_RD_OVER_CL45(sc, phy, MDIO_REG_BANK_SERDES_DIGITAL, - MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &control1); + MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, + &control1); control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT; /* Set sgmii mode (and not fiber) */ control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE | @@ -4914,7 +6151,8 @@ static void elink_initialize_sgmii_process(struct elink_phy *phy, MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE); CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_SERDES_DIGITAL, - MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, control1); + MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, + control1); /* If forced speed */ if (!(vars->line_speed == ELINK_SPEED_AUTO_NEG)) { @@ -4923,7 +6161,8 @@ static void elink_initialize_sgmii_process(struct elink_phy *phy, CL22_RD_OVER_CL45(sc, phy, MDIO_REG_BANK_COMBO_IEEE0, - MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control); + MDIO_COMBO_IEEE0_MII_CONTROL, + &mii_control); mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK | MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX); @@ -4931,30 +6170,32 @@ static void elink_initialize_sgmii_process(struct elink_phy *phy, switch (vars->line_speed) { case ELINK_SPEED_100: mii_control |= - MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100; + MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100; break; case ELINK_SPEED_1000: mii_control |= - MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000; + MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000; break; case ELINK_SPEED_10: /* There is nothing to set for 10M */ break; default: /* Invalid speed for SGMII */ - PMD_DRV_LOG(DEBUG, "Invalid line_speed 0x%x", - vars->line_speed); + ELINK_DEBUG_P1(sc, "Invalid line_speed 0x%x", + vars->line_speed); break; } /* Setting the full duplex */ if (phy->req_duplex == DUPLEX_FULL) - mii_control |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX; + mii_control |= + MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX; CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_COMBO_IEEE0, - MDIO_COMBO_IEEE0_MII_CONTROL, mii_control); + MDIO_COMBO_IEEE0_MII_CONTROL, + mii_control); - } else { /* AN mode */ + } else { /* AN mode */ /* Enable and restart AN */ elink_restart_autoneg(phy, params, 0); } @@ -4963,8 +6204,7 @@ static void elink_initialize_sgmii_process(struct elink_phy *phy, /* Link management */ static elink_status_t elink_direct_parallel_detect_used(struct elink_phy *phy, - struct elink_params - *params) + struct elink_params *params) { struct bnx2x_softc *sc = params->sc; uint16_t pd_10g, status2_1000x; @@ -4972,34 +6212,38 @@ static elink_status_t elink_direct_parallel_detect_used(struct elink_phy *phy, return ELINK_STATUS_OK; CL22_RD_OVER_CL45(sc, phy, MDIO_REG_BANK_SERDES_DIGITAL, - MDIO_SERDES_DIGITAL_A_1000X_STATUS2, &status2_1000x); + MDIO_SERDES_DIGITAL_A_1000X_STATUS2, + &status2_1000x); CL22_RD_OVER_CL45(sc, phy, MDIO_REG_BANK_SERDES_DIGITAL, - MDIO_SERDES_DIGITAL_A_1000X_STATUS2, &status2_1000x); + MDIO_SERDES_DIGITAL_A_1000X_STATUS2, + &status2_1000x); if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) { - PMD_DRV_LOG(DEBUG, "1G parallel detect link on port %d", - params->port); - return ELINK_STATUS_ERROR; + ELINK_DEBUG_P1(sc, "1G parallel detect link on port %d", + params->port); + return 1; } CL22_RD_OVER_CL45(sc, phy, MDIO_REG_BANK_10G_PARALLEL_DETECT, - MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS, &pd_10g); + MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS, + &pd_10g); if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) { - PMD_DRV_LOG(DEBUG, "10G parallel detect link on port %d", - params->port); - return ELINK_STATUS_ERROR; + ELINK_DEBUG_P1(sc, "10G parallel detect link on port %d", + params->port); + return 1; } return ELINK_STATUS_OK; } static void elink_update_adv_fc(struct elink_phy *phy, struct elink_params *params, - struct elink_vars *vars, uint32_t gp_status) + struct elink_vars *vars, + uint32_t gp_status) { - uint16_t ld_pause; /* local driver */ - uint16_t lp_pause; /* link partner */ + uint16_t ld_pause; /* local driver */ + uint16_t lp_pause; /* link partner */ uint16_t pause_result; struct bnx2x_softc *sc = params->sc; if ((gp_status & @@ -5010,37 +6254,42 @@ static void elink_update_adv_fc(struct elink_phy *phy, CL22_RD_OVER_CL45(sc, phy, MDIO_REG_BANK_CL73_IEEEB1, - MDIO_CL73_IEEEB1_AN_ADV1, &ld_pause); + MDIO_CL73_IEEEB1_AN_ADV1, + &ld_pause); CL22_RD_OVER_CL45(sc, phy, MDIO_REG_BANK_CL73_IEEEB1, - MDIO_CL73_IEEEB1_AN_LP_ADV1, &lp_pause); + MDIO_CL73_IEEEB1_AN_LP_ADV1, + &lp_pause); pause_result = (ld_pause & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK) >> 8; pause_result |= (lp_pause & MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK) >> 10; - PMD_DRV_LOG(DEBUG, "pause_result CL73 0x%x", pause_result); + ELINK_DEBUG_P1(sc, "pause_result CL73 0x%x", pause_result); } else { CL22_RD_OVER_CL45(sc, phy, MDIO_REG_BANK_COMBO_IEEE0, - MDIO_COMBO_IEEE0_AUTO_NEG_ADV, &ld_pause); + MDIO_COMBO_IEEE0_AUTO_NEG_ADV, + &ld_pause); CL22_RD_OVER_CL45(sc, phy, - MDIO_REG_BANK_COMBO_IEEE0, - MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1, - &lp_pause); + MDIO_REG_BANK_COMBO_IEEE0, + MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1, + &lp_pause); pause_result = (ld_pause & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) >> 5; pause_result |= (lp_pause & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) >> 7; - PMD_DRV_LOG(DEBUG, "pause_result CL37 0x%x", pause_result); + ELINK_DEBUG_P1(sc, "pause_result CL37 0x%x", pause_result); } - elink_pause_resolve(vars, pause_result); + elink_pause_resolve(phy, params, vars, pause_result); } static void elink_flow_ctrl_resolve(struct elink_phy *phy, struct elink_params *params, - struct elink_vars *vars, uint32_t gp_status) + struct elink_vars *vars, + uint32_t gp_status) { + struct bnx2x_softc *sc = params->sc; vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; /* Resolve from gp_status in case of AN complete and not sgmii */ @@ -5060,7 +6309,7 @@ static void elink_flow_ctrl_resolve(struct elink_phy *phy, } elink_update_adv_fc(phy, params, vars, gp_status); } - PMD_DRV_LOG(DEBUG, "flow_ctrl 0x%x", vars->flow_ctrl); + ELINK_DEBUG_P1(sc, "flow_ctrl 0x%x", vars->flow_ctrl); } static void elink_check_fallback_to_cl37(struct elink_phy *phy, @@ -5068,14 +6317,16 @@ static void elink_check_fallback_to_cl37(struct elink_phy *phy, { struct bnx2x_softc *sc = params->sc; uint16_t rx_status, ustat_val, cl37_fsm_received; - PMD_DRV_LOG(DEBUG, "elink_check_fallback_to_cl37"); + ELINK_DEBUG_P0(sc, "elink_check_fallback_to_cl37"); /* Step 1: Make sure signal is detected */ CL22_RD_OVER_CL45(sc, phy, - MDIO_REG_BANK_RX0, MDIO_RX0_RX_STATUS, &rx_status); + MDIO_REG_BANK_RX0, + MDIO_RX0_RX_STATUS, + &rx_status); if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) != (MDIO_RX0_RX_STATUS_SIGDET)) { - PMD_DRV_LOG(DEBUG, "Signal is not detected. Restoring CL73." - "rx_status(0x80b0) = 0x%x", rx_status); + ELINK_DEBUG_P1(sc, "Signal is not detected. Restoring CL73." + "rx_status(0x80b0) = 0x%x", rx_status); CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_CL73_IEEEB0, MDIO_CL73_IEEEB0_CL73_AN_CONTROL, @@ -5085,14 +6336,15 @@ static void elink_check_fallback_to_cl37(struct elink_phy *phy, /* Step 2: Check CL73 state machine */ CL22_RD_OVER_CL45(sc, phy, MDIO_REG_BANK_CL73_USERB0, - MDIO_CL73_USERB0_CL73_USTAT1, &ustat_val); + MDIO_CL73_USERB0_CL73_USTAT1, + &ustat_val); if ((ustat_val & (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK | MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) != (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK | - MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) { - PMD_DRV_LOG(DEBUG, "CL73 state-machine is not stable. " - "ustat_val(0x8371) = 0x%x", ustat_val); + MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) { + ELINK_DEBUG_P1(sc, "CL73 state-machine is not stable. " + "ustat_val(0x8371) = 0x%x", ustat_val); return; } /* Step 3: Check CL37 Message Pages received to indicate LP @@ -5100,14 +6352,16 @@ static void elink_check_fallback_to_cl37(struct elink_phy *phy, */ CL22_RD_OVER_CL45(sc, phy, MDIO_REG_BANK_REMOTE_PHY, - MDIO_REMOTE_PHY_MISC_RX_STATUS, &cl37_fsm_received); + MDIO_REMOTE_PHY_MISC_RX_STATUS, + &cl37_fsm_received); if ((cl37_fsm_received & (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG | - MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) != + MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) != (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG | - MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) { - PMD_DRV_LOG(DEBUG, "No CL37 FSM were received. " - "misc_rx_status(0x8330) = 0x%x", cl37_fsm_received); + MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) { + ELINK_DEBUG_P1(sc, "No CL37 FSM were received. " + "misc_rx_status(0x8330) = 0x%x", + cl37_fsm_received); return; } /* The combined cl37/cl73 fsm state information indicating that @@ -5119,34 +6373,38 @@ static void elink_check_fallback_to_cl37(struct elink_phy *phy, /* Disable CL73 */ CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_CL73_IEEEB0, - MDIO_CL73_IEEEB0_CL73_AN_CONTROL, 0); + MDIO_CL73_IEEEB0_CL73_AN_CONTROL, + 0); /* Restart CL37 autoneg */ elink_restart_autoneg(phy, params, 0); - PMD_DRV_LOG(DEBUG, "Disabling CL73, and restarting CL37 autoneg"); + ELINK_DEBUG_P0(sc, "Disabling CL73, and restarting CL37 autoneg"); } static void elink_xgxs_an_resolve(struct elink_phy *phy, struct elink_params *params, - struct elink_vars *vars, uint32_t gp_status) + struct elink_vars *vars, + uint32_t gp_status) { if (gp_status & ELINK_MDIO_AN_CL73_OR_37_COMPLETE) - vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; + vars->link_status |= + LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; if (elink_direct_parallel_detect_used(phy, params)) - vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED; + vars->link_status |= + LINK_STATUS_PARALLEL_DETECTION_USED; } - static elink_status_t elink_get_link_speed_duplex(struct elink_phy *phy, - struct elink_params *params __rte_unused, - struct elink_vars *vars, - uint16_t is_link_up, - uint16_t speed_mask, - uint16_t is_duplex) + struct elink_params *params, + struct elink_vars *vars, + uint16_t is_link_up, + uint16_t speed_mask, + uint16_t is_duplex) { + struct bnx2x_softc *sc = params->sc; if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED; if (is_link_up) { - PMD_DRV_LOG(DEBUG, "phy link up"); + ELINK_DEBUG_P0(sc, "phy link up"); vars->phy_link_up = 1; vars->link_status |= LINK_STATUS_LINK_UP; @@ -5187,9 +6445,9 @@ static elink_status_t elink_get_link_speed_duplex(struct elink_phy *phy, case ELINK_GP_STATUS_5G: case ELINK_GP_STATUS_6G: - PMD_DRV_LOG(DEBUG, - "link speed unsupported gp_status 0x%x", - speed_mask); + ELINK_DEBUG_P1(sc, + "link speed unsupported gp_status 0x%x", + speed_mask); return ELINK_STATUS_ERROR; case ELINK_GP_STATUS_10G_KX4: @@ -5207,13 +6465,13 @@ static elink_status_t elink_get_link_speed_duplex(struct elink_phy *phy, vars->link_status |= ELINK_LINK_20GTFD; break; default: - PMD_DRV_LOG(DEBUG, - "link speed unsupported gp_status 0x%x", - speed_mask); + ELINK_DEBUG_P1(sc, + "link speed unsupported gp_status 0x%x", + speed_mask); return ELINK_STATUS_ERROR; } - } else { /* link_down */ - PMD_DRV_LOG(DEBUG, "phy link down"); + } else { /* link_down */ + ELINK_DEBUG_P0(sc, "phy link down"); vars->phy_link_up = 0; @@ -5221,14 +6479,16 @@ static elink_status_t elink_get_link_speed_duplex(struct elink_phy *phy, vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; vars->mac_type = ELINK_MAC_TYPE_NONE; } - PMD_DRV_LOG(DEBUG, " phy_link_up %x line_speed %d", + ELINK_DEBUG_P2(sc, " in elink_get_link_speed_duplex vars->link_status = %x, vars->duplex = %x", + vars->link_status, vars->duplex); + ELINK_DEBUG_P2(sc, " phy_link_up %x line_speed %d", vars->phy_link_up, vars->line_speed); return ELINK_STATUS_OK; } static uint8_t elink_link_settings_status(struct elink_phy *phy, - struct elink_params *params, - struct elink_vars *vars) + struct elink_params *params, + struct elink_vars *vars) { struct bnx2x_softc *sc = params->sc; @@ -5238,14 +6498,23 @@ static uint8_t elink_link_settings_status(struct elink_phy *phy, /* Read gp_status */ CL22_RD_OVER_CL45(sc, phy, MDIO_REG_BANK_GP_STATUS, - MDIO_GP_STATUS_TOP_AN_STATUS1, &gp_status); - if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS) + MDIO_GP_STATUS_TOP_AN_STATUS1, + &gp_status); + if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS) { duplex = DUPLEX_FULL; + ELINK_DEBUG_P1(sc, "duplex status read from phy is = %x", + duplex); + } else { + ELINK_DEBUG_P1(sc, "phy status does not allow interface to be FULL_DUPLEX : %x", + gp_status); + } + + if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) link_up = 1; speed_mask = gp_status & ELINK_GP_STATUS_SPEED_MASK; - PMD_DRV_LOG(DEBUG, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x", - gp_status, link_up, speed_mask); + ELINK_DEBUG_P3(sc, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x", + gp_status, link_up, speed_mask); rc = elink_get_link_speed_duplex(phy, params, vars, link_up, speed_mask, duplex); if (rc == ELINK_STATUS_ERROR) @@ -5259,7 +6528,7 @@ static uint8_t elink_link_settings_status(struct elink_phy *phy, elink_xgxs_an_resolve(phy, params, vars, gp_status); } - } else { /* Link_down */ + } else { /* Link_down */ if ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) && ELINK_SINGLE_MEDIA_DIRECT(params)) { /* Check signal is detected */ @@ -5267,7 +6536,7 @@ static uint8_t elink_link_settings_status(struct elink_phy *phy, } } - /* Read LP advertised speeds */ + /* Read LP advertised speeds*/ if (ELINK_SINGLE_MEDIA_DIRECT(params) && (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)) { uint16_t val; @@ -5277,61 +6546,69 @@ static uint8_t elink_link_settings_status(struct elink_phy *phy, if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX) vars->link_status |= - LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; + LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 | MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR)) vars->link_status |= - LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; + LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; CL22_RD_OVER_CL45(sc, phy, MDIO_REG_BANK_OVER_1G, MDIO_OVER_1G_LP_UP1, &val); if (val & MDIO_OVER_1G_UP1_2_5G) vars->link_status |= - LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE; + LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE; if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH)) vars->link_status |= - LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; + LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; } - PMD_DRV_LOG(DEBUG, "duplex %x flow_ctrl 0x%x link_status 0x%x", - vars->duplex, vars->flow_ctrl, vars->link_status); + ELINK_DEBUG_P3(sc, "duplex %x flow_ctrl 0x%x link_status 0x%x", + vars->duplex, vars->flow_ctrl, vars->link_status); return rc; } static uint8_t elink_warpcore_read_status(struct elink_phy *phy, - struct elink_params *params, - struct elink_vars *vars) + struct elink_params *params, + struct elink_vars *vars) { struct bnx2x_softc *sc = params->sc; uint8_t lane; uint16_t gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL; elink_status_t rc = ELINK_STATUS_OK; - lane = elink_get_warpcore_lane(params); + lane = elink_get_warpcore_lane(phy, params); /* Read gp_status */ - if ((params->loopback_mode) && (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)) { + if ((params->loopback_mode) && + (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)) { elink_cl45_read(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up); elink_cl45_read(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up); link_up &= 0x1; + ELINK_DEBUG_P1(sc, "params->loopback_mode link_up read = %x", + link_up); } else if ((phy->req_line_speed > ELINK_SPEED_10000) && - (phy->supported & ELINK_SUPPORTED_20000baseMLD2_Full)) { + (phy->supported & ELINK_SUPPORTED_20000baseMLD2_Full)) { uint16_t temp_link_up; - elink_cl45_read(sc, phy, MDIO_WC_DEVAD, 1, &temp_link_up); - elink_cl45_read(sc, phy, MDIO_WC_DEVAD, 1, &link_up); - PMD_DRV_LOG(DEBUG, "PCS RX link status = 0x%x-->0x%x", - temp_link_up, link_up); + elink_cl45_read(sc, phy, MDIO_WC_DEVAD, + 1, &temp_link_up); + elink_cl45_read(sc, phy, MDIO_WC_DEVAD, + 1, &link_up); + ELINK_DEBUG_P2(sc, "PCS RX link status = 0x%x-->0x%x", + temp_link_up, link_up); link_up &= (1 << 2); if (link_up) elink_ext_phy_resolve_fc(phy, params, vars); } else { elink_cl45_read(sc, phy, MDIO_WC_DEVAD, - MDIO_WC_REG_GP2_STATUS_GP_2_1, &gp_status1); - PMD_DRV_LOG(DEBUG, "0x81d1 = 0x%x", gp_status1); + MDIO_WC_REG_GP2_STATUS_GP_2_1, + &gp_status1); + ELINK_DEBUG_P1(sc, "0x81d1 = 0x%x", gp_status1); /* Check for either KR, 1G, or AN up. */ link_up = ((gp_status1 >> 8) | - (gp_status1 >> 12) | (gp_status1)) & (1 << lane); + (gp_status1 >> 12) | + (gp_status1)) & + (1 << lane); if (phy->supported & ELINK_SUPPORTED_20000baseKR2_Full) { uint16_t an_link; elink_cl45_read(sc, phy, MDIO_AN_DEVAD, @@ -5339,6 +6616,8 @@ static uint8_t elink_warpcore_read_status(struct elink_phy *phy, elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_STATUS, &an_link); link_up |= (an_link & (1 << 2)); + ELINK_DEBUG_P2(sc, "an_link = %x, link_up = %x", + an_link, link_up); } if (link_up && ELINK_SINGLE_MEDIA_DIRECT(params)) { uint16_t pd, gp_status4; @@ -5349,7 +6628,7 @@ static uint8_t elink_warpcore_read_status(struct elink_phy *phy, &gp_status4); if (gp_status4 & ((1 << 12) << lane)) vars->link_status |= - LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; + LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; /* Check parallel detect used */ elink_cl45_read(sc, phy, MDIO_WC_DEVAD, @@ -5357,13 +6636,19 @@ static uint8_t elink_warpcore_read_status(struct elink_phy *phy, &pd); if (pd & (1 << 15)) vars->link_status |= - LINK_STATUS_PARALLEL_DETECTION_USED; + LINK_STATUS_PARALLEL_DETECTION_USED; + ELINK_DEBUG_P2(sc, "pd = %x, link_status = %x", + pd, vars->link_status); } elink_ext_phy_resolve_fc(phy, params, vars); vars->duplex = duplex; + ELINK_DEBUG_P3(sc, " ELINK_SINGLE_MEDIA_DIRECT duplex %x flow_ctrl 0x%x link_status 0x%x", + vars->duplex, vars->flow_ctrl, + vars->link_status); } } - + ELINK_DEBUG_P3(sc, "duplex %x flow_ctrl 0x%x link_status 0x%x", + vars->duplex, vars->flow_ctrl, vars->link_status); if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) && ELINK_SINGLE_MEDIA_DIRECT(params)) { uint16_t val; @@ -5373,24 +6658,28 @@ static uint8_t elink_warpcore_read_status(struct elink_phy *phy, if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX) vars->link_status |= - LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; + LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 | MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR)) vars->link_status |= - LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; - + LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; + ELINK_DEBUG_P2(sc, "val = %x, link_status = %x", + val, vars->link_status); elink_cl45_read(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL3_LP_UP1, &val); if (val & MDIO_OVER_1G_UP1_2_5G) vars->link_status |= - LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE; + LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE; if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH)) vars->link_status |= - LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; + LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; + ELINK_DEBUG_P2(sc, "val = %x, link_status = %x", + val, vars->link_status); } + if (lane < 2) { elink_cl45_read(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_2, &gp_speed); @@ -5398,12 +6687,12 @@ static uint8_t elink_warpcore_read_status(struct elink_phy *phy, elink_cl45_read(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_3, &gp_speed); } - PMD_DRV_LOG(DEBUG, "lane %d gp_speed 0x%x", lane, gp_speed); + ELINK_DEBUG_P2(sc, "lane %d gp_speed 0x%x", lane, gp_speed); if ((lane & 1) == 0) gp_speed <<= 8; gp_speed &= 0x3f00; - link_up = ! !link_up; + link_up = !!link_up; /* Reset the TX FIFO to fix SGMII issue */ rc = elink_get_link_speed_duplex(phy, params, vars, link_up, gp_speed, @@ -5414,11 +6703,10 @@ static uint8_t elink_warpcore_read_status(struct elink_phy *phy, (!(phy->flags & ELINK_FLAGS_WC_DUAL_MODE))) vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY; - PMD_DRV_LOG(DEBUG, "duplex %x flow_ctrl 0x%x link_status 0x%x", - vars->duplex, vars->flow_ctrl, vars->link_status); + ELINK_DEBUG_P3(sc, "duplex %x flow_ctrl 0x%x link_status 0x%x", + vars->duplex, vars->flow_ctrl, vars->link_status); return rc; } - static void elink_set_gmii_tx_driver(struct elink_params *params) { struct bnx2x_softc *sc = params->sc; @@ -5429,7 +6717,8 @@ static void elink_set_gmii_tx_driver(struct elink_params *params) /* Read precomp */ CL22_RD_OVER_CL45(sc, phy, - MDIO_REG_BANK_OVER_1G, MDIO_OVER_1G_LP_UP2, &lp_up2); + MDIO_REG_BANK_OVER_1G, + MDIO_OVER_1G_LP_UP2, &lp_up2); /* Bits [10:7] at lp_up2, positioned at [15:12] */ lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >> @@ -5440,32 +6729,36 @@ static void elink_set_gmii_tx_driver(struct elink_params *params) return; for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3; - bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) { + bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) { CL22_RD_OVER_CL45(sc, phy, - bank, MDIO_TX0_TX_DRIVER, &tx_driver); + bank, + MDIO_TX0_TX_DRIVER, &tx_driver); /* Replace tx_driver bits [15:12] */ - if (lp_up2 != (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) { + if (lp_up2 != + (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) { tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK; tx_driver |= lp_up2; CL22_WR_OVER_CL45(sc, phy, - bank, MDIO_TX0_TX_DRIVER, tx_driver); + bank, + MDIO_TX0_TX_DRIVER, tx_driver); } } } static elink_status_t elink_emac_program(struct elink_params *params, - struct elink_vars *vars) + struct elink_vars *vars) { struct bnx2x_softc *sc = params->sc; uint8_t port = params->port; uint16_t mode = 0; - PMD_DRV_LOG(DEBUG, "setting link speed & duplex"); + ELINK_DEBUG_P0(sc, "setting link speed & duplex"); elink_bits_dis(sc, GRCBASE_EMAC0 + port * 0x400 + EMAC_REG_EMAC_MODE, (EMAC_MODE_25G_MODE | - EMAC_MODE_PORT_MII_10M | EMAC_MODE_HALF_DUPLEX)); + EMAC_MODE_PORT_MII_10M | + EMAC_MODE_HALF_DUPLEX)); switch (vars->line_speed) { case ELINK_SPEED_10: mode |= EMAC_MODE_PORT_MII_10M; @@ -5485,14 +6778,16 @@ static elink_status_t elink_emac_program(struct elink_params *params, default: /* 10G not valid for EMAC */ - PMD_DRV_LOG(DEBUG, "Invalid line_speed 0x%x", vars->line_speed); + ELINK_DEBUG_P1(sc, "Invalid line_speed 0x%x", + vars->line_speed); return ELINK_STATUS_ERROR; } if (vars->duplex == DUPLEX_HALF) mode |= EMAC_MODE_HALF_DUPLEX; elink_bits_en(sc, - GRCBASE_EMAC0 + port * 0x400 + EMAC_REG_EMAC_MODE, mode); + GRCBASE_EMAC0 + port * 0x400 + EMAC_REG_EMAC_MODE, + mode); elink_set_led(params, vars, ELINK_LED_MODE_OPER, vars->line_speed); return ELINK_STATUS_OK; @@ -5509,24 +6804,26 @@ static void elink_set_preemphasis(struct elink_phy *phy, bank += (MDIO_REG_BANK_RX1 - MDIO_REG_BANK_RX0), i++) { CL22_WR_OVER_CL45(sc, phy, bank, - MDIO_RX0_RX_EQ_BOOST, phy->rx_preemphasis[i]); + MDIO_RX0_RX_EQ_BOOST, + phy->rx_preemphasis[i]); } for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3; bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) { CL22_WR_OVER_CL45(sc, phy, bank, - MDIO_TX0_TX_DRIVER, phy->tx_preemphasis[i]); + MDIO_TX0_TX_DRIVER, + phy->tx_preemphasis[i]); } } static uint8_t elink_xgxs_config_init(struct elink_phy *phy, - struct elink_params *params, - struct elink_vars *vars) + struct elink_params *params, + struct elink_vars *vars) { + struct bnx2x_softc *sc = params->sc; uint8_t enable_cl73 = (ELINK_SINGLE_MEDIA_DIRECT(params) || - (params->loopback_mode == ELINK_LOOPBACK_XGXS)); - + (params->loopback_mode == ELINK_LOOPBACK_XGXS)); if (!(vars->phy_flags & PHY_SGMII_FLAG)) { if (ELINK_SINGLE_MEDIA_DIRECT(params) && (params->feature_config_flags & @@ -5537,7 +6834,7 @@ static uint8_t elink_xgxs_config_init(struct elink_phy *phy, if (vars->line_speed != ELINK_SPEED_AUTO_NEG || (ELINK_SINGLE_MEDIA_DIRECT(params) && params->loopback_mode == ELINK_LOOPBACK_EXT)) { - PMD_DRV_LOG(DEBUG, "not SGMII, no AN"); + ELINK_DEBUG_P0(sc, "not SGMII, no AN"); /* Disable autoneg */ elink_set_autoneg(phy, params, vars, 0); @@ -5545,8 +6842,8 @@ static uint8_t elink_xgxs_config_init(struct elink_phy *phy, /* Program speed and duplex */ elink_program_serdes(phy, params, vars); - } else { /* AN_mode */ - PMD_DRV_LOG(DEBUG, "not SGMII, AN"); + } else { /* AN_mode */ + ELINK_DEBUG_P0(sc, "not SGMII, AN"); /* AN enabled */ elink_set_brcm_cl37_advertisement(phy, params); @@ -5562,8 +6859,8 @@ static uint8_t elink_xgxs_config_init(struct elink_phy *phy, elink_restart_autoneg(phy, params, enable_cl73); } - } else { /* SGMII mode */ - PMD_DRV_LOG(DEBUG, "SGMII"); + } else { /* SGMII mode */ + ELINK_DEBUG_P0(sc, "SGMII"); elink_initialize_sgmii_process(phy, params, vars); } @@ -5572,8 +6869,8 @@ static uint8_t elink_xgxs_config_init(struct elink_phy *phy, } static elink_status_t elink_prepare_xgxs(struct elink_phy *phy, - struct elink_params *params, - struct elink_vars *vars) + struct elink_params *params, + struct elink_vars *vars) { elink_status_t rc; vars->phy_flags |= PHY_XGXS_FLAG; @@ -5611,28 +6908,32 @@ static elink_status_t elink_prepare_xgxs(struct elink_phy *phy, } static uint16_t elink_wait_reset_complete(struct bnx2x_softc *sc, - struct elink_phy *phy, - struct elink_params *params) + struct elink_phy *phy, + struct elink_params *params) { uint16_t cnt, ctrl; /* Wait for soft reset to get cleared up to 1 sec */ for (cnt = 0; cnt < 1000; cnt++) { - if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE) - elink_cl22_read(sc, phy, MDIO_PMA_REG_CTRL, &ctrl); + if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X54618SE) + elink_cl22_read(sc, phy, + MDIO_PMA_REG_CTRL, &ctrl); else elink_cl45_read(sc, phy, - MDIO_PMA_DEVAD, - MDIO_PMA_REG_CTRL, &ctrl); + MDIO_PMA_DEVAD, + MDIO_PMA_REG_CTRL, &ctrl); if (!(ctrl & (1 << 15))) break; DELAY(1000 * 1); } if (cnt == 1000) - elink_cb_event_log(sc, ELINK_LOG_ID_PHY_UNINITIALIZED, params->port); // "Warning: PHY was not initialized," - // " Port %d", + elink_cb_event_log(sc, ELINK_LOG_ID_PHY_UNINITIALIZED, + params->port); + /* "Warning: PHY was not initialized," + * " Port %d", + */ - PMD_DRV_LOG(DEBUG, "control reg 0x%x (after %d ms)", ctrl, cnt); + ELINK_DEBUG_P2(sc, "control reg 0x%x (after %d ms)", ctrl, cnt); return cnt; } @@ -5650,37 +6951,38 @@ static void elink_link_int_enable(struct elink_params *params) } else if (params->switch_cfg == ELINK_SWITCH_CFG_10G) { mask = (ELINK_NIG_MASK_XGXS0_LINK10G | ELINK_NIG_MASK_XGXS0_LINK_STATUS); - PMD_DRV_LOG(DEBUG, "enabled XGXS interrupt"); + ELINK_DEBUG_P0(sc, "enabled XGXS interrupt"); if (!(ELINK_SINGLE_MEDIA_DIRECT(params)) && - params->phy[ELINK_INT_PHY].type != - PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) { + params->phy[ELINK_INT_PHY].type != + PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) { mask |= ELINK_NIG_MASK_MI_INT; - PMD_DRV_LOG(DEBUG, "enabled external phy int"); + ELINK_DEBUG_P0(sc, "enabled external phy int"); } - } else { /* SerDes */ + } else { /* SerDes */ mask = ELINK_NIG_MASK_SERDES0_LINK_STATUS; - PMD_DRV_LOG(DEBUG, "enabled SerDes interrupt"); + ELINK_DEBUG_P0(sc, "enabled SerDes interrupt"); if (!(ELINK_SINGLE_MEDIA_DIRECT(params)) && - params->phy[ELINK_INT_PHY].type != - PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) { + params->phy[ELINK_INT_PHY].type != + PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) { mask |= ELINK_NIG_MASK_MI_INT; - PMD_DRV_LOG(DEBUG, "enabled external phy int"); + ELINK_DEBUG_P0(sc, "enabled external phy int"); } } - elink_bits_en(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, mask); + elink_bits_en(sc, + NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, + mask); - PMD_DRV_LOG(DEBUG, "port %x, is_xgxs %x, int_status 0x%x", port, - (params->switch_cfg == ELINK_SWITCH_CFG_10G), - REG_RD(sc, NIG_REG_STATUS_INTERRUPT_PORT0 + port * 4)); - PMD_DRV_LOG(DEBUG, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x", - REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4), - REG_RD(sc, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port * 0x18), - REG_RD(sc, - NIG_REG_SERDES0_STATUS_LINK_STATUS + port * 0x3c)); - PMD_DRV_LOG(DEBUG, " 10G %x, XGXS_LINK %x", - REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK10G + port * 0x68), - REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK_STATUS + port * 0x68)); + ELINK_DEBUG_P3(sc, "port %x, is_xgxs %x, int_status 0x%x", port, + (params->switch_cfg == ELINK_SWITCH_CFG_10G), + REG_RD(sc, NIG_REG_STATUS_INTERRUPT_PORT0 + port * 4)); + ELINK_DEBUG_P3(sc, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x", + REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4), + REG_RD(sc, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port * 0x18), + REG_RD(sc, NIG_REG_SERDES0_STATUS_LINK_STATUS + port * 0x3c)); + ELINK_DEBUG_P2(sc, " 10G %x, XGXS_LINK %x", + REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK10G + port * 0x68), + REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK_STATUS + port * 0x68)); } static void elink_rearm_latch_signal(struct bnx2x_softc *sc, uint8_t port, @@ -5693,17 +6995,20 @@ static void elink_rearm_latch_signal(struct bnx2x_softc *sc, uint8_t port, * so in this case we need to write the status to clear the XOR */ /* Read Latched signals */ - latch_status = REG_RD(sc, NIG_REG_LATCH_STATUS_0 + port * 8); - PMD_DRV_LOG(DEBUG, "latch_status = 0x%x", latch_status); - /* Handle only those with latched-signal=up. */ + latch_status = REG_RD(sc, + NIG_REG_LATCH_STATUS_0 + port * 8); + ELINK_DEBUG_P1(sc, "latch_status = 0x%x", latch_status); + /* Handle only those with latched-signal=up.*/ if (exp_mi_int) elink_bits_en(sc, NIG_REG_STATUS_INTERRUPT_PORT0 - + port * 4, ELINK_NIG_STATUS_EMAC0_MI_INT); + + port * 4, + ELINK_NIG_STATUS_EMAC0_MI_INT); else elink_bits_dis(sc, NIG_REG_STATUS_INTERRUPT_PORT0 - + port * 4, ELINK_NIG_STATUS_EMAC0_MI_INT); + + port * 4, + ELINK_NIG_STATUS_EMAC0_MI_INT); if (latch_status & 1) { @@ -5738,23 +7043,24 @@ static void elink_link_int_ack(struct elink_params *params, * the relevant lane in the status register */ uint32_t ser_lane = - ((params->lane_config & - PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> - PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); + ((params->lane_config & + PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> + PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); mask = ((1 << ser_lane) << - ELINK_NIG_STATUS_XGXS0_LINK_STATUS_SIZE); + ELINK_NIG_STATUS_XGXS0_LINK_STATUS_SIZE); } else mask = ELINK_NIG_STATUS_SERDES0_LINK_STATUS; } - PMD_DRV_LOG(DEBUG, "Ack link up interrupt with mask 0x%x", - mask); + ELINK_DEBUG_P1(sc, "Ack link up interrupt with mask 0x%x", + mask); elink_bits_en(sc, - NIG_REG_STATUS_INTERRUPT_PORT0 + port * 4, mask); + NIG_REG_STATUS_INTERRUPT_PORT0 + port * 4, + mask); } } -static uint8_t elink_format_ver(uint32_t num, uint8_t * str, - uint16_t * len) +static elink_status_t elink_format_ver(uint32_t num, uint8_t *str, + uint16_t *len) { uint8_t *str_ptr = str; uint32_t mask = 0xf0000000; @@ -5792,14 +7098,57 @@ static uint8_t elink_format_ver(uint32_t num, uint8_t * str, return ELINK_STATUS_OK; } -static uint8_t elink_null_format_ver(__rte_unused uint32_t spirom_ver, - uint8_t * str, uint16_t * len) + +static elink_status_t elink_null_format_ver(__rte_unused uint32_t spirom_ver, + uint8_t *str, + uint16_t *len) { str[0] = '\0'; (*len)--; return ELINK_STATUS_OK; } +elink_status_t elink_get_ext_phy_fw_version(struct elink_params *params, + uint8_t *version, + uint16_t len) +{ + struct bnx2x_softc *sc; + uint32_t spirom_ver = 0; + elink_status_t status = ELINK_STATUS_OK; + uint8_t *ver_p = version; + uint16_t remain_len = len; + if (version == NULL || params == NULL) + return ELINK_STATUS_ERROR; + sc = params->sc; + + /* Extract first external phy*/ + version[0] = '\0'; + spirom_ver = REG_RD(sc, params->phy[ELINK_EXT_PHY1].ver_addr); + + if (params->phy[ELINK_EXT_PHY1].format_fw_ver) { + status |= params->phy[ELINK_EXT_PHY1].format_fw_ver(spirom_ver, + ver_p, + &remain_len); + ver_p += (len - remain_len); + } + if ((params->num_phys == ELINK_MAX_PHYS) && + (params->phy[ELINK_EXT_PHY2].ver_addr != 0)) { + spirom_ver = REG_RD(sc, params->phy[ELINK_EXT_PHY2].ver_addr); + if (params->phy[ELINK_EXT_PHY2].format_fw_ver) { + *ver_p = '/'; + ver_p++; + remain_len--; + status |= params->phy[ELINK_EXT_PHY2].format_fw_ver( + spirom_ver, + ver_p, + &remain_len); + ver_p = version + (len - remain_len); + } + } + *ver_p = '\0'; + return status; +} + static void elink_set_xgxs_loopback(struct elink_phy *phy, struct elink_params *params) { @@ -5809,7 +7158,7 @@ static void elink_set_xgxs_loopback(struct elink_phy *phy, if (phy->req_line_speed != ELINK_SPEED_1000) { uint32_t md_devad = 0; - PMD_DRV_LOG(DEBUG, "XGXS 10G loopback enable"); + ELINK_DEBUG_P0(sc, "XGXS 10G loopback enable"); if (!CHIP_IS_E3(sc)) { /* Change the uni_phy_addr in the nig */ @@ -5823,7 +7172,8 @@ static void elink_set_xgxs_loopback(struct elink_phy *phy, elink_cl45_write(sc, phy, 5, (MDIO_REG_BANK_AER_BLOCK + - (MDIO_AER_BLOCK_AER_REG & 0xf)), 0x2800); + (MDIO_AER_BLOCK_AER_REG & 0xf)), + 0x2800); elink_cl45_write(sc, phy, 5, @@ -5841,22 +7191,21 @@ static void elink_set_xgxs_loopback(struct elink_phy *phy, } } else { uint16_t mii_ctrl; - PMD_DRV_LOG(DEBUG, "XGXS 1G loopback enable"); + ELINK_DEBUG_P0(sc, "XGXS 1G loopback enable"); elink_cl45_read(sc, phy, 5, (MDIO_REG_BANK_COMBO_IEEE0 + - (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)), + (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)), &mii_ctrl); elink_cl45_write(sc, phy, 5, (MDIO_REG_BANK_COMBO_IEEE0 + - (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)), + (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)), mii_ctrl | MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK); } } elink_status_t elink_set_led(struct elink_params *params, - struct elink_vars *vars, uint8_t mode, - uint32_t speed) + struct elink_vars *vars, uint8_t mode, uint32_t speed) { uint8_t port = params->port; uint16_t hw_led_mode = params->hw_led_mode; @@ -5865,15 +7214,21 @@ elink_status_t elink_set_led(struct elink_params *params, uint32_t tmp; uint32_t emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; struct bnx2x_softc *sc = params->sc; - PMD_DRV_LOG(DEBUG, "elink_set_led: port %x, mode %d", port, mode); - PMD_DRV_LOG(DEBUG, "speed 0x%x, hw_led_mode 0x%x", speed, hw_led_mode); + ELINK_DEBUG_P2(sc, "elink_set_led: port %x, mode %d", port, mode); + ELINK_DEBUG_P2(sc, "speed 0x%x, hw_led_mode 0x%x", + speed, hw_led_mode); /* In case */ for (phy_idx = ELINK_EXT_PHY1; phy_idx < ELINK_MAX_PHYS; phy_idx++) { if (params->phy[phy_idx].set_link_led) { - params->phy[phy_idx].set_link_led(¶ms->phy[phy_idx], - params, mode); + params->phy[phy_idx].set_link_led( + ¶ms->phy[phy_idx], params, mode); } } +#ifdef ELINK_INCLUDE_EMUL + if (params->feature_config_flags & + ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC) + return rc; +#endif switch (mode) { case ELINK_LED_MODE_FRONT_PANEL_OFF: @@ -5884,10 +7239,10 @@ elink_status_t elink_set_led(struct elink_params *params, tmp = elink_cb_reg_read(sc, emac_base + EMAC_REG_EMAC_LED); if (params->phy[ELINK_EXT_PHY1].type == - PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE) + PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X54618SE) tmp &= ~(EMAC_LED_1000MB_OVERRIDE | - EMAC_LED_100MB_OVERRIDE | - EMAC_LED_10MB_OVERRIDE); + EMAC_LED_100MB_OVERRIDE | + EMAC_LED_10MB_OVERRIDE); else tmp |= EMAC_LED_OVERRIDE; @@ -5900,25 +7255,22 @@ elink_status_t elink_set_led(struct elink_params *params, */ if (!vars->link_up) break; - /* fall-through */ + /* fallthrough */ case ELINK_LED_MODE_ON: if (((params->phy[ELINK_EXT_PHY1].type == - PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727) || - (params->phy[ELINK_EXT_PHY1].type == - PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722)) && + PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727) || + (params->phy[ELINK_EXT_PHY1].type == + PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722)) && CHIP_IS_E2(sc) && params->num_phys == 2) { - /* This is a work-around for E2+8727 Configurations */ + /* This is a work-around for E2 + 8727 Configurations */ if (mode == ELINK_LED_MODE_ON || - speed == ELINK_SPEED_10000) { + speed == ELINK_SPEED_10000){ REG_WR(sc, NIG_REG_LED_MODE_P0 + port * 4, 0); REG_WR(sc, NIG_REG_LED_10G_P0 + port * 4, 1); - tmp = - elink_cb_reg_read(sc, - emac_base + - EMAC_REG_EMAC_LED); - elink_cb_reg_write(sc, - emac_base + + tmp = elink_cb_reg_read(sc, emac_base + + EMAC_REG_EMAC_LED); + elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_LED, (tmp | EMAC_LED_OVERRIDE)); /* Return here without enabling traffic @@ -5934,22 +7286,23 @@ elink_status_t elink_set_led(struct elink_params *params, * is up in CL73 */ if ((!CHIP_IS_E3(sc)) || - (CHIP_IS_E3(sc) && mode == ELINK_LED_MODE_ON)) + (CHIP_IS_E3(sc) && + mode == ELINK_LED_MODE_ON)) REG_WR(sc, NIG_REG_LED_10G_P0 + port * 4, 1); if (CHIP_IS_E1x(sc) || - CHIP_IS_E2(sc) || (mode == ELINK_LED_MODE_ON)) + CHIP_IS_E2(sc) || + (mode == ELINK_LED_MODE_ON)) REG_WR(sc, NIG_REG_LED_MODE_P0 + port * 4, 0); else REG_WR(sc, NIG_REG_LED_MODE_P0 + port * 4, hw_led_mode); } else if ((params->phy[ELINK_EXT_PHY1].type == - PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE) && + PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X54618SE) && (mode == ELINK_LED_MODE_ON)) { REG_WR(sc, NIG_REG_LED_MODE_P0 + port * 4, 0); - tmp = - elink_cb_reg_read(sc, - emac_base + EMAC_REG_EMAC_LED); + tmp = elink_cb_reg_read(sc, emac_base + + EMAC_REG_EMAC_LED); elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_LED, tmp | EMAC_LED_OVERRIDE | EMAC_LED_1000MB_OVERRIDE); @@ -5959,11 +7312,10 @@ elink_status_t elink_set_led(struct elink_params *params, break; } else { uint32_t nig_led_mode = ((params->hw_led_mode << - SHARED_HW_CFG_LED_MODE_SHIFT) - == - SHARED_HW_CFG_LED_EXTPHY2) - ? (SHARED_HW_CFG_LED_PHY1 >> - SHARED_HW_CFG_LED_MODE_SHIFT) : hw_led_mode; + SHARED_HW_CFG_LED_MODE_SHIFT) == + SHARED_HW_CFG_LED_EXTPHY2) ? + (SHARED_HW_CFG_LED_PHY1 >> + SHARED_HW_CFG_LED_MODE_SHIFT) : hw_led_mode; REG_WR(sc, NIG_REG_LED_MODE_P0 + port * 4, nig_led_mode); } @@ -5977,26 +7329,133 @@ elink_status_t elink_set_led(struct elink_params *params, else REG_WR(sc, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port * 4, LED_BLINK_RATE_VAL_E1X_E2); - REG_WR(sc, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 + port * 4, 1); + REG_WR(sc, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 + + port * 4, 1); tmp = elink_cb_reg_read(sc, emac_base + EMAC_REG_EMAC_LED); elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_LED, - (tmp & (~EMAC_LED_OVERRIDE))); + (tmp & (~EMAC_LED_OVERRIDE))); + if (CHIP_IS_E1(sc) && + ((speed == ELINK_SPEED_2500) || + (speed == ELINK_SPEED_1000) || + (speed == ELINK_SPEED_100) || + (speed == ELINK_SPEED_10))) { + /* For speeds less than 10G LED scheme is different */ + REG_WR(sc, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + + port * 4, 1); + REG_WR(sc, NIG_REG_LED_CONTROL_TRAFFIC_P0 + + port * 4, 0); + REG_WR(sc, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 + + port * 4, 1); + } break; default: rc = ELINK_STATUS_ERROR; - PMD_DRV_LOG(DEBUG, "elink_set_led: Invalid led mode %d", mode); + ELINK_DEBUG_P1(sc, "elink_set_led: Invalid led mode %d", + mode); break; } return rc; } +/* This function comes to reflect the actual link state read DIRECTLY from the + * HW + */ +elink_status_t elink_test_link(struct elink_params *params, + __rte_unused struct elink_vars *vars, + uint8_t is_serdes) +{ + struct bnx2x_softc *sc = params->sc; + uint16_t gp_status = 0, phy_index = 0; + uint8_t ext_phy_link_up = 0, serdes_phy_type; + struct elink_vars temp_vars; + struct elink_phy *int_phy = ¶ms->phy[ELINK_INT_PHY]; +#ifdef ELINK_INCLUDE_FPGA + if (CHIP_REV_IS_FPGA(sc)) + return ELINK_STATUS_OK; +#endif +#ifdef ELINK_INCLUDE_EMUL + if (CHIP_REV_IS_EMUL(sc)) + return ELINK_STATUS_OK; +#endif + + if (CHIP_IS_E3(sc)) { + uint16_t link_up; + if (params->req_line_speed[ELINK_LINK_CONFIG_IDX(ELINK_INT_PHY)] + > ELINK_SPEED_10000) { + /* Check 20G link */ + elink_cl45_read(sc, int_phy, MDIO_WC_DEVAD, + 1, &link_up); + elink_cl45_read(sc, int_phy, MDIO_WC_DEVAD, + 1, &link_up); + link_up &= (1 << 2); + } else { + /* Check 10G link and below*/ + uint8_t lane = elink_get_warpcore_lane(int_phy, params); + elink_cl45_read(sc, int_phy, MDIO_WC_DEVAD, + MDIO_WC_REG_GP2_STATUS_GP_2_1, + &gp_status); + gp_status = ((gp_status >> 8) & 0xf) | + ((gp_status >> 12) & 0xf); + link_up = gp_status & (1 << lane); + } + if (!link_up) + return ELINK_STATUS_NO_LINK; + } else { + CL22_RD_OVER_CL45(sc, int_phy, + MDIO_REG_BANK_GP_STATUS, + MDIO_GP_STATUS_TOP_AN_STATUS1, + &gp_status); + /* Link is up only if both local phy and external phy are up */ + if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)) + return ELINK_STATUS_NO_LINK; + } + /* In XGXS loopback mode, do not check external PHY */ + if (params->loopback_mode == ELINK_LOOPBACK_XGXS) + return ELINK_STATUS_OK; + + switch (params->num_phys) { + case 1: + /* No external PHY */ + return ELINK_STATUS_OK; + case 2: + ext_phy_link_up = params->phy[ELINK_EXT_PHY1].read_status( + ¶ms->phy[ELINK_EXT_PHY1], + params, &temp_vars); + break; + case 3: /* Dual Media */ + for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys; + phy_index++) { + serdes_phy_type = ((params->phy[phy_index].media_type == + ELINK_ETH_PHY_SFPP_10G_FIBER) || + (params->phy[phy_index].media_type == + ELINK_ETH_PHY_SFP_1G_FIBER) || + (params->phy[phy_index].media_type == + ELINK_ETH_PHY_XFP_FIBER) || + (params->phy[phy_index].media_type == + ELINK_ETH_PHY_DA_TWINAX)); + + if (is_serdes != serdes_phy_type) + continue; + if (params->phy[phy_index].read_status) { + ext_phy_link_up |= + params->phy[phy_index].read_status( + ¶ms->phy[phy_index], + params, &temp_vars); + } + } + break; + } + if (ext_phy_link_up) + return ELINK_STATUS_OK; + return ELINK_STATUS_NO_LINK; +} + static elink_status_t elink_link_initialize(struct elink_params *params, - struct elink_vars *vars) + struct elink_vars *vars) { - elink_status_t rc = ELINK_STATUS_OK; uint8_t phy_index, non_ext_phy; struct bnx2x_softc *sc = params->sc; /* In case of external phy existence, the line speed would be the @@ -6021,11 +7480,12 @@ static elink_status_t elink_link_initialize(struct elink_params *params, (params->loopback_mode == ELINK_LOOPBACK_EXT_PHY)) { struct elink_phy *phy = ¶ms->phy[ELINK_INT_PHY]; if (vars->line_speed == ELINK_SPEED_AUTO_NEG && - (CHIP_IS_E1x(sc) || CHIP_IS_E2(sc))) + (CHIP_IS_E1x(sc) || + CHIP_IS_E2(sc))) elink_set_parallel_detection(phy, params); if (params->phy[ELINK_INT_PHY].config_init) - params->phy[ELINK_INT_PHY].config_init(phy, - params, vars); + params->phy[ELINK_INT_PHY].config_init(phy, params, + vars); } /* Re-read this value in case it was changed inside config_init due to @@ -6033,14 +7493,14 @@ static elink_status_t elink_link_initialize(struct elink_params *params, */ vars->line_speed = params->phy[ELINK_INT_PHY].req_line_speed; - /* Init external phy */ + /* Init external phy*/ if (non_ext_phy) { if (params->phy[ELINK_INT_PHY].supported & ELINK_SUPPORTED_FIBRE) vars->link_status |= LINK_STATUS_SERDES_LINK; } else { for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys; - phy_index++) { + phy_index++) { /* No need to initialize second phy in case of first * phy only selection. In case of second phy, we do * need to initialize the first phy, since they are @@ -6053,13 +7513,13 @@ static elink_status_t elink_link_initialize(struct elink_params *params, if (phy_index == ELINK_EXT_PHY2 && (elink_phy_selection(params) == PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) { - PMD_DRV_LOG(DEBUG, - "Not initializing second phy"); + ELINK_DEBUG_P0(sc, + "Not initializing second phy"); continue; } - params->phy[phy_index].config_init(¶ms-> - phy[phy_index], - params, vars); + params->phy[phy_index].config_init( + ¶ms->phy[phy_index], + params, vars); } } /* Reset the interrupt indication after phy was initialized */ @@ -6069,7 +7529,7 @@ static elink_status_t elink_link_initialize(struct elink_params *params, ELINK_NIG_STATUS_XGXS0_LINK_STATUS | ELINK_NIG_STATUS_SERDES0_LINK_STATUS | ELINK_NIG_MASK_MI_INT)); - return rc; + return ELINK_STATUS_OK; } static void elink_int_link_reset(__rte_unused struct elink_phy *phy, @@ -6091,19 +7551,21 @@ static void elink_common_ext_link_reset(__rte_unused struct elink_phy *phy, else gpio_port = params->port; elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1, - MISC_REGISTERS_GPIO_OUTPUT_LOW, gpio_port); + MISC_REGISTERS_GPIO_OUTPUT_LOW, + gpio_port); elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2, - MISC_REGISTERS_GPIO_OUTPUT_LOW, gpio_port); - PMD_DRV_LOG(DEBUG, "reset external PHY"); + MISC_REGISTERS_GPIO_OUTPUT_LOW, + gpio_port); + ELINK_DEBUG_P0(sc, "reset external PHY"); } static elink_status_t elink_update_link_down(struct elink_params *params, - struct elink_vars *vars) + struct elink_vars *vars) { struct bnx2x_softc *sc = params->sc; uint8_t port = params->port; - PMD_DRV_LOG(DEBUG, "Port %x: Link is down", port); + ELINK_DEBUG_P1(sc, "Port %x: Link is down", port); elink_set_led(params, vars, ELINK_LED_MODE_OFF, 0); vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG; /* Indicate no mac active */ @@ -6123,8 +7585,9 @@ static elink_status_t elink_update_link_down(struct elink_params *params, DELAY(1000 * 10); /* Reset BigMac/Xmac */ - if (CHIP_IS_E1x(sc) || CHIP_IS_E2(sc)) - elink_set_bmac_rx(sc, params->port, 0); + if (CHIP_IS_E1x(sc) || + CHIP_IS_E2(sc)) + elink_set_bmac_rx(sc, params->chip_id, params->port, 0); if (CHIP_IS_E3(sc)) { /* Prevent LPI Generation by chip */ @@ -6144,8 +7607,8 @@ static elink_status_t elink_update_link_down(struct elink_params *params, } static elink_status_t elink_update_link_up(struct elink_params *params, - struct elink_vars *vars, - uint8_t link_10g) + struct elink_vars *vars, + uint8_t link_10g) { struct bnx2x_softc *sc = params->sc; uint8_t phy_idx, port = params->port; @@ -6156,15 +7619,17 @@ static elink_status_t elink_update_link_up(struct elink_params *params, vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG; if (vars->flow_ctrl & ELINK_FLOW_CTRL_TX) - vars->link_status |= LINK_STATUS_TX_FLOW_CONTROL_ENABLED; + vars->link_status |= + LINK_STATUS_TX_FLOW_CONTROL_ENABLED; if (vars->flow_ctrl & ELINK_FLOW_CTRL_RX) - vars->link_status |= LINK_STATUS_RX_FLOW_CONTROL_ENABLED; + vars->link_status |= + LINK_STATUS_RX_FLOW_CONTROL_ENABLED; if (USES_WARPCORE(sc)) { if (link_10g) { if (elink_xmac_enable(params, vars, 0) == ELINK_STATUS_NO_LINK) { - PMD_DRV_LOG(DEBUG, "Found errors on XMAC"); + ELINK_DEBUG_P0(sc, "Found errors on XMAC"); vars->link_up = 0; vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG; vars->link_status &= ~LINK_STATUS_LINK_UP; @@ -6176,7 +7641,7 @@ static elink_status_t elink_update_link_up(struct elink_params *params, if ((vars->eee_status & SHMEM_EEE_ACTIVE_BIT) && (vars->eee_status & SHMEM_EEE_LPI_REQUESTED_BIT)) { - PMD_DRV_LOG(DEBUG, "Enabling LPI assertion"); + ELINK_DEBUG_P0(sc, "Enabling LPI assertion"); REG_WR(sc, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 1); REG_WR(sc, MISC_REG_CPMU_LP_DR_ENABLE, 1); @@ -6184,11 +7649,12 @@ static elink_status_t elink_update_link_up(struct elink_params *params, (params->port << 2), 0xfc20); } } - if ((CHIP_IS_E1x(sc) || CHIP_IS_E2(sc))) { + if ((CHIP_IS_E1x(sc) || + CHIP_IS_E2(sc))) { if (link_10g) { if (elink_bmac_enable(params, vars, 0, 1) == ELINK_STATUS_NO_LINK) { - PMD_DRV_LOG(DEBUG, "Found errors on BMAC"); + ELINK_DEBUG_P0(sc, "Found errors on BMAC"); vars->link_up = 0; vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG; vars->link_status &= ~LINK_STATUS_LINK_UP; @@ -6231,6 +7697,24 @@ static elink_status_t elink_update_link_up(struct elink_params *params, return rc; } +static void elink_chng_link_count(struct elink_params *params, uint8_t clear) +{ + struct bnx2x_softc *sc = params->sc; + uint32_t addr, val; + + /* Verify the link_change_count is supported by the MFW */ + if (!(SHMEM2_HAS(sc, link_change_count))) + return; + + addr = params->shmem2_base + + offsetof(struct shmem2_region, link_change_count[params->port]); + if (clear) + val = 0; + else + val = REG_RD(sc, addr) + 1; + REG_WR(sc, addr, val); +} + /* The elink_link_update function should be called upon link * interrupt. * Link is considered up as follows: @@ -6243,24 +7727,24 @@ static elink_status_t elink_update_link_up(struct elink_params *params, * external phy needs to be up, and at least one of the 2 * external phy link must be up. */ -elink_status_t elink_link_update(struct elink_params * params, - struct elink_vars * vars) +elink_status_t elink_link_update(struct elink_params *params, + struct elink_vars *vars) { struct bnx2x_softc *sc = params->sc; struct elink_vars phy_vars[ELINK_MAX_PHYS]; uint8_t port = params->port; uint8_t link_10g_plus, phy_index; + uint32_t prev_link_status = vars->link_status; uint8_t ext_phy_link_up = 0, cur_link_up; elink_status_t rc = ELINK_STATUS_OK; - __rte_unused uint8_t is_mi_int = 0; uint16_t ext_phy_line_speed = 0, prev_line_speed = vars->line_speed; uint8_t active_external_phy = ELINK_INT_PHY; vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG; vars->link_status &= ~ELINK_LINK_UPDATE_MASK; for (phy_index = ELINK_INT_PHY; phy_index < params->num_phys; - phy_index++) { + phy_index++) { phy_vars[phy_index].flow_ctrl = 0; - phy_vars[phy_index].link_status = ETH_LINK_DOWN; + phy_vars[phy_index].link_status = 0; phy_vars[phy_index].line_speed = 0; phy_vars[phy_index].duplex = DUPLEX_FULL; phy_vars[phy_index].phy_link_up = 0; @@ -6273,21 +7757,18 @@ elink_status_t elink_link_update(struct elink_params * params, if (USES_WARPCORE(sc)) elink_set_aer_mmd(params, ¶ms->phy[ELINK_INT_PHY]); - PMD_DRV_LOG(DEBUG, "port %x, XGXS?%x, int_status 0x%x", - port, (vars->phy_flags & PHY_XGXS_FLAG), - REG_RD(sc, NIG_REG_STATUS_INTERRUPT_PORT0 + port * 4)); + ELINK_DEBUG_P3(sc, "port %x, XGXS?%x, int_status 0x%x", + port, (vars->phy_flags & PHY_XGXS_FLAG), + REG_RD(sc, NIG_REG_STATUS_INTERRUPT_PORT0 + port * 4)); - is_mi_int = (uint8_t) (REG_RD(sc, NIG_REG_EMAC0_STATUS_MISC_MI_INT + - port * 0x18) > 0); - PMD_DRV_LOG(DEBUG, "int_mask 0x%x MI_INT %x, SERDES_LINK %x", - REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4), - is_mi_int, - REG_RD(sc, - NIG_REG_SERDES0_STATUS_LINK_STATUS + port * 0x3c)); + ELINK_DEBUG_P3(sc, "int_mask 0x%x MI_INT %x, SERDES_LINK %x", + REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4), + REG_RD(sc, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port * 0x18) > 0, + REG_RD(sc, NIG_REG_SERDES0_STATUS_LINK_STATUS + port * 0x3c)); - PMD_DRV_LOG(DEBUG, " 10G %x, XGXS_LINK %x", - REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK10G + port * 0x68), - REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK_STATUS + port * 0x68)); + ELINK_DEBUG_P2(sc, " 10G %x, XGXS_LINK %x", + REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK10G + port * 0x68), + REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK_STATUS + port * 0x68)); /* Disable emac */ if (!CHIP_IS_E3(sc)) @@ -6301,7 +7782,7 @@ elink_status_t elink_link_update(struct elink_params * params, * speed/duplex result */ for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys; - phy_index++) { + phy_index++) { struct elink_phy *phy = ¶ms->phy[phy_index]; if (!phy->read_status) continue; @@ -6309,11 +7790,11 @@ elink_status_t elink_link_update(struct elink_params * params, cur_link_up = phy->read_status(phy, params, &phy_vars[phy_index]); if (cur_link_up) { - PMD_DRV_LOG(DEBUG, "phy in index %d link is up", - phy_index); + ELINK_DEBUG_P1(sc, "phy in index %d link is up", + phy_index); } else { - PMD_DRV_LOG(DEBUG, "phy in index %d link is down", - phy_index); + ELINK_DEBUG_P1(sc, "phy in index %d link is down", + phy_index); continue; } @@ -6324,30 +7805,30 @@ elink_status_t elink_link_update(struct elink_params * params, switch (elink_phy_selection(params)) { case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT: case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY: - /* In this option, the first PHY makes sure to pass the - * traffic through itself only. - * Its not clear how to reset the link on the second phy - */ + /* In this option, the first PHY makes sure to pass the + * traffic through itself only. + * Its not clear how to reset the link on the second phy + */ active_external_phy = ELINK_EXT_PHY1; break; case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY: - /* In this option, the first PHY makes sure to pass the - * traffic through the second PHY. - */ + /* In this option, the first PHY makes sure to pass the + * traffic through the second PHY. + */ active_external_phy = ELINK_EXT_PHY2; break; default: - /* Link indication on both PHYs with the following cases - * is invalid: - * - FIRST_PHY means that second phy wasn't initialized, - * hence its link is expected to be down - * - SECOND_PHY means that first phy should not be able - * to link up by itself (using configuration) - * - DEFAULT should be overridden during initialization - */ - PMD_DRV_LOG(DEBUG, "Invalid link indication" - "mpc=0x%x. DISABLING LINK !!!", - params->multi_phy_config); + /* Link indication on both PHYs with the following cases + * is invalid: + * - FIRST_PHY means that second phy wasn't initialized, + * hence its link is expected to be down + * - SECOND_PHY means that first phy should not be able + * to link up by itself (using configuration) + * - DEFAULT should be overridden during initialiazation + */ + ELINK_DEBUG_P1(sc, "Invalid link indication" + " mpc=0x%x. DISABLING LINK !!!", + params->multi_phy_config); ext_phy_link_up = 0; break; } @@ -6361,9 +7842,9 @@ elink_status_t elink_link_update(struct elink_params * params, * external phy */ if (params->phy[ELINK_INT_PHY].read_status) - params->phy[ELINK_INT_PHY].read_status(¶ms-> - phy[ELINK_INT_PHY], - params, vars); + params->phy[ELINK_INT_PHY].read_status( + ¶ms->phy[ELINK_INT_PHY], + params, vars); /* The INT_PHY flow control reside in the vars. This include the * case where the speed or flow control are not set to AUTO. * Otherwise, the active external phy flow control result is set @@ -6383,11 +7864,11 @@ elink_status_t elink_link_update(struct elink_params * params, */ if (active_external_phy == ELINK_EXT_PHY1) { if (params->phy[ELINK_EXT_PHY2].phy_specific_func) { - PMD_DRV_LOG(DEBUG, "Disabling TX on EXT_PHY2"); - params->phy[ELINK_EXT_PHY2]. - phy_specific_func(¶ms-> - phy[ELINK_EXT_PHY2], - params, ELINK_DISABLE_TX); + ELINK_DEBUG_P0(sc, + "Disabling TX on EXT_PHY2"); + params->phy[ELINK_EXT_PHY2].phy_specific_func( + ¶ms->phy[ELINK_EXT_PHY2], + params, ELINK_DISABLE_TX); } } @@ -6401,12 +7882,27 @@ elink_status_t elink_link_update(struct elink_params * params, vars->eee_status = phy_vars[active_external_phy].eee_status; - PMD_DRV_LOG(DEBUG, "Active external phy selected: %x", - active_external_phy); - } + ELINK_DEBUG_P1(sc, "Active external phy selected: %x", + active_external_phy); + } + + ELINK_DEBUG_P3(sc, "vars : phy_flags = %x, mac_type = %x, phy_link_up = %x", + vars->phy_flags, vars->mac_type, vars->phy_link_up); + ELINK_DEBUG_P3(sc, "vars : link_up = %x, line_speed = %x, duplex = %x", + vars->link_up, vars->line_speed, vars->duplex); + ELINK_DEBUG_P3(sc, "vars : flow_ctrl = %x, ieee_fc = %x, link_status = %x", + vars->flow_ctrl, vars->ieee_fc, vars->link_status); + ELINK_DEBUG_P3(sc, "vars : eee_status = %x, fault_detected = %x, check_kr2_recovery_cnt = %x", + vars->eee_status, vars->fault_detected, + vars->check_kr2_recovery_cnt); + ELINK_DEBUG_P3(sc, "vars : periodic_flags = %x, aeu_int_mask = %x, rx_tx_asic_rst = %x", + vars->periodic_flags, vars->aeu_int_mask, + vars->rx_tx_asic_rst); + ELINK_DEBUG_P2(sc, "vars : turn_to_run_wc_rt = %x, rsrv2 = %x", + vars->turn_to_run_wc_rt, vars->rsrv2); for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys; - phy_index++) { + phy_index++) { if (params->phy[phy_index].flags & ELINK_FLAGS_REARM_LATCH_SIGNAL) { elink_rearm_latch_signal(sc, port, @@ -6415,9 +7911,9 @@ elink_status_t elink_link_update(struct elink_params * params, break; } } - PMD_DRV_LOG(DEBUG, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x," - " ext_phy_line_speed = %d", vars->flow_ctrl, - vars->link_status, ext_phy_line_speed); + ELINK_DEBUG_P3(sc, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x," + " ext_phy_line_speed = %d", vars->flow_ctrl, + vars->link_status, ext_phy_line_speed); /* Upon link speed change set the NIG into drain mode. Comes to * deals with possible FIFO glitch due to clk change when speed * is decreased without link down indicator @@ -6426,15 +7922,15 @@ elink_status_t elink_link_update(struct elink_params * params, if (vars->phy_link_up) { if (!(ELINK_SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up && (ext_phy_line_speed != vars->line_speed)) { - PMD_DRV_LOG(DEBUG, "Internal link speed %d is" - " different than the external" - " link speed %d", vars->line_speed, - ext_phy_line_speed); + ELINK_DEBUG_P2(sc, "Internal link speed %d is" + " different than the external" + " link speed %d", vars->line_speed, + ext_phy_line_speed); vars->phy_link_up = 0; + ELINK_DEBUG_P0(sc, "phy_link_up set to 0"); } else if (prev_line_speed != vars->line_speed) { - REG_WR(sc, - NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, - 0); + REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + + params->port * 4, 0); DELAY(1000 * 1); } } @@ -6452,11 +7948,11 @@ elink_status_t elink_link_update(struct elink_params * params, * initialize it */ if (!(ELINK_SINGLE_MEDIA_DIRECT(params))) { - PMD_DRV_LOG(DEBUG, "ext_phy_link_up = %d, int_link_up = %d," - " init_preceding = %d", ext_phy_link_up, - vars->phy_link_up, - params->phy[ELINK_EXT_PHY1].flags & - ELINK_FLAGS_INIT_XGXS_FIRST); + ELINK_DEBUG_P3(sc, "ext_phy_link_up = %d, int_link_up = %d," + " init_preceding = %d", ext_phy_link_up, + vars->phy_link_up, + params->phy[ELINK_EXT_PHY1].flags & + ELINK_FLAGS_INIT_XGXS_FIRST); if (!(params->phy[ELINK_EXT_PHY1].flags & ELINK_FLAGS_INIT_XGXS_FIRST) && ext_phy_link_up && !vars->phy_link_up) { @@ -6467,11 +7963,9 @@ elink_status_t elink_link_update(struct elink_params * params, vars->phy_flags &= ~PHY_SGMII_FLAG; if (params->phy[ELINK_INT_PHY].config_init) - params->phy[ELINK_INT_PHY].config_init(¶ms-> - phy - [ELINK_INT_PHY], - params, - vars); + params->phy[ELINK_INT_PHY].config_init( + ¶ms->phy[ELINK_INT_PHY], params, + vars); } } /* Link is up only if both local phy and external phy (in case of @@ -6482,6 +7976,11 @@ elink_status_t elink_link_update(struct elink_params * params, ELINK_SINGLE_MEDIA_DIRECT(params)) && (phy_vars[active_external_phy].fault_detected == 0)); + if (vars->link_up) + ELINK_DEBUG_P0(sc, "local phy and external phy are up"); + else + ELINK_DEBUG_P0(sc, "either local phy or external phy or both are down"); + /* Update the PFC configuration in case it was changed */ if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) vars->link_status |= LINK_STATUS_PFC_ENABLED; @@ -6493,9 +7992,12 @@ elink_status_t elink_link_update(struct elink_params * params, else rc = elink_update_link_down(params, vars); + if ((prev_link_status ^ vars->link_status) & LINK_STATUS_LINK_UP) + elink_chng_link_count(params, 0); + /* Update MCP link status was changed */ - if (params-> - feature_config_flags & ELINK_FEATURE_CONFIG_BC_SUPPORTS_AFEX) + if (params->feature_config_flags & + ELINK_FEATURE_CONFIG_BC_SUPPORTS_AFEX) elink_cb_fw_command(sc, DRV_MSG_CODE_LINK_STATUS_CHANGED, 0); return rc; @@ -6504,28 +8006,28 @@ elink_status_t elink_link_update(struct elink_params * params, /*****************************************************************************/ /* External Phy section */ /*****************************************************************************/ -static void elink_ext_phy_hw_reset(struct bnx2x_softc *sc, uint8_t port) +void elink_ext_phy_hw_reset(struct bnx2x_softc *sc, uint8_t port) { elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1, - MISC_REGISTERS_GPIO_OUTPUT_LOW, port); + MISC_REGISTERS_GPIO_OUTPUT_LOW, port); DELAY(1000 * 1); elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1, - MISC_REGISTERS_GPIO_OUTPUT_HIGH, port); + MISC_REGISTERS_GPIO_OUTPUT_HIGH, port); } -static void elink_save_spirom_version(struct bnx2x_softc *sc, - __rte_unused uint8_t port, +static void elink_save_spirom_version(struct bnx2x_softc *sc, uint8_t port, uint32_t spirom_ver, uint32_t ver_addr) { - PMD_DRV_LOG(DEBUG, "FW version 0x%x:0x%x for port %d", - (uint16_t) (spirom_ver >> 16), (uint16_t) spirom_ver, port); + ELINK_DEBUG_P3(sc, "FW version 0x%x:0x%x for port %d", + (uint16_t)(spirom_ver >> 16), (uint16_t)spirom_ver, port); if (ver_addr) REG_WR(sc, ver_addr, spirom_ver); } static void elink_save_bnx2x_spirom_ver(struct bnx2x_softc *sc, - struct elink_phy *phy, uint8_t port) + struct elink_phy *phy, + uint8_t port) { uint16_t fw_ver1, fw_ver2; @@ -6533,18 +8035,21 @@ static void elink_save_bnx2x_spirom_ver(struct bnx2x_softc *sc, MDIO_PMA_REG_ROM_VER1, &fw_ver1); elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER2, &fw_ver2); - elink_save_spirom_version(sc, port, - (uint32_t) (fw_ver1 << 16 | fw_ver2), + elink_save_spirom_version(sc, port, (uint32_t)(fw_ver1 << 16 | fw_ver2), phy->ver_addr); } static void elink_ext_phy_10G_an_resolve(struct bnx2x_softc *sc, - struct elink_phy *phy, - struct elink_vars *vars) + struct elink_phy *phy, + struct elink_vars *vars) { uint16_t val; - elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_STATUS, &val); - elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_STATUS, &val); + elink_cl45_read(sc, phy, + MDIO_AN_DEVAD, + MDIO_AN_REG_STATUS, &val); + elink_cl45_read(sc, phy, + MDIO_AN_DEVAD, + MDIO_AN_REG_STATUS, &val); if (val & (1 << 5)) vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; if ((val & (1 << 0)) == 0) @@ -6568,8 +8073,8 @@ static void elink_8073_resolve_fc(struct elink_phy *phy, if (elink_ext_phy_resolve_fc(phy, params, vars) && (vars->flow_ctrl == ELINK_FLOW_CTRL_NONE)) { uint16_t pause_result; - uint16_t ld_pause; /* local */ - uint16_t lp_pause; /* link partner */ + uint16_t ld_pause; /* local */ + uint16_t lp_pause; /* link partner */ elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &ld_pause); @@ -6582,31 +8087,35 @@ static void elink_8073_resolve_fc(struct elink_phy *phy, pause_result |= (lp_pause & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7; - elink_pause_resolve(vars, pause_result); - PMD_DRV_LOG(DEBUG, "Ext PHY CL37 pause result 0x%x", - pause_result); + elink_pause_resolve(phy, params, vars, pause_result); + ELINK_DEBUG_P1(sc, "Ext PHY CL37 pause result 0x%x", + pause_result); } } - static elink_status_t elink_8073_8727_external_rom_boot(struct bnx2x_softc *sc, - struct elink_phy *phy, - uint8_t port) + struct elink_phy *phy, + uint8_t port) { uint32_t count = 0; - uint16_t fw_ver1 = 0, fw_msgout; + uint16_t fw_ver1, fw_msgout; elink_status_t rc = ELINK_STATUS_OK; /* Boot port from external ROM */ /* EDC grst */ elink_cl45_write(sc, phy, - MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001); + MDIO_PMA_DEVAD, + MDIO_PMA_REG_GEN_CTRL, + 0x0001); /* Ucode reboot and rst */ elink_cl45_write(sc, phy, - MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x008c); + MDIO_PMA_DEVAD, + MDIO_PMA_REG_GEN_CTRL, + 0x008c); elink_cl45_write(sc, phy, - MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL1, 0x0001); + MDIO_PMA_DEVAD, + MDIO_PMA_REG_MISC_CTRL1, 0x0001); /* Reset internal microprocessor */ elink_cl45_write(sc, phy, @@ -6627,10 +8136,10 @@ static elink_status_t elink_8073_8727_external_rom_boot(struct bnx2x_softc *sc, do { count++; if (count > 300) { - PMD_DRV_LOG(DEBUG, - "elink_8073_8727_external_rom_boot port %x:" - "Download failed. fw version = 0x%x", - port, fw_ver1); + ELINK_DEBUG_P2(sc, + "elink_8073_8727_external_rom_boot port %x:" + "Download failed. fw version = 0x%x", + port, fw_ver1); rc = ELINK_STATUS_ERROR; break; } @@ -6644,17 +8153,19 @@ static elink_status_t elink_8073_8727_external_rom_boot(struct bnx2x_softc *sc, DELAY(1000 * 1); } while (fw_ver1 == 0 || fw_ver1 == 0x4321 || - ((fw_msgout & 0xff) != 0x03 && (phy->type == - PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8073))); + ((fw_msgout & 0xff) != 0x03 && (phy->type == + PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8073))); /* Clear ser_boot_ctl bit */ elink_cl45_write(sc, phy, - MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL1, 0x0000); + MDIO_PMA_DEVAD, + MDIO_PMA_REG_MISC_CTRL1, 0x0000); elink_save_bnx2x_spirom_ver(sc, phy, port); - PMD_DRV_LOG(DEBUG, - "elink_8073_8727_external_rom_boot port %x:" - "Download complete. fw version = 0x%x", port, fw_ver1); + ELINK_DEBUG_P2(sc, + "elink_8073_8727_external_rom_boot port %x:" + "Download complete. fw version = 0x%x", + port, fw_ver1); return rc; } @@ -6668,22 +8179,25 @@ static elink_status_t elink_8073_is_snr_needed(struct bnx2x_softc *sc, /* This is only required for 8073A1, version 102 only */ uint16_t val; - /* Read 8073 HW revision */ + /* Read 8073 HW revision*/ elink_cl45_read(sc, phy, - MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV, &val); + MDIO_PMA_DEVAD, + MDIO_PMA_REG_8073_CHIP_REV, &val); if (val != 1) { /* No need to workaround in 8073 A1 */ return ELINK_STATUS_OK; } - elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER2, &val); + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_ROM_VER2, &val); /* SNR should be applied only for version 0x102 */ if (val != 0x102) return ELINK_STATUS_OK; - return ELINK_STATUS_ERROR; + return 1; } static elink_status_t elink_8073_xaui_wa(struct bnx2x_softc *sc, @@ -6692,7 +8206,8 @@ static elink_status_t elink_8073_xaui_wa(struct bnx2x_softc *sc, uint16_t val, cnt, cnt1; elink_cl45_read(sc, phy, - MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV, &val); + MDIO_PMA_DEVAD, + MDIO_PMA_REG_8073_CHIP_REV, &val); if (val > 0) { /* No need to workaround in 8073 A1 */ @@ -6707,16 +8222,17 @@ static elink_status_t elink_8073_xaui_wa(struct bnx2x_softc *sc, for (cnt = 0; cnt < 1000; cnt++) { elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, - MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &val); - /* If bit [14] = 0 or bit [13] = 0, continue on with - * system initialization (XAUI work-around not required, as - * these bits indicate 2.5G or 1G link up). - */ + MDIO_PMA_REG_8073_SPEED_LINK_STATUS, + &val); + /* If bit [14] = 0 or bit [13] = 0, continue on with + * system initialization (XAUI work-around not required, as + * these bits indicate 2.5G or 1G link up). + */ if (!(val & (1 << 14)) || !(val & (1 << 13))) { - PMD_DRV_LOG(DEBUG, "XAUI work-around not required"); + ELINK_DEBUG_P0(sc, "XAUI work-around not required"); return ELINK_STATUS_OK; } else if (!(val & (1 << 15))) { - PMD_DRV_LOG(DEBUG, "bit 15 went off"); + ELINK_DEBUG_P0(sc, "bit 15 went off"); /* If bit 15 is 0, then poll Dev1, Reg $C841 until it's * MSB (bit15) goes to 1 (indicating that the XAUI * workaround has completed), then continue on with @@ -6724,12 +8240,11 @@ static elink_status_t elink_8073_xaui_wa(struct bnx2x_softc *sc, */ for (cnt1 = 0; cnt1 < 1000; cnt1++) { elink_cl45_read(sc, phy, - MDIO_PMA_DEVAD, - MDIO_PMA_REG_8073_XAUI_WA, - &val); + MDIO_PMA_DEVAD, + MDIO_PMA_REG_8073_XAUI_WA, &val); if (val & (1 << 15)) { - PMD_DRV_LOG(DEBUG, - "XAUI workaround has completed"); + ELINK_DEBUG_P0(sc, + "XAUI workaround has completed"); return ELINK_STATUS_OK; } DELAY(1000 * 3); @@ -6738,19 +8253,21 @@ static elink_status_t elink_8073_xaui_wa(struct bnx2x_softc *sc, } DELAY(1000 * 3); } - PMD_DRV_LOG(DEBUG, "Warning: XAUI work-around timeout !!!"); + ELINK_DEBUG_P0(sc, "Warning: XAUI work-around timeout !!!"); return ELINK_STATUS_ERROR; } static void elink_807x_force_10G(struct bnx2x_softc *sc, struct elink_phy *phy) { /* Force KR or KX */ - elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040); + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040); elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b); elink_cl45_write(sc, phy, - MDIO_PMA_DEVAD, MDIO_PMA_REG_BNX2X_CTRL, 0x0000); - elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000); + MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000); + elink_cl45_write(sc, phy, + MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000); } static void elink_8073_set_pause_cl37(struct elink_params *params, @@ -6766,21 +8283,22 @@ static void elink_8073_set_pause_cl37(struct elink_params *params, /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); if ((vars->ieee_fc & - MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) == + MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) == MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) { - cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC; + cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC; } if ((vars->ieee_fc & - MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) == + MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) == MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) { - cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; + cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; } if ((vars->ieee_fc & - MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) == + MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) == MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) { cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; } - PMD_DRV_LOG(DEBUG, "Ext phy AN advertize cl37 0x%x", cl37_val); + ELINK_DEBUG_P1(sc, + "Ext phy AN advertize cl37 0x%x", cl37_val); elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val); @@ -6798,31 +8316,31 @@ static void elink_8073_specific_func(struct elink_phy *phy, elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, (1 << 2)); - elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, - 0x0004); + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0004); break; } } static uint8_t elink_8073_config_init(struct elink_phy *phy, - struct elink_params *params, - struct elink_vars *vars) + struct elink_params *params, + struct elink_vars *vars) { struct bnx2x_softc *sc = params->sc; uint16_t val = 0, tmp1; uint8_t gpio_port; - PMD_DRV_LOG(DEBUG, "Init 8073"); + ELINK_DEBUG_P0(sc, "Init 8073"); if (CHIP_IS_E2(sc)) gpio_port = SC_PATH(sc); else gpio_port = params->port; - /* Restore normal power mode */ + /* Restore normal power mode*/ elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2, - MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port); + MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port); elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1, - MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port); + MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port); elink_8073_specific_func(phy, params, ELINK_PHY_INIT); elink_8073_set_pause_cl37(params, phy, vars); @@ -6830,14 +8348,15 @@ static uint8_t elink_8073_config_init(struct elink_phy *phy, elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1); - elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1); + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1); - PMD_DRV_LOG(DEBUG, "Before rom RX_ALARM(port1): 0x%x", tmp1); + ELINK_DEBUG_P1(sc, "Before rom RX_ALARM(port1): 0x%x", tmp1); /* Swap polarity if required - Must be done only in non-1G mode */ if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) { /* Configure the 8073 to swap _P and _N of the KR lines */ - PMD_DRV_LOG(DEBUG, "Swapping polarity for the 8073"); + ELINK_DEBUG_P0(sc, "Swapping polarity for the 8073"); /* 10G Rx/Tx and 1G Tx signal polarity swap */ elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, @@ -6848,31 +8367,33 @@ static uint8_t elink_8073_config_init(struct elink_phy *phy, (val | (3 << 9))); } + /* Enable CL37 BAM */ if (REG_RD(sc, params->shmem_base + - offsetof(struct shmem_region, - dev_info.port_hw_config[params->port]. - default_cfg)) & + offsetof(struct shmem_region, dev_info. + port_hw_config[params->port].default_cfg)) & PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) { elink_cl45_read(sc, phy, - MDIO_AN_DEVAD, MDIO_AN_REG_8073_BAM, &val); + MDIO_AN_DEVAD, + MDIO_AN_REG_8073_BAM, &val); elink_cl45_write(sc, phy, - MDIO_AN_DEVAD, MDIO_AN_REG_8073_BAM, val | 1); - PMD_DRV_LOG(DEBUG, "Enable CL37 BAM on KR"); + MDIO_AN_DEVAD, + MDIO_AN_REG_8073_BAM, val | 1); + ELINK_DEBUG_P0(sc, "Enable CL37 BAM on KR"); } if (params->loopback_mode == ELINK_LOOPBACK_EXT) { elink_807x_force_10G(sc, phy); - PMD_DRV_LOG(DEBUG, "Forced speed 10G on 807X"); + ELINK_DEBUG_P0(sc, "Forced speed 10G on 807X"); return ELINK_STATUS_OK; } else { elink_cl45_write(sc, phy, - MDIO_PMA_DEVAD, MDIO_PMA_REG_BNX2X_CTRL, 0x0002); + MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002); } if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG) { if (phy->req_line_speed == ELINK_SPEED_10000) { val = (1 << 7); - } else if (phy->req_line_speed == ELINK_SPEED_2500) { + } else if (phy->req_line_speed == ELINK_SPEED_2500) { val = (1 << 5); /* Note that 2.5G works only when used with 1G * advertisement @@ -6881,15 +8402,16 @@ static uint8_t elink_8073_config_init(struct elink_phy *phy, val = (1 << 5); } else { val = 0; - if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) + if (phy->speed_cap_mask & + PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) val |= (1 << 7); /* Note that 2.5G works only when used with 1G advertisement */ if (phy->speed_cap_mask & - (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G | - PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) + (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G | + PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) val |= (1 << 5); - PMD_DRV_LOG(DEBUG, "807x autoneg val = 0x%x", val); + ELINK_DEBUG_P1(sc, "807x autoneg val = 0x%x", val); } elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val); @@ -6903,13 +8425,13 @@ static uint8_t elink_8073_config_init(struct elink_phy *phy, elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV, &phy_ver); - PMD_DRV_LOG(DEBUG, "Add 2.5G"); + ELINK_DEBUG_P0(sc, "Add 2.5G"); if (phy_ver > 0) tmp1 |= 1; else tmp1 &= 0xfffe; } else { - PMD_DRV_LOG(DEBUG, "Disable 2.5G"); + ELINK_DEBUG_P0(sc, "Disable 2.5G"); tmp1 &= 0xfffe; } @@ -6943,14 +8465,14 @@ static uint8_t elink_8073_config_init(struct elink_phy *phy, /* Restart autoneg */ DELAY(1000 * 500); elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); - PMD_DRV_LOG(DEBUG, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x", - ((val & (1 << 5)) > 0), ((val & (1 << 7)) > 0)); + ELINK_DEBUG_P2(sc, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x", + ((val & (1 << 5)) > 0), ((val & (1 << 7)) > 0)); return ELINK_STATUS_OK; } static uint8_t elink_8073_read_status(struct elink_phy *phy, - struct elink_params *params, - struct elink_vars *vars) + struct elink_params *params, + struct elink_vars *vars) { struct bnx2x_softc *sc = params->sc; uint8_t link_up = 0; @@ -6958,33 +8480,41 @@ static uint8_t elink_8073_read_status(struct elink_phy *phy, uint16_t link_status = 0; uint16_t an1000_status = 0; - elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); - PMD_DRV_LOG(DEBUG, "8703 LASI status 0x%x", val1); + ELINK_DEBUG_P1(sc, "8703 LASI status 0x%x", val1); /* Clear the interrupt LASI status register */ - elink_cl45_read(sc, phy, MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2); - elink_cl45_read(sc, phy, MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1); - PMD_DRV_LOG(DEBUG, "807x PCS status 0x%x->0x%x", val2, val1); + elink_cl45_read(sc, phy, + MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2); + elink_cl45_read(sc, phy, + MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1); + ELINK_DEBUG_P2(sc, "807x PCS status 0x%x->0x%x", val2, val1); /* Clear MSG-OUT */ elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1); /* Check the LASI */ - elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2); + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2); - PMD_DRV_LOG(DEBUG, "KR 0x9003 0x%x", val2); + ELINK_DEBUG_P1(sc, "KR 0x9003 0x%x", val2); /* Check the link status */ - elink_cl45_read(sc, phy, MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2); - PMD_DRV_LOG(DEBUG, "KR PCS status 0x%x", val2); + elink_cl45_read(sc, phy, + MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2); + ELINK_DEBUG_P1(sc, "KR PCS status 0x%x", val2); - elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2); - elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1); + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2); + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1); link_up = ((val1 & 4) == 4); - PMD_DRV_LOG(DEBUG, "PMA_REG_STATUS=0x%x", val1); + ELINK_DEBUG_P1(sc, "PMA_REG_STATUS=0x%x", val1); - if (link_up && ((phy->req_line_speed != ELINK_SPEED_10000))) { + if (link_up && + ((phy->req_line_speed != ELINK_SPEED_10000))) { if (elink_8073_xaui_wa(sc, phy) != 0) return 0; } @@ -6994,10 +8524,12 @@ static uint8_t elink_8073_read_status(struct elink_phy *phy, MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status); /* Check the link status on 1.1.2 */ - elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2); - elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1); - PMD_DRV_LOG(DEBUG, "KR PMA status 0x%x->0x%x," - "an_link_status=0x%x", val2, val1, an1000_status); + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2); + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1); + ELINK_DEBUG_P3(sc, "KR PMA status 0x%x->0x%x," + "an_link_status=0x%x", val2, val1, an1000_status); link_up = (((val1 & 4) == 4) || (an1000_status & (1 << 1))); if (link_up && elink_8073_is_snr_needed(sc, phy)) { @@ -7022,27 +8554,28 @@ static uint8_t elink_8073_read_status(struct elink_phy *phy, if ((link_status & (1 << 2)) && (!(link_status & (1 << 15)))) { link_up = 1; vars->line_speed = ELINK_SPEED_10000; - PMD_DRV_LOG(DEBUG, "port %x: External link up in 10G", - params->port); + ELINK_DEBUG_P1(sc, "port %x: External link up in 10G", + params->port); } else if ((link_status & (1 << 1)) && (!(link_status & (1 << 14)))) { link_up = 1; vars->line_speed = ELINK_SPEED_2500; - PMD_DRV_LOG(DEBUG, "port %x: External link up in 2.5G", - params->port); + ELINK_DEBUG_P1(sc, "port %x: External link up in 2.5G", + params->port); } else if ((link_status & (1 << 0)) && (!(link_status & (1 << 13)))) { link_up = 1; vars->line_speed = ELINK_SPEED_1000; - PMD_DRV_LOG(DEBUG, "port %x: External link up in 1G", - params->port); + ELINK_DEBUG_P1(sc, "port %x: External link up in 1G", + params->port); } else { link_up = 0; - PMD_DRV_LOG(DEBUG, "port %x: External link is down", - params->port); + ELINK_DEBUG_P1(sc, "port %x: External link is down", + params->port); } if (link_up) { /* Swap polarity if required */ - if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) { + if (params->lane_config & + PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) { /* Configure the 8073 to swap P and N of the KR lines */ elink_cl45_read(sc, phy, MDIO_XS_DEVAD, @@ -7051,15 +8584,16 @@ static uint8_t elink_8073_read_status(struct elink_phy *phy, * when it`s in 10G mode. */ if (vars->line_speed == ELINK_SPEED_1000) { - PMD_DRV_LOG(DEBUG, "Swapping 1G polarity for" - "the 8073"); + ELINK_DEBUG_P0(sc, "Swapping 1G polarity for" + " the 8073"); val1 |= (1 << 3); } else val1 &= ~(1 << 3); elink_cl45_write(sc, phy, MDIO_XS_DEVAD, - MDIO_XS_REG_8073_RX_CTRL_PCIE, val1); + MDIO_XS_REG_8073_RX_CTRL_PCIE, + val1); } elink_ext_phy_10G_an_resolve(sc, phy, vars); elink_8073_resolve_fc(phy, params, vars); @@ -7072,10 +8606,10 @@ static uint8_t elink_8073_read_status(struct elink_phy *phy, if (val1 & (1 << 5)) vars->link_status |= - LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; + LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; if (val1 & (1 << 7)) vars->link_status |= - LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; + LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; } return link_up; @@ -7090,25 +8624,25 @@ static void elink_8073_link_reset(__rte_unused struct elink_phy *phy, gpio_port = SC_PATH(sc); else gpio_port = params->port; - PMD_DRV_LOG(DEBUG, "Setting 8073 port %d into low power mode", - gpio_port); + ELINK_DEBUG_P1(sc, "Setting 8073 port %d into low power mode", + gpio_port); elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2, - MISC_REGISTERS_GPIO_OUTPUT_LOW, gpio_port); + MISC_REGISTERS_GPIO_OUTPUT_LOW, + gpio_port); } /******************************************************************/ /* BNX2X8705 PHY SECTION */ /******************************************************************/ static uint8_t elink_8705_config_init(struct elink_phy *phy, - struct elink_params *params, - __rte_unused struct elink_vars - *vars) + struct elink_params *params, + __rte_unused struct elink_vars *vars) { struct bnx2x_softc *sc = params->sc; - PMD_DRV_LOG(DEBUG, "init 8705"); - /* Restore normal power mode */ + ELINK_DEBUG_P0(sc, "init 8705"); + /* Restore normal power mode*/ elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2, - MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); + MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); /* HW reset */ elink_ext_phy_hw_reset(sc, params->port); elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040); @@ -7120,36 +8654,40 @@ static uint8_t elink_8705_config_init(struct elink_phy *phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf); elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100); - elink_cl45_write(sc, phy, MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1); + elink_cl45_write(sc, phy, + MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1); /* BNX2X8705 doesn't have microcode, hence the 0 */ elink_save_spirom_version(sc, params->port, params->shmem_base, 0); return ELINK_STATUS_OK; } static uint8_t elink_8705_read_status(struct elink_phy *phy, - struct elink_params *params, - struct elink_vars *vars) + struct elink_params *params, + struct elink_vars *vars) { uint8_t link_up = 0; uint16_t val1, rx_sd; struct bnx2x_softc *sc = params->sc; - PMD_DRV_LOG(DEBUG, "read status 8705"); + ELINK_DEBUG_P0(sc, "read status 8705"); elink_cl45_read(sc, phy, - MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1); - PMD_DRV_LOG(DEBUG, "8705 LASI status 0x%x", val1); + MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1); + ELINK_DEBUG_P1(sc, "8705 LASI status 0x%x", val1); elink_cl45_read(sc, phy, - MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1); - PMD_DRV_LOG(DEBUG, "8705 LASI status 0x%x", val1); + MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1); + ELINK_DEBUG_P1(sc, "8705 LASI status 0x%x", val1); - elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd); + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd); - elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xc809, &val1); - elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xc809, &val1); + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, 0xc809, &val1); + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, 0xc809, &val1); - PMD_DRV_LOG(DEBUG, "8705 1.c809 val=0x%x", val1); - link_up = ((rx_sd & 0x1) && (val1 & (1 << 9)) - && ((val1 & (1 << 8)) == 0)); + ELINK_DEBUG_P1(sc, "8705 1.c809 val=0x%x", val1); + link_up = ((rx_sd & 0x1) && (val1 & (1 << 9)) && + ((val1 & (1 << 8)) == 0)); if (link_up) { vars->line_speed = ELINK_SPEED_10000; elink_ext_phy_resolve_fc(phy, params, vars); @@ -7170,17 +8708,17 @@ static void elink_set_disable_pmd_transmit(struct elink_params *params, */ if (pmd_dis) { if (params->feature_config_flags & - ELINK_FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED) { - PMD_DRV_LOG(DEBUG, "Disabling PMD transmitter"); + ELINK_FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED) { + ELINK_DEBUG_P0(sc, "Disabling PMD transmitter"); } else { - PMD_DRV_LOG(DEBUG, "NOT disabling PMD transmitter"); + ELINK_DEBUG_P0(sc, "NOT disabling PMD transmitter"); return; } - } else { - PMD_DRV_LOG(DEBUG, "Enabling PMD transmitter"); - } + } else + ELINK_DEBUG_P0(sc, "Enabling PMD transmitter"); elink_cl45_write(sc, phy, - MDIO_PMA_DEVAD, MDIO_PMA_REG_TX_DISABLE, pmd_dis); + MDIO_PMA_DEVAD, + MDIO_PMA_REG_TX_DISABLE, pmd_dis); } static uint8_t elink_get_gpio_port(struct elink_params *params) @@ -7188,37 +8726,38 @@ static uint8_t elink_get_gpio_port(struct elink_params *params) uint8_t gpio_port; uint32_t swap_val, swap_override; struct bnx2x_softc *sc = params->sc; - if (CHIP_IS_E2(sc)) { + if (CHIP_IS_E2(sc)) gpio_port = SC_PATH(sc); - } else { + else gpio_port = params->port; - } swap_val = REG_RD(sc, NIG_REG_PORT_SWAP); swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE); return gpio_port ^ (swap_val && swap_override); } static void elink_sfp_e1e2_set_transmitter(struct elink_params *params, - struct elink_phy *phy, uint8_t tx_en) + struct elink_phy *phy, + uint8_t tx_en) { uint16_t val; uint8_t port = params->port; struct bnx2x_softc *sc = params->sc; uint32_t tx_en_mode; - /* Disable/Enable transmitter ( TX laser of the SFP+ module.) */ + /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/ tx_en_mode = REG_RD(sc, params->shmem_base + offsetof(struct shmem_region, dev_info.port_hw_config[port].sfp_ctrl)) & - PORT_HW_CFG_TX_LASER_MASK; - PMD_DRV_LOG(DEBUG, "Setting transmitter tx_en=%x for port %x " - "mode = %x", tx_en, port, tx_en_mode); + PORT_HW_CFG_TX_LASER_MASK; + ELINK_DEBUG_P3(sc, "Setting transmitter tx_en=%x for port %x " + "mode = %x", tx_en, port, tx_en_mode); switch (tx_en_mode) { case PORT_HW_CFG_TX_LASER_MDIO: elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, - MDIO_PMA_REG_PHY_IDENTIFIER, &val); + MDIO_PMA_REG_PHY_IDENTIFIER, + &val); if (tx_en) val &= ~(1 << 15); @@ -7227,36 +8766,38 @@ static void elink_sfp_e1e2_set_transmitter(struct elink_params *params, elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, - MDIO_PMA_REG_PHY_IDENTIFIER, val); - break; + MDIO_PMA_REG_PHY_IDENTIFIER, + val); + break; case PORT_HW_CFG_TX_LASER_GPIO0: case PORT_HW_CFG_TX_LASER_GPIO1: case PORT_HW_CFG_TX_LASER_GPIO2: case PORT_HW_CFG_TX_LASER_GPIO3: - { - uint16_t gpio_pin; - uint8_t gpio_port, gpio_mode; - if (tx_en) - gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH; - else - gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW; + { + uint16_t gpio_pin; + uint8_t gpio_port, gpio_mode; + if (tx_en) + gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH; + else + gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW; - gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0; - gpio_port = elink_get_gpio_port(params); - elink_cb_gpio_write(sc, gpio_pin, gpio_mode, gpio_port); - break; - } + gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0; + gpio_port = elink_get_gpio_port(params); + elink_cb_gpio_write(sc, gpio_pin, gpio_mode, gpio_port); + break; + } default: - PMD_DRV_LOG(DEBUG, "Invalid TX_LASER_MDIO 0x%x", tx_en_mode); + ELINK_DEBUG_P1(sc, "Invalid TX_LASER_MDIO 0x%x", tx_en_mode); break; } } static void elink_sfp_set_transmitter(struct elink_params *params, - struct elink_phy *phy, uint8_t tx_en) + struct elink_phy *phy, + uint8_t tx_en) { struct bnx2x_softc *sc = params->sc; - PMD_DRV_LOG(DEBUG, "Setting SFP+ transmitter to %d", tx_en); + ELINK_DEBUG_P1(sc, "Setting SFP+ transmitter to %d", tx_en); if (CHIP_IS_E3(sc)) elink_sfp_e3_set_transmitter(params, phy, tx_en); else @@ -7264,20 +8805,17 @@ static void elink_sfp_set_transmitter(struct elink_params *params, } static elink_status_t elink_8726_read_sfp_module_eeprom(struct elink_phy *phy, - struct elink_params - *params, - uint8_t dev_addr, - uint16_t addr, - uint8_t byte_cnt, - uint8_t * o_buf, - __rte_unused uint8_t - is_init) + struct elink_params *params, + uint8_t dev_addr, uint16_t addr, + uint8_t byte_cnt, + uint8_t *o_buf, __rte_unused uint8_t is_init) { struct bnx2x_softc *sc = params->sc; uint16_t val = 0; uint16_t i; if (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) { - PMD_DRV_LOG(DEBUG, "Reading from eeprom is limited to 0xf"); + ELINK_DEBUG_P0(sc, + "Reading from eeprom is limited to 0xf"); return ELINK_STATUS_ERROR; } /* Set the read command byte count */ @@ -7307,10 +8845,10 @@ static elink_status_t elink_8726_read_sfp_module_eeprom(struct elink_phy *phy, } if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) != - MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) { - PMD_DRV_LOG(DEBUG, - "Got bad status 0x%x when reading from SFP+ EEPROM", - (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK)); + MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) { + ELINK_DEBUG_P1(sc, + "Got bad status 0x%x when reading from SFP+ EEPROM", + (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK)); return ELINK_STATUS_ERROR; } @@ -7319,8 +8857,8 @@ static elink_status_t elink_8726_read_sfp_module_eeprom(struct elink_phy *phy, elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val); - o_buf[i] = - (uint8_t) (val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK); + o_buf[i] = (uint8_t) + (val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK); } for (i = 0; i < 100; i++) { @@ -7343,29 +8881,27 @@ static void elink_warpcore_power_module(struct elink_params *params, pin_cfg = (REG_RD(sc, params->shmem_base + offsetof(struct shmem_region, - dev_info.port_hw_config[params->port]. - e3_sfp_ctrl)) & PORT_HW_CFG_E3_PWR_DIS_MASK) - >> PORT_HW_CFG_E3_PWR_DIS_SHIFT; + dev_info.port_hw_config[params->port].e3_sfp_ctrl)) & + PORT_HW_CFG_E3_PWR_DIS_MASK) >> + PORT_HW_CFG_E3_PWR_DIS_SHIFT; if (pin_cfg == PIN_CFG_NA) return; - PMD_DRV_LOG(DEBUG, "Setting SFP+ module power to %d using pin cfg %d", - power, pin_cfg); + ELINK_DEBUG_P2(sc, "Setting SFP+ module power to %d using pin cfg %d", + power, pin_cfg); /* Low ==> corresponding SFP+ module is powered * high ==> the SFP+ module is powered down */ elink_set_cfg_pin(sc, pin_cfg, power ^ 1); } - -static elink_status_t elink_warpcore_read_sfp_module_eeprom(__rte_unused struct - elink_phy *phy, - struct elink_params - *params, - uint8_t dev_addr, - uint16_t addr, - uint8_t byte_cnt, - uint8_t * o_buf, - uint8_t is_init) +static elink_status_t elink_warpcore_read_sfp_module_eeprom( + __rte_unused struct elink_phy *phy, + struct elink_params *params, + uint8_t dev_addr, + uint16_t addr, + uint8_t byte_cnt, + uint8_t *o_buf, + uint8_t is_init) { elink_status_t rc = ELINK_STATUS_OK; uint8_t i, j = 0, cnt = 0; @@ -7374,8 +8910,8 @@ static elink_status_t elink_warpcore_read_sfp_module_eeprom(__rte_unused struct struct bnx2x_softc *sc = params->sc; if (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) { - PMD_DRV_LOG(DEBUG, - "Reading from eeprom is limited to 16 bytes"); + ELINK_DEBUG_P0(sc, + "Reading from eeprom is limited to 16 bytes"); return ELINK_STATUS_ERROR; } @@ -7388,13 +8924,15 @@ static elink_status_t elink_warpcore_read_sfp_module_eeprom(__rte_unused struct DELAY(1000 * 1); elink_warpcore_power_module(params, 1); } - rc = elink_bsc_read(params, sc, dev_addr, addr32, 0, byte_cnt, + + elink_bsc_module_sel(params); + rc = elink_bsc_read(sc, dev_addr, addr32, 0, byte_cnt, data_array); } while ((rc != ELINK_STATUS_OK) && (++cnt < I2C_WA_RETRY_CNT)); if (rc == ELINK_STATUS_OK) { for (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) { - o_buf[j] = *((uint8_t *) data_array + i); + o_buf[j] = *((uint8_t *)data_array + i); j++; } } @@ -7403,20 +8941,18 @@ static elink_status_t elink_warpcore_read_sfp_module_eeprom(__rte_unused struct } static elink_status_t elink_8727_read_sfp_module_eeprom(struct elink_phy *phy, - struct elink_params - *params, - uint8_t dev_addr, - uint16_t addr, - uint8_t byte_cnt, - uint8_t * o_buf, - __rte_unused uint8_t - is_init) + struct elink_params *params, + uint8_t dev_addr, uint16_t addr, + uint8_t byte_cnt, + uint8_t *o_buf, + __rte_unused uint8_t is_init) { struct bnx2x_softc *sc = params->sc; uint16_t val, i; if (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) { - PMD_DRV_LOG(DEBUG, "Reading from eeprom is limited to 0xf"); + ELINK_DEBUG_P0(sc, + "Reading from eeprom is limited to 0xf"); return ELINK_STATUS_ERROR; } @@ -7431,7 +8967,9 @@ static elink_status_t elink_8727_read_sfp_module_eeprom(struct elink_phy *phy, /* Need to read from 1.8000 to clear it */ elink_cl45_read(sc, phy, - MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); + MDIO_PMA_DEVAD, + MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, + &val); /* Set the read command byte count */ elink_cl45_write(sc, phy, @@ -7442,16 +8980,19 @@ static elink_status_t elink_8727_read_sfp_module_eeprom(struct elink_phy *phy, /* Set the read command address */ elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, - MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR, addr); + MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR, + addr); /* Set the destination address */ elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, - 0x8004, MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF); + 0x8004, + MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF); /* Activate read command */ elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, - MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, 0x8002); + MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, + 0x8002); /* Wait appropriate time for two-wire command to finish before * polling the status register */ @@ -7469,10 +9010,10 @@ static elink_status_t elink_8727_read_sfp_module_eeprom(struct elink_phy *phy, } if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) != - MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) { - PMD_DRV_LOG(DEBUG, - "Got bad status 0x%x when reading from SFP+ EEPROM", - (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK)); + MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) { + ELINK_DEBUG_P1(sc, + "Got bad status 0x%x when reading from SFP+ EEPROM", + (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK)); return ELINK_STATUS_TIMEOUT; } @@ -7481,8 +9022,8 @@ static elink_status_t elink_8727_read_sfp_module_eeprom(struct elink_phy *phy, elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val); - o_buf[i] = - (uint8_t) (val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK); + o_buf[i] = (uint8_t) + (val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK); } for (i = 0; i < 100; i++) { @@ -7497,21 +9038,18 @@ static elink_status_t elink_8727_read_sfp_module_eeprom(struct elink_phy *phy, return ELINK_STATUS_ERROR; } - -static elink_status_t elink_read_sfp_module_eeprom(struct elink_phy *phy, - struct elink_params *params, - uint8_t dev_addr, - uint16_t addr, - uint16_t byte_cnt, - uint8_t * o_buf) +elink_status_t elink_read_sfp_module_eeprom(struct elink_phy *phy, + struct elink_params *params, uint8_t dev_addr, + uint16_t addr, uint16_t byte_cnt, + uint8_t *o_buf) { - elink_status_t rc = ELINK_STATUS_OK; + elink_status_t rc = 0; + struct bnx2x_softc *sc = params->sc; uint8_t xfer_size; uint8_t *user_data = o_buf; read_sfp_module_eeprom_func_p read_func; - if ((dev_addr != 0xa0) && (dev_addr != 0xa2)) { - PMD_DRV_LOG(DEBUG, "invalid dev_addr 0x%x", dev_addr); + ELINK_DEBUG_P1(sc, "invalid dev_addr 0x%x", dev_addr); return ELINK_STATUS_ERROR; } @@ -7532,7 +9070,7 @@ static elink_status_t elink_read_sfp_module_eeprom(struct elink_phy *phy, while (!rc && (byte_cnt > 0)) { xfer_size = (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) ? - ELINK_SFP_EEPROM_PAGE_SIZE : byte_cnt; + ELINK_SFP_EEPROM_PAGE_SIZE : byte_cnt; rc = read_func(phy, params, dev_addr, addr, xfer_size, user_data, 0); byte_cnt -= xfer_size; @@ -7543,91 +9081,105 @@ static elink_status_t elink_read_sfp_module_eeprom(struct elink_phy *phy, } static elink_status_t elink_get_edc_mode(struct elink_phy *phy, - struct elink_params *params, - uint16_t * edc_mode) + struct elink_params *params, + uint16_t *edc_mode) { struct bnx2x_softc *sc = params->sc; uint32_t sync_offset = 0, phy_idx, media_types; - uint8_t gport, val[2], check_limiting_mode = 0; + uint8_t val[ELINK_SFP_EEPROM_FC_TX_TECH_ADDR + 1]; + uint8_t check_limiting_mode = 0; *edc_mode = ELINK_EDC_MODE_LIMITING; phy->media_type = ELINK_ETH_PHY_UNSPECIFIED; /* First check for copper cable */ if (elink_read_sfp_module_eeprom(phy, params, ELINK_I2C_DEV_ADDR_A0, - ELINK_SFP_EEPROM_CON_TYPE_ADDR, - 2, (uint8_t *) val) != 0) { - PMD_DRV_LOG(DEBUG, "Failed to read from SFP+ module EEPROM"); + 0, + ELINK_SFP_EEPROM_FC_TX_TECH_ADDR + 1, + (uint8_t *)val) != 0) { + ELINK_DEBUG_P0(sc, "Failed to read from SFP+ module EEPROM"); return ELINK_STATUS_ERROR; } - - switch (val[0]) { + params->link_attr_sync &= ~LINK_SFP_EEPROM_COMP_CODE_MASK; + params->link_attr_sync |= val[ELINK_SFP_EEPROM_10G_COMP_CODE_ADDR] << + LINK_SFP_EEPROM_COMP_CODE_SHIFT; + elink_update_link_attr(params, params->link_attr_sync); + switch (val[ELINK_SFP_EEPROM_CON_TYPE_ADDR]) { case ELINK_SFP_EEPROM_CON_TYPE_VAL_COPPER: - { - uint8_t copper_module_type; - phy->media_type = ELINK_ETH_PHY_DA_TWINAX; - /* Check if its active cable (includes SFP+ module) - * of passive cable + { + uint8_t copper_module_type; + phy->media_type = ELINK_ETH_PHY_DA_TWINAX; + /* Check if its active cable (includes SFP+ module) + * of passive cable + */ + copper_module_type = val[ELINK_SFP_EEPROM_FC_TX_TECH_ADDR]; + if (copper_module_type & + ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) { + ELINK_DEBUG_P0(sc, "Active Copper cable detected"); + if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) + *edc_mode = ELINK_EDC_MODE_ACTIVE_DAC; + else + check_limiting_mode = 1; + } else { + *edc_mode = ELINK_EDC_MODE_PASSIVE_DAC; + /* Even in case PASSIVE_DAC indication is not set, + * treat it as a passive DAC cable, since some cables + * don't have this indication. */ - if (elink_read_sfp_module_eeprom(phy, - params, - ELINK_I2C_DEV_ADDR_A0, - ELINK_SFP_EEPROM_FC_TX_TECH_ADDR, - 1, - &copper_module_type) != - 0) { - PMD_DRV_LOG(DEBUG, - "Failed to read copper-cable-type" - " from SFP+ EEPROM"); - return ELINK_STATUS_ERROR; - } - if (copper_module_type & - ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) { - PMD_DRV_LOG(DEBUG, - "Active Copper cable detected"); - if (phy->type == - PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) - *edc_mode = ELINK_EDC_MODE_ACTIVE_DAC; - else - check_limiting_mode = 1; - } else if (copper_module_type & - ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) - { - PMD_DRV_LOG(DEBUG, - "Passive Copper cable detected"); - *edc_mode = ELINK_EDC_MODE_PASSIVE_DAC; + ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) { + ELINK_DEBUG_P0(sc, + "Passive Copper cable detected"); } else { - PMD_DRV_LOG(DEBUG, - "Unknown copper-cable-type 0x%x !!!", - copper_module_type); - return ELINK_STATUS_ERROR; + ELINK_DEBUG_P0(sc, + "Unknown copper-cable-type"); } - break; } + break; + } + case ELINK_SFP_EEPROM_CON_TYPE_VAL_UNKNOWN: case ELINK_SFP_EEPROM_CON_TYPE_VAL_LC: case ELINK_SFP_EEPROM_CON_TYPE_VAL_RJ45: check_limiting_mode = 1; - if ((val[1] & (ELINK_SFP_EEPROM_COMP_CODE_SR_MASK | - ELINK_SFP_EEPROM_COMP_CODE_LR_MASK | - ELINK_SFP_EEPROM_COMP_CODE_LRM_MASK)) == 0) { - PMD_DRV_LOG(DEBUG, "1G SFP module detected"); - gport = params->port; + /* Module is considered as 1G in case it's NOT compliant with + * any 10G ethernet protocol, but is 1G Ethernet compliant. + */ + if (((val[ELINK_SFP_EEPROM_10G_COMP_CODE_ADDR] & + (ELINK_SFP_EEPROM_10G_COMP_CODE_SR_MASK | + ELINK_SFP_EEPROM_10G_COMP_CODE_LR_MASK | + ELINK_SFP_EEPROM_10G_COMP_CODE_LRM_MASK)) == 0) && + (val[ELINK_SFP_EEPROM_1G_COMP_CODE_ADDR] != 0)) { + ELINK_DEBUG_P0(sc, "1G SFP module detected"); phy->media_type = ELINK_ETH_PHY_SFP_1G_FIBER; if (phy->req_line_speed != ELINK_SPEED_1000) { + uint8_t gport = params->port; phy->req_line_speed = ELINK_SPEED_1000; if (!CHIP_IS_E1x(sc)) { gport = SC_PATH(sc) + - (params->port << 1); + (params->port << 1); } - elink_cb_event_log(sc, ELINK_LOG_ID_NON_10G_MODULE, gport); //"Warning: Link speed was forced to 1000Mbps." - // " Current SFP module in port %d is not" - // " compliant with 10G Ethernet", + elink_cb_event_log(sc, + ELINK_LOG_ID_NON_10G_MODULE, + gport); + /*"Warning: Link speed was forced to 1000Mbps." + *" Current SFP module in port %d is not" + *" compliant with 10G Ethernet", + */ + } + if (val[ELINK_SFP_EEPROM_1G_COMP_CODE_ADDR] & + ELINK_SFP_EEPROM_1G_COMP_CODE_BASE_T) { + /* Some 1G-baseT modules will not link up, + * unless TX_EN is toggled with long delay in + * between. + */ + elink_sfp_set_transmitter(params, phy, 0); + DELAY(1000 * 40); + elink_sfp_set_transmitter(params, phy, 1); } } else { int idx, cfg_idx = 0; - PMD_DRV_LOG(DEBUG, "10G Optic module detected"); + ELINK_DEBUG_P0(sc, "10G Optic module detected"); for (idx = ELINK_INT_PHY; idx < ELINK_MAX_PHYS; idx++) { if (params->phy[idx].type == phy->type) { cfg_idx = ELINK_LINK_CONFIG_IDX(idx); @@ -7639,24 +9191,22 @@ static elink_status_t elink_get_edc_mode(struct elink_phy *phy, } break; default: - PMD_DRV_LOG(DEBUG, "Unable to determine module type 0x%x !!!", - val[0]); + ELINK_DEBUG_P1(sc, "Unable to determine module type 0x%x !!!", + val[ELINK_SFP_EEPROM_CON_TYPE_ADDR]); return ELINK_STATUS_ERROR; } sync_offset = params->shmem_base + - offsetof(struct shmem_region, - dev_info.port_hw_config[params->port].media_type); + offsetof(struct shmem_region, + dev_info.port_hw_config[params->port].media_type); media_types = REG_RD(sc, sync_offset); /* Update media type for non-PMF sync */ for (phy_idx = ELINK_INT_PHY; phy_idx < ELINK_MAX_PHYS; phy_idx++) { if (&(params->phy[phy_idx]) == phy) { media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK << - (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * - phy_idx)); - media_types |= - ((phy-> - media_type & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) << - (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx)); + (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx)); + media_types |= ((phy->media_type & + PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) << + (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx)); break; } } @@ -7669,8 +9219,8 @@ static elink_status_t elink_get_edc_mode(struct elink_phy *phy, ELINK_SFP_EEPROM_OPTIONS_ADDR, ELINK_SFP_EEPROM_OPTIONS_SIZE, options) != 0) { - PMD_DRV_LOG(DEBUG, - "Failed to read Option field from module EEPROM"); + ELINK_DEBUG_P0(sc, + "Failed to read Option field from module EEPROM"); return ELINK_STATUS_ERROR; } if ((options[0] & ELINK_SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK)) @@ -7678,15 +9228,14 @@ static elink_status_t elink_get_edc_mode(struct elink_phy *phy, else *edc_mode = ELINK_EDC_MODE_LIMITING; } - PMD_DRV_LOG(DEBUG, "EDC mode is set to 0x%x", *edc_mode); + ELINK_DEBUG_P1(sc, "EDC mode is set to 0x%x", *edc_mode); return ELINK_STATUS_OK; } - /* This function read the relevant field from the module (SFP+), and verify it * is compliant with this board */ static elink_status_t elink_verify_sfp_module(struct elink_phy *phy, - struct elink_params *params) + struct elink_params *params) { struct bnx2x_softc *sc = params->sc; uint32_t val, cmd; @@ -7695,12 +9244,11 @@ static elink_status_t elink_verify_sfp_module(struct elink_phy *phy, char vendor_pn[ELINK_SFP_EEPROM_PART_NO_SIZE + 1]; phy->flags &= ~ELINK_FLAGS_SFP_NOT_APPROVED; val = REG_RD(sc, params->shmem_base + - offsetof(struct shmem_region, - dev_info.port_feature_config[params->port]. - config)); + offsetof(struct shmem_region, dev_info. + port_feature_config[params->port].config)); if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) { - PMD_DRV_LOG(DEBUG, "NOT enforcing module verification"); + ELINK_DEBUG_P0(sc, "NOT enforcing module verification"); return ELINK_STATUS_OK; } @@ -7710,23 +9258,24 @@ static elink_status_t elink_verify_sfp_module(struct elink_phy *phy, cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL; } else if (params->feature_config_flags & ELINK_FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) { - /* Use first phy request only in case of non-dual media */ + /* Use first phy request only in case of non-dual media*/ if (ELINK_DUAL_MEDIA(params)) { - PMD_DRV_LOG(DEBUG, - "FW does not support OPT MDL verification"); + ELINK_DEBUG_P0(sc, + "FW does not support OPT MDL verification"); return ELINK_STATUS_ERROR; } cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL; } else { /* No support in OPT MDL detection */ - PMD_DRV_LOG(DEBUG, "FW does not support OPT MDL verification"); + ELINK_DEBUG_P0(sc, + "FW does not support OPT MDL verification"); return ELINK_STATUS_ERROR; } fw_cmd_param = ELINK_FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl); fw_resp = elink_cb_fw_command(sc, cmd, fw_cmd_param); if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) { - PMD_DRV_LOG(DEBUG, "Approved module"); + ELINK_DEBUG_P0(sc, "Approved module"); return ELINK_STATUS_OK; } @@ -7736,7 +9285,7 @@ static elink_status_t elink_verify_sfp_module(struct elink_phy *phy, ELINK_I2C_DEV_ADDR_A0, ELINK_SFP_EEPROM_VENDOR_NAME_ADDR, ELINK_SFP_EEPROM_VENDOR_NAME_SIZE, - (uint8_t *) vendor_name)) + (uint8_t *)vendor_name)) vendor_name[0] = '\0'; else vendor_name[ELINK_SFP_EEPROM_VENDOR_NAME_SIZE] = '\0'; @@ -7745,13 +9294,16 @@ static elink_status_t elink_verify_sfp_module(struct elink_phy *phy, ELINK_I2C_DEV_ADDR_A0, ELINK_SFP_EEPROM_PART_NO_ADDR, ELINK_SFP_EEPROM_PART_NO_SIZE, - (uint8_t *) vendor_pn)) + (uint8_t *)vendor_pn)) vendor_pn[0] = '\0'; else vendor_pn[ELINK_SFP_EEPROM_PART_NO_SIZE] = '\0'; - elink_cb_event_log(sc, ELINK_LOG_ID_UNQUAL_IO_MODULE, params->port, vendor_name, vendor_pn); // "Warning: Unqualified SFP+ module detected," - // " Port %d from %s part number %s", + elink_cb_event_log(sc, ELINK_LOG_ID_UNQUAL_IO_MODULE, params->port, + vendor_name, vendor_pn); + /* "Warning: Unqualified SFP+ module detected," + * " Port %d from %s part number %s", + */ if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) != PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG) @@ -7759,13 +9311,14 @@ static elink_status_t elink_verify_sfp_module(struct elink_phy *phy, return ELINK_STATUS_ERROR; } -static elink_status_t elink_wait_for_sfp_module_initialized(struct elink_phy - *phy, - struct elink_params - *params) +static elink_status_t elink_wait_for_sfp_module_initialized( + struct elink_phy *phy, + struct elink_params *params) + { uint8_t val; elink_status_t rc; + struct bnx2x_softc *sc = params->sc; uint16_t timeout; /* Initialization time after hot-plug may take up to 300ms for * some phys type ( e.g. JDSU ) @@ -7773,18 +9326,17 @@ static elink_status_t elink_wait_for_sfp_module_initialized(struct elink_phy for (timeout = 0; timeout < 60; timeout++) { if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) - rc = elink_warpcore_read_sfp_module_eeprom(phy, params, - ELINK_I2C_DEV_ADDR_A0, - 1, 1, &val, - 1); + rc = elink_warpcore_read_sfp_module_eeprom( + phy, params, ELINK_I2C_DEV_ADDR_A0, 1, 1, &val, + 1); else rc = elink_read_sfp_module_eeprom(phy, params, ELINK_I2C_DEV_ADDR_A0, 1, 1, &val); if (rc == 0) { - PMD_DRV_LOG(DEBUG, - "SFP+ module initialization took %d ms", - timeout * 5); + ELINK_DEBUG_P1(sc, + "SFP+ module initialization took %d ms", + timeout * 5); return ELINK_STATUS_OK; } DELAY(1000 * 5); @@ -7795,8 +9347,8 @@ static elink_status_t elink_wait_for_sfp_module_initialized(struct elink_phy } static void elink_8727_power_module(struct bnx2x_softc *sc, - struct elink_phy *phy, uint8_t is_power_up) -{ + struct elink_phy *phy, + uint8_t is_power_up) { /* Make sure GPIOs are not using for LED mode */ uint16_t val; /* In the GPIO register, bit 4 is use to determine if the GPIOs are @@ -7821,29 +9373,33 @@ static void elink_8727_power_module(struct bnx2x_softc *sc, val = (1 << 1); elink_cl45_write(sc, phy, - MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL, val); + MDIO_PMA_DEVAD, + MDIO_PMA_REG_8727_GPIO_CTRL, + val); } static elink_status_t elink_8726_set_limiting_mode(struct bnx2x_softc *sc, - struct elink_phy *phy, - uint16_t edc_mode) + struct elink_phy *phy, + uint16_t edc_mode) { uint16_t cur_limiting_mode; elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, - MDIO_PMA_REG_ROM_VER2, &cur_limiting_mode); - PMD_DRV_LOG(DEBUG, "Current Limiting mode is 0x%x", cur_limiting_mode); + MDIO_PMA_REG_ROM_VER2, + &cur_limiting_mode); + ELINK_DEBUG_P1(sc, "Current Limiting mode is 0x%x", + cur_limiting_mode); if (edc_mode == ELINK_EDC_MODE_LIMITING) { - PMD_DRV_LOG(DEBUG, "Setting LIMITING MODE"); + ELINK_DEBUG_P0(sc, "Setting LIMITING MODE"); elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER2, ELINK_EDC_MODE_LIMITING); - } else { /* LRM mode ( default ) */ + } else { /* LRM mode ( default )*/ - PMD_DRV_LOG(DEBUG, "Setting LRM MODE"); + ELINK_DEBUG_P0(sc, "Setting LRM MODE"); /* Changing to LRM mode takes quite few seconds. So do it only * if current mode is limiting (default is LRM) @@ -7852,27 +9408,35 @@ static elink_status_t elink_8726_set_limiting_mode(struct bnx2x_softc *sc, return ELINK_STATUS_OK; elink_cl45_write(sc, phy, - MDIO_PMA_DEVAD, MDIO_PMA_REG_LRM_MODE, 0); + MDIO_PMA_DEVAD, + MDIO_PMA_REG_LRM_MODE, + 0); elink_cl45_write(sc, phy, - MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER2, 0x128); + MDIO_PMA_DEVAD, + MDIO_PMA_REG_ROM_VER2, + 0x128); elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, - MDIO_PMA_REG_MISC_CTRL0, 0x4008); + MDIO_PMA_REG_MISC_CTRL0, + 0x4008); elink_cl45_write(sc, phy, - MDIO_PMA_DEVAD, MDIO_PMA_REG_LRM_MODE, 0xaaaa); + MDIO_PMA_DEVAD, + MDIO_PMA_REG_LRM_MODE, + 0xaaaa); } return ELINK_STATUS_OK; } static elink_status_t elink_8727_set_limiting_mode(struct bnx2x_softc *sc, - struct elink_phy *phy, - uint16_t edc_mode) + struct elink_phy *phy, + uint16_t edc_mode) { uint16_t phy_identifier; uint16_t rom_ver2_val; elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, - MDIO_PMA_REG_PHY_IDENTIFIER, &phy_identifier); + MDIO_PMA_REG_PHY_IDENTIFIER, + &phy_identifier); elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, @@ -7880,7 +9444,9 @@ static elink_status_t elink_8727_set_limiting_mode(struct bnx2x_softc *sc, (phy_identifier & ~(1 << 9))); elink_cl45_read(sc, phy, - MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER2, &rom_ver2_val); + MDIO_PMA_DEVAD, + MDIO_PMA_REG_ROM_VER2, + &rom_ver2_val); /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */ elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, @@ -7914,12 +9480,14 @@ static void elink_8727_specific_func(struct elink_phy *phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, (1 << 2) | (1 << 5)); elink_cl45_write(sc, phy, - MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL, 0); + MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL, + 0); elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0006); /* Make MOD_ABS give interrupt on change */ elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, - MDIO_PMA_REG_8727_PCS_OPT_CTRL, &val); + MDIO_PMA_REG_8727_PCS_OPT_CTRL, + &val); val |= (1 << 12); if (phy->flags & ELINK_FLAGS_NOC) val |= (3 << 5); @@ -7927,29 +9495,27 @@ static void elink_8727_specific_func(struct elink_phy *phy, * status which reflect SFP+ module over-current */ if (!(phy->flags & ELINK_FLAGS_NOC)) - val &= 0xff8f; /* Reset bits 4-6 */ + val &= 0xff8f; /* Reset bits 4-6 */ elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, val); break; default: - PMD_DRV_LOG(DEBUG, "Function 0x%x not supported by 8727", - action); + ELINK_DEBUG_P1(sc, "Function 0x%x not supported by 8727", + action); return; } } static void elink_set_e1e2_module_fault_led(struct elink_params *params, - uint8_t gpio_mode) + uint8_t gpio_mode) { struct bnx2x_softc *sc = params->sc; uint32_t fault_led_gpio = REG_RD(sc, params->shmem_base + - offsetof(struct shmem_region, - dev_info. - port_hw_config[params->port]. - sfp_ctrl)) & - PORT_HW_CFG_FAULT_MODULE_LED_MASK; + offsetof(struct shmem_region, + dev_info.port_hw_config[params->port].sfp_ctrl)) & + PORT_HW_CFG_FAULT_MODULE_LED_MASK; switch (fault_led_gpio) { case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED: return; @@ -7957,19 +9523,19 @@ static void elink_set_e1e2_module_fault_led(struct elink_params *params, case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1: case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2: case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3: - { - uint8_t gpio_port = elink_get_gpio_port(params); - uint16_t gpio_pin = fault_led_gpio - - PORT_HW_CFG_FAULT_MODULE_LED_GPIO0; - PMD_DRV_LOG(DEBUG, "Set fault module-detected led " - "pin %x port %x mode %x", - gpio_pin, gpio_port, gpio_mode); - elink_cb_gpio_write(sc, gpio_pin, gpio_mode, gpio_port); - } - break; + { + uint8_t gpio_port = elink_get_gpio_port(params); + uint16_t gpio_pin = fault_led_gpio - + PORT_HW_CFG_FAULT_MODULE_LED_GPIO0; + ELINK_DEBUG_P3(sc, "Set fault module-detected led " + "pin %x port %x mode %x", + gpio_pin, gpio_port, gpio_mode); + elink_cb_gpio_write(sc, gpio_pin, gpio_mode, gpio_port); + } + break; default: - PMD_DRV_LOG(DEBUG, "Error: Invalid fault led mode 0x%x", - fault_led_gpio); + ELINK_DEBUG_P1(sc, "Error: Invalid fault led mode 0x%x", + fault_led_gpio); } } @@ -7980,12 +9546,12 @@ static void elink_set_e3_module_fault_led(struct elink_params *params, uint8_t port = params->port; struct bnx2x_softc *sc = params->sc; pin_cfg = (REG_RD(sc, params->shmem_base + - offsetof(struct shmem_region, - dev_info.port_hw_config[port].e3_sfp_ctrl)) & - PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >> - PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT; - PMD_DRV_LOG(DEBUG, "Setting Fault LED to %d using pin cfg %d", - gpio_mode, pin_cfg); + offsetof(struct shmem_region, + dev_info.port_hw_config[port].e3_sfp_ctrl)) & + PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >> + PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT; + ELINK_DEBUG_P2(sc, "Setting Fault LED to %d using pin cfg %d", + gpio_mode, pin_cfg); elink_set_cfg_pin(sc, pin_cfg, gpio_mode); } @@ -7993,7 +9559,7 @@ static void elink_set_sfp_module_fault_led(struct elink_params *params, uint8_t gpio_mode) { struct bnx2x_softc *sc = params->sc; - PMD_DRV_LOG(DEBUG, "Setting SFP+ module fault LED to %d", gpio_mode); + ELINK_DEBUG_P1(sc, "Setting SFP+ module fault LED to %d", gpio_mode); if (CHIP_IS_E3(sc)) { /* Low ==> if SFP+ module is supported otherwise * High ==> if SFP+ module is not on the approved vendor list @@ -8018,9 +9584,11 @@ static void elink_warpcore_hw_reset(__rte_unused struct elink_phy *phy, } static void elink_power_sfp_module(struct elink_params *params, - struct elink_phy *phy, uint8_t power) + struct elink_phy *phy, + uint8_t power) { - PMD_DRV_LOG(DEBUG, "Setting SFP+ power to %x", power); + struct bnx2x_softc *sc = params->sc; + ELINK_DEBUG_P1(sc, "Setting SFP+ power to %x", power); switch (phy->type) { case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727: @@ -8034,7 +9602,6 @@ static void elink_power_sfp_module(struct elink_params *params, break; } } - static void elink_warpcore_set_limiting_mode(struct elink_params *params, struct elink_phy *phy, uint16_t edc_mode) @@ -8043,7 +9610,7 @@ static void elink_warpcore_set_limiting_mode(struct elink_params *params, uint16_t mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT; struct bnx2x_softc *sc = params->sc; - uint8_t lane = elink_get_warpcore_lane(params); + uint8_t lane = elink_get_warpcore_lane(phy, params); /* This is a global register which controls all lanes */ elink_cl45_read(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val); @@ -8076,7 +9643,8 @@ static void elink_warpcore_set_limiting_mode(struct elink_params *params, } static void elink_set_limiting_mode(struct elink_params *params, - struct elink_phy *phy, uint16_t edc_mode) + struct elink_phy *phy, + uint16_t edc_mode) { switch (phy->type) { case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726: @@ -8092,30 +9660,28 @@ static void elink_set_limiting_mode(struct elink_params *params, } } -static elink_status_t elink_sfp_module_detection(struct elink_phy *phy, - struct elink_params *params) +elink_status_t elink_sfp_module_detection(struct elink_phy *phy, + struct elink_params *params) { struct bnx2x_softc *sc = params->sc; uint16_t edc_mode; elink_status_t rc = ELINK_STATUS_OK; uint32_t val = REG_RD(sc, params->shmem_base + - offsetof(struct shmem_region, - dev_info.port_feature_config[params-> - port]. - config)); + offsetof(struct shmem_region, dev_info. + port_feature_config[params->port].config)); /* Enabled transmitter by default */ elink_sfp_set_transmitter(params, phy, 1); - PMD_DRV_LOG(DEBUG, "SFP+ module plugged in/out detected on port %d", - params->port); + ELINK_DEBUG_P1(sc, "SFP+ module plugged in/out detected on port %d", + params->port); /* Power up module */ elink_power_sfp_module(params, phy, 1); if (elink_get_edc_mode(phy, params, &edc_mode) != 0) { - PMD_DRV_LOG(DEBUG, "Failed to get valid module type"); + ELINK_DEBUG_P0(sc, "Failed to get valid module type"); return ELINK_STATUS_ERROR; } else if (elink_verify_sfp_module(phy, params) != 0) { /* Check SFP+ module compatibility */ - PMD_DRV_LOG(DEBUG, "Module verification failed!!"); + ELINK_DEBUG_P0(sc, "Module verification failed!!"); rc = ELINK_STATUS_ERROR; /* Turn on fault module-detected led */ elink_set_sfp_module_fault_led(params, @@ -8123,8 +9689,8 @@ static elink_status_t elink_sfp_module_detection(struct elink_phy *phy, /* Check if need to power down the SFP+ module */ if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == - PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) { - PMD_DRV_LOG(DEBUG, "Shutdown SFP+ module!!"); + PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) { + ELINK_DEBUG_P0(sc, "Shutdown SFP+ module!!"); elink_power_sfp_module(params, phy, 0); return rc; } @@ -8157,22 +9723,22 @@ void elink_handle_module_detect_int(struct elink_params *params) uint8_t gpio_num, gpio_port; if (CHIP_IS_E3(sc)) { phy = ¶ms->phy[ELINK_INT_PHY]; - /* Always enable TX laser,will be disabled in case of fault */ + /* Always enable TX laser, will be disabled in case of fault */ elink_sfp_set_transmitter(params, phy, 1); } else { phy = ¶ms->phy[ELINK_EXT_PHY1]; } - if (elink_get_mod_abs_int_cfg(sc, params->shmem_base, + if (elink_get_mod_abs_int_cfg(sc, params->chip_id, params->shmem_base, params->port, &gpio_num, &gpio_port) == ELINK_STATUS_ERROR) { - PMD_DRV_LOG(DEBUG, "Failed to get MOD_ABS interrupt config"); + ELINK_DEBUG_P0(sc, "Failed to get MOD_ABS interrupt config"); return; } /* Set valid module led off */ elink_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH); - /* Get current gpio val reflecting module plugged in / out */ + /* Get current gpio val reflecting module plugged in / out*/ gpio_val = elink_cb_gpio_read(sc, gpio_num, gpio_port); /* Call the handling function in case module is detected */ @@ -8182,8 +9748,8 @@ void elink_handle_module_detect_int(struct elink_params *params) elink_power_sfp_module(params, phy, 1); elink_cb_gpio_int_write(sc, gpio_num, - MISC_REGISTERS_GPIO_INT_OUTPUT_CLR, - gpio_port); + MISC_REGISTERS_GPIO_INT_OUTPUT_CLR, + gpio_port); if (elink_wait_for_sfp_module_initialized(phy, params) == 0) { elink_sfp_module_detection(phy, params); if (CHIP_IS_E3(sc)) { @@ -8205,12 +9771,12 @@ void elink_handle_module_detect_int(struct elink_params *params) } } } else { - PMD_DRV_LOG(DEBUG, "SFP+ module is not initialized"); + ELINK_DEBUG_P0(sc, "SFP+ module is not initialized"); } } else { elink_cb_gpio_int_write(sc, gpio_num, - MISC_REGISTERS_GPIO_INT_OUTPUT_SET, - gpio_port); + MISC_REGISTERS_GPIO_INT_OUTPUT_SET, + gpio_port); /* Module was plugged out. * Disable transmit for this module */ @@ -8228,9 +9794,11 @@ static void elink_sfp_mask_fault(struct bnx2x_softc *sc, { uint16_t alarm_status, val; elink_cl45_read(sc, phy, - MDIO_PMA_DEVAD, alarm_status_offset, &alarm_status); + MDIO_PMA_DEVAD, alarm_status_offset, + &alarm_status); elink_cl45_read(sc, phy, - MDIO_PMA_DEVAD, alarm_status_offset, &alarm_status); + MDIO_PMA_DEVAD, alarm_status_offset, + &alarm_status); /* Mask or enable the fault event. */ elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val); if (alarm_status & (1 << 0)) @@ -8239,37 +9807,42 @@ static void elink_sfp_mask_fault(struct bnx2x_softc *sc, val |= (1 << 0); elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val); } - /******************************************************************/ /* common BNX2X8706/BNX2X8726 PHY SECTION */ /******************************************************************/ static uint8_t elink_8706_8726_read_status(struct elink_phy *phy, - struct elink_params *params, - struct elink_vars *vars) + struct elink_params *params, + struct elink_vars *vars) { uint8_t link_up = 0; uint16_t val1, val2, rx_sd, pcs_status; struct bnx2x_softc *sc = params->sc; - PMD_DRV_LOG(DEBUG, "XGXS 8706/8726"); - /* Clear RX Alarm */ - elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2); + ELINK_DEBUG_P0(sc, "XGXS 8706/8726"); + /* Clear RX Alarm*/ + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2); elink_sfp_mask_fault(sc, phy, MDIO_PMA_LASI_TXSTAT, MDIO_PMA_LASI_TXCTRL); - /* Clear LASI indication */ - elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); - elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2); - PMD_DRV_LOG(DEBUG, "8706/8726 LASI status 0x%x--> 0x%x", val1, val2); + /* Clear LASI indication*/ + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2); + ELINK_DEBUG_P2(sc, "8706/8726 LASI status 0x%x--> 0x%x", val1, val2); - elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd); + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd); elink_cl45_read(sc, phy, MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status); - elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2); - elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2); + elink_cl45_read(sc, phy, + MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2); + elink_cl45_read(sc, phy, + MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2); - PMD_DRV_LOG(DEBUG, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps" - " link_status 0x%x", rx_sd, pcs_status, val2); + ELINK_DEBUG_P3(sc, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps" + " link_status 0x%x", rx_sd, pcs_status, val2); /* Link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status * are set, or if the autoneg bit 1 is set */ @@ -8286,9 +9859,9 @@ static uint8_t elink_8706_8726_read_status(struct elink_phy *phy, /* Capture 10G link fault. Read twice to clear stale value. */ if (vars->line_speed == ELINK_SPEED_10000) { elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, - MDIO_PMA_LASI_TXSTAT, &val1); + MDIO_PMA_LASI_TXSTAT, &val1); elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, - MDIO_PMA_LASI_TXSTAT, &val1); + MDIO_PMA_LASI_TXSTAT, &val1); if (val1 & (1 << 0)) vars->fault_detected = 1; } @@ -8300,15 +9873,15 @@ static uint8_t elink_8706_8726_read_status(struct elink_phy *phy, /* BNX2X8706 PHY SECTION */ /******************************************************************/ static uint8_t elink_8706_config_init(struct elink_phy *phy, - struct elink_params *params, - __rte_unused struct elink_vars *vars) + struct elink_params *params, + __rte_unused struct elink_vars *vars) { uint32_t tx_en_mode; uint16_t cnt, val, tmp1; struct bnx2x_softc *sc = params->sc; elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2, - MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); + MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); /* HW reset */ elink_ext_phy_hw_reset(sc, params->port); elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040); @@ -8322,34 +9895,35 @@ static uint8_t elink_8706_config_init(struct elink_phy *phy, break; DELAY(1000 * 10); } - PMD_DRV_LOG(DEBUG, "XGXS 8706 is initialized after %d ms", cnt); + ELINK_DEBUG_P1(sc, "XGXS 8706 is initialized after %d ms", cnt); if ((params->feature_config_flags & ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) { uint8_t i; uint16_t reg; for (i = 0; i < 4; i++) { reg = MDIO_XS_8706_REG_BANK_RX0 + - i * (MDIO_XS_8706_REG_BANK_RX1 - - MDIO_XS_8706_REG_BANK_RX0); + i * (MDIO_XS_8706_REG_BANK_RX1 - + MDIO_XS_8706_REG_BANK_RX0); elink_cl45_read(sc, phy, MDIO_XS_DEVAD, reg, &val); /* Clear first 3 bits of the control */ val &= ~0x7; /* Set control bits according to configuration */ val |= (phy->rx_preemphasis[i] & 0x7); - PMD_DRV_LOG(DEBUG, "Setting RX Equalizer to BNX2X8706" - " reg 0x%x <-- val 0x%x", reg, val); + ELINK_DEBUG_P2(sc, "Setting RX Equalizer to BNX2X8706" + " reg 0x%x <-- val 0x%x", reg, val); elink_cl45_write(sc, phy, MDIO_XS_DEVAD, reg, val); } } /* Force speed */ if (phy->req_line_speed == ELINK_SPEED_10000) { - PMD_DRV_LOG(DEBUG, "XGXS 8706 force 10Gbps"); + ELINK_DEBUG_P0(sc, "XGXS 8706 force 10Gbps"); elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, 0x400); elink_cl45_write(sc, phy, - MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL, 0); + MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL, + 0); /* Arm LASI for link and Tx fault. */ elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 3); @@ -8357,7 +9931,7 @@ static uint8_t elink_8706_config_init(struct elink_phy *phy, /* Force 1Gbps using autoneg with 1G advertisement */ /* Allow CL37 through CL73 */ - PMD_DRV_LOG(DEBUG, "XGXS 8706 AutoNeg"); + ELINK_DEBUG_P0(sc, "XGXS 8706 AutoNeg"); elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c); @@ -8375,9 +9949,11 @@ static uint8_t elink_8706_config_init(struct elink_phy *phy, elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); elink_cl45_write(sc, phy, - MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 0x0400); + MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, + 0x0400); elink_cl45_write(sc, phy, - MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0004); + MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, + 0x0004); } elink_save_bnx2x_spirom_ver(sc, phy, params->port); @@ -8387,27 +9963,24 @@ static uint8_t elink_8706_config_init(struct elink_phy *phy, tx_en_mode = REG_RD(sc, params->shmem_base + offsetof(struct shmem_region, - dev_info.port_hw_config[params->port]. - sfp_ctrl)) - & PORT_HW_CFG_TX_LASER_MASK; + dev_info.port_hw_config[params->port].sfp_ctrl)) + & PORT_HW_CFG_TX_LASER_MASK; if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) { - PMD_DRV_LOG(DEBUG, "Enabling TXONOFF_PWRDN_DIS"); + ELINK_DEBUG_P0(sc, "Enabling TXONOFF_PWRDN_DIS"); elink_cl45_read(sc, phy, - MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, - &tmp1); + MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, &tmp1); tmp1 |= 0x1; elink_cl45_write(sc, phy, - MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, - tmp1); + MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, tmp1); } return ELINK_STATUS_OK; } static uint8_t elink_8706_read_status(struct elink_phy *phy, - struct elink_params *params, - struct elink_vars *vars) + struct elink_params *params, + struct elink_vars *vars) { return elink_8706_8726_read_status(phy, params, vars); } @@ -8419,7 +9992,7 @@ static void elink_8726_config_loopback(struct elink_phy *phy, struct elink_params *params) { struct bnx2x_softc *sc = params->sc; - PMD_DRV_LOG(DEBUG, "PMA/PMD ext_phy_loopback: 8726"); + ELINK_DEBUG_P0(sc, "PMA/PMD ext_phy_loopback: 8726"); elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001); } @@ -8441,7 +10014,8 @@ static void elink_8726_external_rom_boot(struct elink_phy *phy, MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET); elink_cl45_write(sc, phy, - MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL1, 0x0001); + MDIO_PMA_DEVAD, + MDIO_PMA_REG_MISC_CTRL1, 0x0001); elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, @@ -8453,15 +10027,16 @@ static void elink_8726_external_rom_boot(struct elink_phy *phy, /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */ elink_cl45_write(sc, phy, - MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL1, 0x0000); + MDIO_PMA_DEVAD, + MDIO_PMA_REG_MISC_CTRL1, 0x0000); DELAY(1000 * 200); elink_save_bnx2x_spirom_ver(sc, phy, params->port); } static uint8_t elink_8726_read_status(struct elink_phy *phy, - struct elink_params *params, - struct elink_vars *vars) + struct elink_params *params, + struct elink_vars *vars) { struct bnx2x_softc *sc = params->sc; uint16_t val1; @@ -8471,7 +10046,7 @@ static uint8_t elink_8726_read_status(struct elink_phy *phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &val1); if (val1 & (1 << 15)) { - PMD_DRV_LOG(DEBUG, "Tx is disabled"); + ELINK_DEBUG_P0(sc, "Tx is disabled"); link_up = 0; vars->line_speed = 0; } @@ -8479,12 +10054,13 @@ static uint8_t elink_8726_read_status(struct elink_phy *phy, return link_up; } + static uint8_t elink_8726_config_init(struct elink_phy *phy, - struct elink_params *params, - struct elink_vars *vars) + struct elink_params *params, + struct elink_vars *vars) { struct bnx2x_softc *sc = params->sc; - PMD_DRV_LOG(DEBUG, "Initializing BNX2X8726"); + ELINK_DEBUG_P0(sc, "Initializing BNX2X8726"); elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1 << 15); elink_wait_reset_complete(sc, phy, params); @@ -8499,7 +10075,7 @@ static uint8_t elink_8726_config_init(struct elink_phy *phy, elink_sfp_module_detection(phy, params); if (phy->req_line_speed == ELINK_SPEED_1000) { - PMD_DRV_LOG(DEBUG, "Setting 1G force"); + ELINK_DEBUG_P0(sc, "Setting 1G force"); elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40); elink_cl45_write(sc, phy, @@ -8507,17 +10083,19 @@ static uint8_t elink_8726_config_init(struct elink_phy *phy, elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x5); elink_cl45_write(sc, phy, - MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 0x400); + MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, + 0x400); } else if ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) && (phy->speed_cap_mask & - PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) && + PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) && ((phy->speed_cap_mask & - PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) != + PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) != PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { - PMD_DRV_LOG(DEBUG, "Setting 1G clause37"); + ELINK_DEBUG_P0(sc, "Setting 1G clause37"); /* Set Flow control */ elink_ext_phy_set_pause(params, phy, vars); - elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20); + elink_cl45_write(sc, phy, + MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20); elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c); elink_cl45_write(sc, phy, @@ -8525,16 +10103,17 @@ static uint8_t elink_8726_config_init(struct elink_phy *phy, elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); elink_cl45_write(sc, phy, - MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); + MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); /* Enable RX-ALARM control to receive interrupt for 1G speed * change */ elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x4); elink_cl45_write(sc, phy, - MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 0x400); + MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, + 0x400); - } else { /* Default 10G. Set only LASI control */ + } else { /* Default 10G. Set only LASI control */ elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 1); } @@ -8542,9 +10121,10 @@ static uint8_t elink_8726_config_init(struct elink_phy *phy, /* Set TX PreEmphasis if needed */ if ((params->feature_config_flags & ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) { - PMD_DRV_LOG(DEBUG, - "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x", - phy->tx_preemphasis[0], phy->tx_preemphasis[1]); + ELINK_DEBUG_P2(sc, + "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x", + phy->tx_preemphasis[0], + phy->tx_preemphasis[1]); elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_8726_TX_CTRL1, @@ -8564,10 +10144,11 @@ static void elink_8726_link_reset(struct elink_phy *phy, struct elink_params *params) { struct bnx2x_softc *sc = params->sc; - PMD_DRV_LOG(DEBUG, "elink_8726_link_reset port %d", params->port); + ELINK_DEBUG_P1(sc, "elink_8726_link_reset port %d", params->port); /* Set serial boot control for external load */ elink_cl45_write(sc, phy, - MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001); + MDIO_PMA_DEVAD, + MDIO_PMA_REG_GEN_CTRL, 0x0001); } /******************************************************************/ @@ -8600,22 +10181,28 @@ static void elink_8727_set_link_led(struct elink_phy *phy, break; } elink_cl45_read(sc, phy, - MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, &val); + MDIO_PMA_DEVAD, + MDIO_PMA_REG_8727_PCS_OPT_CTRL, + &val); val &= 0xff8f; val |= led_mode_bitmask; elink_cl45_write(sc, phy, - MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, val); + MDIO_PMA_DEVAD, + MDIO_PMA_REG_8727_PCS_OPT_CTRL, + val); elink_cl45_read(sc, phy, - MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL, &val); + MDIO_PMA_DEVAD, + MDIO_PMA_REG_8727_GPIO_CTRL, + &val); val &= 0xffe0; val |= gpio_pins_bitmask; elink_cl45_write(sc, phy, - MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL, val); + MDIO_PMA_DEVAD, + MDIO_PMA_REG_8727_GPIO_CTRL, + val); } - static void elink_8727_hw_reset(__rte_unused struct elink_phy *phy, - struct elink_params *params) -{ + struct elink_params *params) { uint32_t swap_val, swap_override; uint8_t port; /* The PHY reset is controlled by GPIO 1. Fake the port number @@ -8626,7 +10213,7 @@ static void elink_8727_hw_reset(__rte_unused struct elink_phy *phy, swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE); port = (swap_val && swap_override) ^ 1; elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1, - MISC_REGISTERS_GPIO_OUTPUT_LOW, port); + MISC_REGISTERS_GPIO_OUTPUT_LOW, port); } static void elink_8727_config_speed(struct elink_phy *phy, @@ -8637,14 +10224,14 @@ static void elink_8727_config_speed(struct elink_phy *phy, /* Set option 1G speed */ if ((phy->req_line_speed == ELINK_SPEED_1000) || (phy->media_type == ELINK_ETH_PHY_SFP_1G_FIBER)) { - PMD_DRV_LOG(DEBUG, "Setting 1G force"); + ELINK_DEBUG_P0(sc, "Setting 1G force"); elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40); elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD); elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1); - PMD_DRV_LOG(DEBUG, "1.7 = 0x%x", tmp1); + ELINK_DEBUG_P1(sc, "1.7 = 0x%x", tmp1); /* Power down the XAUI until link is up in case of dual-media * and 1G */ @@ -8661,10 +10248,10 @@ static void elink_8727_config_speed(struct elink_phy *phy, ((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) && ((phy->speed_cap_mask & - PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) != - PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { + PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) != + PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { - PMD_DRV_LOG(DEBUG, "Setting 1G clause37"); + ELINK_DEBUG_P0(sc, "Setting 1G clause37"); elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0); elink_cl45_write(sc, phy, @@ -8687,9 +10274,8 @@ static void elink_8727_config_speed(struct elink_phy *phy, } static uint8_t elink_8727_config_init(struct elink_phy *phy, - struct elink_params *params, - __rte_unused struct elink_vars - *vars) + struct elink_params *params, + __rte_unused struct elink_vars *vars) { uint32_t tx_en_mode; uint16_t tmp1, mod_abs, tmp2; @@ -8698,7 +10284,7 @@ static uint8_t elink_8727_config_init(struct elink_phy *phy, elink_wait_reset_complete(sc, phy, params); - PMD_DRV_LOG(DEBUG, "Initializing BNX2X8727"); + ELINK_DEBUG_P0(sc, "Initializing BNX2X8727"); elink_8727_specific_func(phy, params, ELINK_PHY_INIT); /* Initially configure MOD_ABS to interrupt when module is @@ -8724,15 +10310,18 @@ static uint8_t elink_8727_config_init(struct elink_phy *phy, elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1); - elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1); + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1); elink_8727_config_speed(phy, params); + /* Set TX PreEmphasis if needed */ if ((params->feature_config_flags & ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) { - PMD_DRV_LOG(DEBUG, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x", - phy->tx_preemphasis[0], phy->tx_preemphasis[1]); + ELINK_DEBUG_P2(sc, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x", + phy->tx_preemphasis[0], + phy->tx_preemphasis[1]); elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1, phy->tx_preemphasis[0]); @@ -8747,25 +10336,24 @@ static uint8_t elink_8727_config_init(struct elink_phy *phy, */ tx_en_mode = REG_RD(sc, params->shmem_base + offsetof(struct shmem_region, - dev_info.port_hw_config[params->port]. - sfp_ctrl)) - & PORT_HW_CFG_TX_LASER_MASK; + dev_info.port_hw_config[params->port].sfp_ctrl)) + & PORT_HW_CFG_TX_LASER_MASK; if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) { - PMD_DRV_LOG(DEBUG, "Enabling TXONOFF_PWRDN_DIS"); + ELINK_DEBUG_P0(sc, "Enabling TXONOFF_PWRDN_DIS"); elink_cl45_read(sc, phy, - MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, - &tmp2); + MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, &tmp2); tmp2 |= 0x1000; tmp2 &= 0xFFEF; elink_cl45_write(sc, phy, - MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, - tmp2); - elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, - MDIO_PMA_REG_PHY_IDENTIFIER, &tmp2); - elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, - MDIO_PMA_REG_PHY_IDENTIFIER, (tmp2 & 0x7fff)); + MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, tmp2); + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, + &tmp2); + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, + (tmp2 & 0x7fff)); } return ELINK_STATUS_OK; @@ -8777,15 +10365,17 @@ static void elink_8727_handle_mod_abs(struct elink_phy *phy, struct bnx2x_softc *sc = params->sc; uint16_t mod_abs, rx_alarm_status; uint32_t val = REG_RD(sc, params->shmem_base + - offsetof(struct shmem_region, - dev_info.port_feature_config[params-> - port].config)); - elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, - &mod_abs); + offsetof(struct shmem_region, dev_info. + port_feature_config[params->port]. + config)); + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs); if (mod_abs & (1 << 8)) { /* Module is absent */ - PMD_DRV_LOG(DEBUG, "MOD_ABS indication show module is absent"); + ELINK_DEBUG_P0(sc, + "MOD_ABS indication show module is absent"); phy->media_type = ELINK_ETH_PHY_NOT_PRESENT; /* 1. Set mod_abs to detect next module * presence event @@ -8810,7 +10400,8 @@ static void elink_8727_handle_mod_abs(struct elink_phy *phy, } else { /* Module is present */ - PMD_DRV_LOG(DEBUG, "MOD_ABS indication show module is present"); + ELINK_DEBUG_P0(sc, + "MOD_ABS indication show module is present"); /* First disable transmitter, and if the module is ok, the * module_detection will enable it * 1. Set mod_abs to detect next module absent event ( bit 8) @@ -8834,51 +10425,56 @@ static void elink_8727_handle_mod_abs(struct elink_phy *phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &rx_alarm_status); + if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER) elink_sfp_set_transmitter(params, phy, 0); - if (elink_wait_for_sfp_module_initialized(phy, params) == 0) { + if (elink_wait_for_sfp_module_initialized(phy, params) == 0) elink_sfp_module_detection(phy, params); - } else { - PMD_DRV_LOG(DEBUG, "SFP+ module is not initialized"); - } + else + ELINK_DEBUG_P0(sc, "SFP+ module is not initialized"); /* Reconfigure link speed based on module type limitations */ elink_8727_config_speed(phy, params); } - PMD_DRV_LOG(DEBUG, "8727 RX_ALARM_STATUS 0x%x", rx_alarm_status); + ELINK_DEBUG_P1(sc, "8727 RX_ALARM_STATUS 0x%x", + rx_alarm_status); /* No need to check link status in case of module plugged in/out */ } static uint8_t elink_8727_read_status(struct elink_phy *phy, - struct elink_params *params, - struct elink_vars *vars) + struct elink_params *params, + struct elink_vars *vars) + { struct bnx2x_softc *sc = params->sc; - uint8_t link_up = 0, oc_port = params->port; + uint8_t link_up = 0; uint16_t link_status = 0; uint16_t rx_alarm_status, lasi_ctrl, val1; /* If PHY is not initialized, do not check link status */ elink_cl45_read(sc, phy, - MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, &lasi_ctrl); + MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, + &lasi_ctrl); if (!lasi_ctrl) return 0; /* Check the LASI on Rx */ elink_cl45_read(sc, phy, - MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &rx_alarm_status); + MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, + &rx_alarm_status); vars->line_speed = 0; - PMD_DRV_LOG(DEBUG, "8727 RX_ALARM_STATUS 0x%x", rx_alarm_status); + ELINK_DEBUG_P1(sc, "8727 RX_ALARM_STATUS 0x%x", rx_alarm_status); elink_sfp_mask_fault(sc, phy, MDIO_PMA_LASI_TXSTAT, MDIO_PMA_LASI_TXCTRL); - elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); - PMD_DRV_LOG(DEBUG, "8727 LASI status 0x%x", val1); + ELINK_DEBUG_P1(sc, "8727 LASI status 0x%x", val1); /* Clear MSG-OUT */ elink_cl45_read(sc, phy, @@ -8888,24 +10484,28 @@ static uint8_t elink_8727_read_status(struct elink_phy *phy, * for over current */ if (!(phy->flags & ELINK_FLAGS_NOC) && !(rx_alarm_status & (1 << 5))) { - /* Check over-current using 8727 GPIO0 input */ + /* Check over-current using 8727 GPIO0 input*/ elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL, &val1); if ((val1 & (1 << 8)) == 0) { + uint8_t oc_port = params->port; if (!CHIP_IS_E1x(sc)) oc_port = SC_PATH(sc) + (params->port << 1); - PMD_DRV_LOG(DEBUG, - "8727 Power fault has been detected on port %d", - oc_port); - elink_cb_event_log(sc, ELINK_LOG_ID_OVER_CURRENT, oc_port); //"Error: Power fault on Port %d has " - // "been detected and the power to " - // "that SFP+ module has been removed " - // "to prevent failure of the card. " - // "Please remove the SFP+ module and " - // "restart the system to clear this " - // "error.", + ELINK_DEBUG_P1(sc, + "8727 Power fault has been detected on port %d", + oc_port); + elink_cb_event_log(sc, ELINK_LOG_ID_OVER_CURRENT, + oc_port); + /* "Error: Power fault on Port %d has " + * "been detected and the power to " + * "that SFP+ module has been removed " + * "to prevent failure of the card. " + * "Please remove the SFP+ module and " + * "restart the system to clear this " + * "error.", + */ /* Disable all RX_ALARMs except for mod_abs */ elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, @@ -8921,14 +10521,13 @@ static uint8_t elink_8727_read_status(struct elink_phy *phy, MDIO_PMA_REG_PHY_IDENTIFIER, val1); /* Clear RX alarm */ elink_cl45_read(sc, phy, - MDIO_PMA_DEVAD, - MDIO_PMA_LASI_RXSTAT, &rx_alarm_status); + MDIO_PMA_DEVAD, + MDIO_PMA_LASI_RXSTAT, &rx_alarm_status); elink_8727_power_module(params->sc, phy, 0); return 0; } - } + } /* Over current check */ - /* Over current check */ /* When module absent bit is set, check module */ if (rx_alarm_status & (1 << 5)) { elink_8727_handle_mod_abs(phy, params); @@ -8939,10 +10538,10 @@ static uint8_t elink_8727_read_status(struct elink_phy *phy, } if (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED)) { - PMD_DRV_LOG(DEBUG, "Enabling 8727 TX laser"); + ELINK_DEBUG_P0(sc, "Enabling 8727 TX laser"); elink_sfp_set_transmitter(params, phy, 1); } else { - PMD_DRV_LOG(DEBUG, "Tx is disabled"); + ELINK_DEBUG_P0(sc, "Tx is disabled"); return 0; } @@ -8956,26 +10555,26 @@ static uint8_t elink_8727_read_status(struct elink_phy *phy, if ((link_status & (1 << 2)) && (!(link_status & (1 << 15)))) { link_up = 1; vars->line_speed = ELINK_SPEED_10000; - PMD_DRV_LOG(DEBUG, "port %x: External link up in 10G", - params->port); + ELINK_DEBUG_P1(sc, "port %x: External link up in 10G", + params->port); } else if ((link_status & (1 << 0)) && (!(link_status & (1 << 13)))) { link_up = 1; vars->line_speed = ELINK_SPEED_1000; - PMD_DRV_LOG(DEBUG, "port %x: External link up in 1G", - params->port); + ELINK_DEBUG_P1(sc, "port %x: External link up in 1G", + params->port); } else { link_up = 0; - PMD_DRV_LOG(DEBUG, "port %x: External link is down", - params->port); + ELINK_DEBUG_P1(sc, "port %x: External link is down", + params->port); } /* Capture 10G link fault. */ if (vars->line_speed == ELINK_SPEED_10000) { elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, - MDIO_PMA_LASI_TXSTAT, &val1); + MDIO_PMA_LASI_TXSTAT, &val1); elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, - MDIO_PMA_LASI_TXSTAT, &val1); + MDIO_PMA_LASI_TXSTAT, &val1); if (val1 & (1 << 0)) { vars->fault_detected = 1; @@ -8985,7 +10584,7 @@ static uint8_t elink_8727_read_status(struct elink_phy *phy, if (link_up) { elink_ext_phy_resolve_fc(phy, params, vars); vars->duplex = DUPLEX_FULL; - PMD_DRV_LOG(DEBUG, "duplex = 0x%x", vars->duplex); + ELINK_DEBUG_P1(sc, "duplex = 0x%x", vars->duplex); } if ((ELINK_DUAL_MEDIA(params)) && @@ -9025,8 +10624,16 @@ static void elink_8727_link_reset(struct elink_phy *phy, /******************************************************************/ /* BNX2X8481/BNX2X84823/BNX2X84833 PHY SECTION */ /******************************************************************/ +static int elink_is_8483x_8485x(struct elink_phy *phy) +{ + return ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) || + (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834) || + (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84858)); +} + static void elink_save_848xx_spirom_version(struct elink_phy *phy, - struct bnx2x_softc *sc, uint8_t port) + struct bnx2x_softc *sc, + uint8_t port) { uint16_t val, fw_ver2, cnt, i; static struct elink_reg_set reg_set[] = { @@ -9038,11 +10645,10 @@ static void elink_save_848xx_spirom_version(struct elink_phy *phy, }; uint16_t fw_ver1; - if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) || - (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) { + if (elink_is_8483x_8485x(phy)) { elink_cl45_read(sc, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1); elink_save_spirom_version(sc, port, fw_ver1 & 0xfff, - phy->ver_addr); + phy->ver_addr); } else { /* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */ /* (1) set reg 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */ @@ -9057,12 +10663,14 @@ static void elink_save_848xx_spirom_version(struct elink_phy *phy, DELAY(5); } if (cnt == 100) { - PMD_DRV_LOG(DEBUG, "Unable to read 848xx " - "phy fw version(1)"); - elink_save_spirom_version(sc, port, 0, phy->ver_addr); + ELINK_DEBUG_P0(sc, "Unable to read 848xx " + "phy fw version(1)"); + elink_save_spirom_version(sc, port, 0, + phy->ver_addr); return; } + /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */ elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000); elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200); @@ -9074,9 +10682,10 @@ static void elink_save_848xx_spirom_version(struct elink_phy *phy, DELAY(5); } if (cnt == 100) { - PMD_DRV_LOG(DEBUG, "Unable to read 848xx phy fw " - "version(2)"); - elink_save_spirom_version(sc, port, 0, phy->ver_addr); + ELINK_DEBUG_P0(sc, "Unable to read 848xx phy fw " + "version(2)"); + elink_save_spirom_version(sc, port, 0, + phy->ver_addr); return; } @@ -9090,8 +10699,8 @@ static void elink_save_848xx_spirom_version(struct elink_phy *phy, } } - -static void elink_848xx_set_led(struct bnx2x_softc *sc, struct elink_phy *phy) +static void elink_848xx_set_led(struct bnx2x_softc *sc, + struct elink_phy *phy) { uint16_t val, offset, i; static struct elink_reg_set reg_set[] = { @@ -9100,29 +10709,30 @@ static void elink_848xx_set_led(struct bnx2x_softc *sc, struct elink_phy *phy) {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_MASK, 0x0006}, {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_BLINK, 0x0000}, {MDIO_PMA_DEVAD, MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH, - MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ}, + MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ}, {MDIO_AN_DEVAD, 0xFFFB, 0xFFFD} }; /* PHYC_CTL_LED_CTL */ elink_cl45_read(sc, phy, - MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LINK_SIGNAL, &val); + MDIO_PMA_DEVAD, + MDIO_PMA_REG_8481_LINK_SIGNAL, &val); val &= 0xFE00; val |= 0x0092; elink_cl45_write(sc, phy, - MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LINK_SIGNAL, val); + MDIO_PMA_DEVAD, + MDIO_PMA_REG_8481_LINK_SIGNAL, val); for (i = 0; i < ARRAY_SIZE(reg_set); i++) elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg, reg_set[i].val); - if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) || - (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) + if (elink_is_8483x_8485x(phy)) offset = MDIO_PMA_REG_84833_CTL_LED_CTL_1; else offset = MDIO_PMA_REG_84823_CTL_LED_CTL_1; - /* stretch_en for LED3 */ + /* stretch_en for LED3*/ elink_cl45_read_or_write(sc, phy, MDIO_PMA_DEVAD, offset, MDIO_PMA_REG_84823_LED3_STRETCH_EN); @@ -9135,8 +10745,7 @@ static void elink_848xx_specific_func(struct elink_phy *phy, struct bnx2x_softc *sc = params->sc; switch (action) { case ELINK_PHY_INIT: - if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) && - (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) { + if (!elink_is_8483x_8485x(phy)) { /* Save spirom version */ elink_save_848xx_spirom_version(phy, sc, params->port); } @@ -9153,14 +10762,15 @@ static void elink_848xx_specific_func(struct elink_phy *phy, } static elink_status_t elink_848xx_cmn_config_init(struct elink_phy *phy, - struct elink_params *params, - struct elink_vars *vars) + struct elink_params *params, + struct elink_vars *vars) { struct bnx2x_softc *sc = params->sc; uint16_t autoneg_val, an_1000_val, an_10_100_val; elink_848xx_specific_func(phy, params, ELINK_PHY_INIT); - elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000); + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000); /* set 1000 speed advertisement */ elink_cl45_read(sc, phy, @@ -9170,24 +10780,25 @@ static elink_status_t elink_848xx_cmn_config_init(struct elink_phy *phy, elink_ext_phy_set_pause(params, phy, vars); elink_cl45_read(sc, phy, MDIO_AN_DEVAD, - MDIO_AN_REG_8481_LEGACY_AN_ADV, &an_10_100_val); + MDIO_AN_REG_8481_LEGACY_AN_ADV, + &an_10_100_val); elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL, &autoneg_val); /* Disable forced speed */ - autoneg_val &= - ~((1 << 6) | (1 << 8) | (1 << 9) | (1 << 12) | (1 << 13)); + autoneg_val &= ~((1 << 6) | (1 << 8) | (1 << 9) | (1 << 12) | + (1 << 13)); an_10_100_val &= ~((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8)); if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) && (phy->speed_cap_mask & - PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || + PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || (phy->req_line_speed == ELINK_SPEED_1000)) { an_1000_val |= (1 << 8); autoneg_val |= (1 << 9 | 1 << 12); if (phy->req_duplex == DUPLEX_FULL) an_1000_val |= (1 << 9); - PMD_DRV_LOG(DEBUG, "Advertising 1G"); + ELINK_DEBUG_P0(sc, "Advertising 1G"); } else an_1000_val &= ~((1 << 8) | (1 << 9)); @@ -9203,7 +10814,7 @@ static elink_status_t elink_848xx_cmn_config_init(struct elink_phy *phy, */ autoneg_val |= (1 << 9 | 1 << 12); an_10_100_val |= (1 << 8); - PMD_DRV_LOG(DEBUG, "Advertising 100M-FD"); + ELINK_DEBUG_P0(sc, "Advertising 100M-FD"); } if (phy->speed_cap_mask & @@ -9212,7 +10823,7 @@ static elink_status_t elink_848xx_cmn_config_init(struct elink_phy *phy, */ autoneg_val |= (1 << 9 | 1 << 12); an_10_100_val |= (1 << 7); - PMD_DRV_LOG(DEBUG, "Advertising 100M-HD"); + ELINK_DEBUG_P0(sc, "Advertising 100M-HD"); } if ((phy->speed_cap_mask & @@ -9220,7 +10831,7 @@ static elink_status_t elink_848xx_cmn_config_init(struct elink_phy *phy, (phy->supported & ELINK_SUPPORTED_10baseT_Full)) { an_10_100_val |= (1 << 6); autoneg_val |= (1 << 9 | 1 << 12); - PMD_DRV_LOG(DEBUG, "Advertising 10M-FD"); + ELINK_DEBUG_P0(sc, "Advertising 10M-FD"); } if ((phy->speed_cap_mask & @@ -9228,14 +10839,15 @@ static elink_status_t elink_848xx_cmn_config_init(struct elink_phy *phy, (phy->supported & ELINK_SUPPORTED_10baseT_Half)) { an_10_100_val |= (1 << 5); autoneg_val |= (1 << 9 | 1 << 12); - PMD_DRV_LOG(DEBUG, "Advertising 10M-HD"); + ELINK_DEBUG_P0(sc, "Advertising 10M-HD"); } } /* Only 10/100 are allowed to work in FORCE mode */ if ((phy->req_line_speed == ELINK_SPEED_100) && (phy->supported & - (ELINK_SUPPORTED_100baseT_Half | ELINK_SUPPORTED_100baseT_Full))) { + (ELINK_SUPPORTED_100baseT_Half | + ELINK_SUPPORTED_100baseT_Full))) { autoneg_val |= (1 << 13); /* Enabled AUTO-MDIX when autoneg is disabled */ elink_cl45_write(sc, phy, @@ -9243,16 +10855,17 @@ static elink_status_t elink_848xx_cmn_config_init(struct elink_phy *phy, (1 << 15 | 1 << 9 | 7 << 0)); /* The PHY needs this set even for forced link. */ an_10_100_val |= (1 << 8) | (1 << 7); - PMD_DRV_LOG(DEBUG, "Setting 100M force"); + ELINK_DEBUG_P0(sc, "Setting 100M force"); } if ((phy->req_line_speed == ELINK_SPEED_10) && (phy->supported & - (ELINK_SUPPORTED_10baseT_Half | ELINK_SUPPORTED_10baseT_Full))) { + (ELINK_SUPPORTED_10baseT_Half | + ELINK_SUPPORTED_10baseT_Full))) { /* Enabled AUTO-MDIX when autoneg is disabled */ elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL, (1 << 15 | 1 << 9 | 7 << 0)); - PMD_DRV_LOG(DEBUG, "Setting 10M force"); + ELINK_DEBUG_P0(sc, "Setting 10M force"); } elink_cl45_write(sc, phy, @@ -9265,42 +10878,44 @@ static elink_status_t elink_848xx_cmn_config_init(struct elink_phy *phy, /* Always write this if this is not 84833/4. * For 84833/4, write it only when it's a forced speed. */ - if (((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) && - (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) || + if (!elink_is_8483x_8485x(phy) || ((autoneg_val & (1 << 12)) == 0)) elink_cl45_write(sc, phy, - MDIO_AN_DEVAD, - MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val); + MDIO_AN_DEVAD, + MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val); if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) && (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) || (phy->req_line_speed == ELINK_SPEED_10000)) { - PMD_DRV_LOG(DEBUG, "Advertising 10G"); - /* Restart autoneg for 10G */ + ELINK_DEBUG_P0(sc, "Advertising 10G"); + /* Restart autoneg for 10G*/ - elink_cl45_read_or_write(sc, phy, - MDIO_AN_DEVAD, - MDIO_AN_REG_8481_10GBASE_T_AN_CTRL, - 0x1000); + elink_cl45_read_or_write( + sc, phy, + MDIO_AN_DEVAD, + MDIO_AN_REG_8481_10GBASE_T_AN_CTRL, + 0x1000); elink_cl45_write(sc, phy, - MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x3200); + MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, + 0x3200); } else elink_cl45_write(sc, phy, MDIO_AN_DEVAD, - MDIO_AN_REG_8481_10GBASE_T_AN_CTRL, 1); + MDIO_AN_REG_8481_10GBASE_T_AN_CTRL, + 1); return ELINK_STATUS_OK; } static uint8_t elink_8481_config_init(struct elink_phy *phy, - struct elink_params *params, - struct elink_vars *vars) + struct elink_params *params, + struct elink_vars *vars) { struct bnx2x_softc *sc = params->sc; - /* Restore normal power mode */ + /* Restore normal power mode*/ elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2, - MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); + MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); /* HW reset */ elink_ext_phy_hw_reset(sc, params->port); @@ -9310,101 +10925,219 @@ static uint8_t elink_8481_config_init(struct elink_phy *phy, return elink_848xx_cmn_config_init(phy, params, vars); } -#define PHY84833_CMDHDLR_WAIT 300 -#define PHY84833_CMDHDLR_MAX_ARGS 5 -static elink_status_t elink_84833_cmd_hdlr(struct elink_phy *phy, +#define PHY848xx_CMDHDLR_WAIT 300 +#define PHY848xx_CMDHDLR_MAX_ARGS 5 + +static elink_status_t elink_84858_cmd_hdlr(struct elink_phy *phy, struct elink_params *params, - uint16_t fw_cmd, uint16_t cmd_args[], - int argc) + uint16_t fw_cmd, + uint16_t cmd_args[], int argc) { int idx; uint16_t val; struct bnx2x_softc *sc = params->sc; + + /* Step 1: Poll the STATUS register to see whether the previous command + * is in progress or the system is busy (CMD_IN_PROGRESS or + * SYSTEM_BUSY). If previous command is in progress or system is busy, + * check again until the previous command finishes execution and the + * system is available for taking command + */ + + for (idx = 0; idx < PHY848xx_CMDHDLR_WAIT; idx++) { + elink_cl45_read(sc, phy, MDIO_CTL_DEVAD, + MDIO_848xx_CMD_HDLR_STATUS, &val); + if ((val != PHY84858_STATUS_CMD_IN_PROGRESS) && + (val != PHY84858_STATUS_CMD_SYSTEM_BUSY)) + break; + DELAY(1000 * 1); + } + if (idx >= PHY848xx_CMDHDLR_WAIT) { + ELINK_DEBUG_P0(sc, "FW cmd: FW not ready."); + return ELINK_STATUS_ERROR; + } + + /* Step2: If any parameters are required for the function, write them + * to the required DATA registers + */ + + for (idx = 0; idx < argc; idx++) { + elink_cl45_write(sc, phy, MDIO_CTL_DEVAD, + MDIO_848xx_CMD_HDLR_DATA1 + idx, + cmd_args[idx]); + } + + /* Step3: When the firmware is ready for commands, write the 'Command + * code' to the CMD register + */ + elink_cl45_write(sc, phy, MDIO_CTL_DEVAD, + MDIO_848xx_CMD_HDLR_COMMAND, fw_cmd); + + /* Step4: Once the command has been written, poll the STATUS register + * to check whether the command has completed (CMD_COMPLETED_PASS/ + * CMD_FOR_CMDS or CMD_COMPLETED_ERROR). + */ + + for (idx = 0; idx < PHY848xx_CMDHDLR_WAIT; idx++) { + elink_cl45_read(sc, phy, MDIO_CTL_DEVAD, + MDIO_848xx_CMD_HDLR_STATUS, &val); + if ((val == PHY84858_STATUS_CMD_COMPLETE_PASS) || + (val == PHY84858_STATUS_CMD_COMPLETE_ERROR)) + break; + DELAY(1000 * 1); + } + if ((idx >= PHY848xx_CMDHDLR_WAIT) || + (val == PHY84858_STATUS_CMD_COMPLETE_ERROR)) { + ELINK_DEBUG_P0(sc, "FW cmd failed."); + return ELINK_STATUS_ERROR; + } + /* Step5: Once the command has completed, read the specficied DATA + * registers for any saved results for the command, if applicable + */ + + /* Gather returning data */ + for (idx = 0; idx < argc; idx++) { + elink_cl45_read(sc, phy, MDIO_CTL_DEVAD, + MDIO_848xx_CMD_HDLR_DATA1 + idx, + &cmd_args[idx]); + } + + return ELINK_STATUS_OK; +} + +static elink_status_t elink_84833_cmd_hdlr(struct elink_phy *phy, + struct elink_params *params, uint16_t fw_cmd, + uint16_t cmd_args[], int argc, int process) +{ + int idx; + uint16_t val; + struct bnx2x_softc *sc = params->sc; + elink_status_t rc = ELINK_STATUS_OK; + + if (process == PHY84833_MB_PROCESS2) { /* Write CMD_OPEN_OVERRIDE to STATUS reg */ elink_cl45_write(sc, phy, MDIO_CTL_DEVAD, - MDIO_84833_CMD_HDLR_STATUS, - PHY84833_STATUS_CMD_OPEN_OVERRIDE); - for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) { + MDIO_848xx_CMD_HDLR_STATUS, + PHY84833_STATUS_CMD_OPEN_OVERRIDE); + } + + for (idx = 0; idx < PHY848xx_CMDHDLR_WAIT; idx++) { elink_cl45_read(sc, phy, MDIO_CTL_DEVAD, - MDIO_84833_CMD_HDLR_STATUS, &val); + MDIO_848xx_CMD_HDLR_STATUS, &val); if (val == PHY84833_STATUS_CMD_OPEN_FOR_CMDS) break; DELAY(1000 * 1); } - if (idx >= PHY84833_CMDHDLR_WAIT) { - PMD_DRV_LOG(DEBUG, "FW cmd: FW not ready."); + if (idx >= PHY848xx_CMDHDLR_WAIT) { + ELINK_DEBUG_P0(sc, "FW cmd: FW not ready."); + /* if the status is CMD_COMPLETE_PASS or CMD_COMPLETE_ERROR + * clear the status to CMD_CLEAR_COMPLETE + */ + if (val == PHY84833_STATUS_CMD_COMPLETE_PASS || + val == PHY84833_STATUS_CMD_COMPLETE_ERROR) { + elink_cl45_write(sc, phy, MDIO_CTL_DEVAD, + MDIO_848xx_CMD_HDLR_STATUS, + PHY84833_STATUS_CMD_CLEAR_COMPLETE); + } return ELINK_STATUS_ERROR; } - - /* Prepare argument(s) and issue command */ + if (process == PHY84833_MB_PROCESS1 || + process == PHY84833_MB_PROCESS2) { + /* Prepare argument(s) */ for (idx = 0; idx < argc; idx++) { elink_cl45_write(sc, phy, MDIO_CTL_DEVAD, - MDIO_84833_CMD_HDLR_DATA1 + idx, - cmd_args[idx]); + MDIO_848xx_CMD_HDLR_DATA1 + idx, + cmd_args[idx]); + } } + + /* Issue command */ elink_cl45_write(sc, phy, MDIO_CTL_DEVAD, - MDIO_84833_CMD_HDLR_COMMAND, fw_cmd); - for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) { + MDIO_848xx_CMD_HDLR_COMMAND, fw_cmd); + for (idx = 0; idx < PHY848xx_CMDHDLR_WAIT; idx++) { elink_cl45_read(sc, phy, MDIO_CTL_DEVAD, - MDIO_84833_CMD_HDLR_STATUS, &val); + MDIO_848xx_CMD_HDLR_STATUS, &val); if ((val == PHY84833_STATUS_CMD_COMPLETE_PASS) || - (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) + (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) break; DELAY(1000 * 1); } - if ((idx >= PHY84833_CMDHDLR_WAIT) || - (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) { - PMD_DRV_LOG(DEBUG, "FW cmd failed."); - return ELINK_STATUS_ERROR; + if ((idx >= PHY848xx_CMDHDLR_WAIT) || + (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) { + ELINK_DEBUG_P0(sc, "FW cmd failed."); + rc = ELINK_STATUS_ERROR; } + if (process == PHY84833_MB_PROCESS3 && rc == ELINK_STATUS_OK) { /* Gather returning data */ for (idx = 0; idx < argc; idx++) { elink_cl45_read(sc, phy, MDIO_CTL_DEVAD, - MDIO_84833_CMD_HDLR_DATA1 + idx, + MDIO_848xx_CMD_HDLR_DATA1 + idx, &cmd_args[idx]); } + } + if (val == PHY84833_STATUS_CMD_COMPLETE_ERROR || + val == PHY84833_STATUS_CMD_COMPLETE_PASS) { elink_cl45_write(sc, phy, MDIO_CTL_DEVAD, - MDIO_84833_CMD_HDLR_STATUS, - PHY84833_STATUS_CMD_CLEAR_COMPLETE); - return ELINK_STATUS_OK; + MDIO_848xx_CMD_HDLR_STATUS, + PHY84833_STATUS_CMD_CLEAR_COMPLETE); + } + return rc; } -static elink_status_t elink_84833_pair_swap_cfg(struct elink_phy *phy, - struct elink_params *params, - __rte_unused struct elink_vars - *vars) +static elink_status_t elink_848xx_cmd_hdlr(struct elink_phy *phy, + struct elink_params *params, + uint16_t fw_cmd, + uint16_t cmd_args[], int argc, + int process) +{ + struct bnx2x_softc *sc = params->sc; + + if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84858) || + (REG_RD(sc, params->shmem2_base + + offsetof(struct shmem2_region, + link_attr_sync[params->port])) & + LINK_ATTR_84858)) { + return elink_84858_cmd_hdlr(phy, params, fw_cmd, cmd_args, + argc); + } else { + return elink_84833_cmd_hdlr(phy, params, fw_cmd, cmd_args, + argc, process); + } +} + +static elink_status_t elink_848xx_pair_swap_cfg(struct elink_phy *phy, + struct elink_params *params, + __rte_unused struct elink_vars *vars) { uint32_t pair_swap; - uint16_t data[PHY84833_CMDHDLR_MAX_ARGS]; + uint16_t data[PHY848xx_CMDHDLR_MAX_ARGS]; elink_status_t status; struct bnx2x_softc *sc = params->sc; /* Check for configuration. */ pair_swap = REG_RD(sc, params->shmem_base + offsetof(struct shmem_region, - dev_info.port_hw_config[params->port]. - xgbt_phy_cfg)) & - PORT_HW_CFG_RJ45_PAIR_SWAP_MASK; + dev_info.port_hw_config[params->port].xgbt_phy_cfg)) & + PORT_HW_CFG_RJ45_PAIR_SWAP_MASK; if (pair_swap == 0) return ELINK_STATUS_OK; /* Only the second argument is used for this command */ - data[1] = (uint16_t) pair_swap; + data[1] = (uint16_t)pair_swap; - status = elink_84833_cmd_hdlr(phy, params, - PHY84833_CMD_SET_PAIR_SWAP, data, - PHY84833_CMDHDLR_MAX_ARGS); - if (status == ELINK_STATUS_OK) { - PMD_DRV_LOG(DEBUG, "Pairswap OK, val=0x%x", data[1]); - } + status = elink_848xx_cmd_hdlr(phy, params, + PHY848xx_CMD_SET_PAIR_SWAP, data, + 2, PHY84833_MB_PROCESS2); + if (status == ELINK_STATUS_OK) + ELINK_DEBUG_P1(sc, "Pairswap OK, val=0x%x", data[1]); return status; } static uint8_t elink_84833_get_reset_gpios(struct bnx2x_softc *sc, - uint32_t shmem_base_path[], - __rte_unused uint32_t chip_id) + uint32_t shmem_base_path[], + __rte_unused uint32_t chip_id) { uint32_t reset_pin[2]; uint32_t idx; @@ -9414,54 +11147,50 @@ static uint8_t elink_84833_get_reset_gpios(struct bnx2x_softc *sc, for (idx = 0; idx < 2; idx++) { /* Map config param to register bit. */ reset_pin[idx] = REG_RD(sc, shmem_base_path[idx] + - offsetof(struct shmem_region, - dev_info. - port_hw_config[0]. - e3_cmn_pin_cfg)); - reset_pin[idx] = - (reset_pin[idx] & PORT_HW_CFG_E3_PHY_RESET_MASK) >> - PORT_HW_CFG_E3_PHY_RESET_SHIFT; + offsetof(struct shmem_region, + dev_info.port_hw_config[0].e3_cmn_pin_cfg)); + reset_pin[idx] = (reset_pin[idx] & + PORT_HW_CFG_E3_PHY_RESET_MASK) >> + PORT_HW_CFG_E3_PHY_RESET_SHIFT; reset_pin[idx] -= PIN_CFG_GPIO0_P0; reset_pin[idx] = (1 << reset_pin[idx]); } - reset_gpios = (uint8_t) (reset_pin[0] | reset_pin[1]); + reset_gpios = (uint8_t)(reset_pin[0] | reset_pin[1]); } else { /* E2, look from diff place of shmem. */ for (idx = 0; idx < 2; idx++) { reset_pin[idx] = REG_RD(sc, shmem_base_path[idx] + - offsetof(struct shmem_region, - dev_info. - port_hw_config[0]. - default_cfg)); + offsetof(struct shmem_region, + dev_info.port_hw_config[0].default_cfg)); reset_pin[idx] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK; reset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0; reset_pin[idx] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT; reset_pin[idx] = (1 << reset_pin[idx]); } - reset_gpios = (uint8_t) (reset_pin[0] | reset_pin[1]); + reset_gpios = (uint8_t)(reset_pin[0] | reset_pin[1]); } return reset_gpios; } static void elink_84833_hw_reset_phy(struct elink_phy *phy, - struct elink_params *params) + struct elink_params *params) { struct bnx2x_softc *sc = params->sc; uint8_t reset_gpios; uint32_t other_shmem_base_addr = REG_RD(sc, params->shmem2_base + - offsetof(struct shmem2_region, - other_shmem_base_addr)); + offsetof(struct shmem2_region, + other_shmem_base_addr)); uint32_t shmem_base_path[2]; /* Work around for 84833 LED failure inside RESET status */ elink_cl45_write(sc, phy, MDIO_AN_DEVAD, - MDIO_AN_REG_8481_LEGACY_MII_CTRL, - MDIO_AN_REG_8481_MII_CTRL_FORCE_1G); + MDIO_AN_REG_8481_LEGACY_MII_CTRL, + MDIO_AN_REG_8481_MII_CTRL_FORCE_1G); elink_cl45_write(sc, phy, MDIO_AN_DEVAD, - MDIO_AN_REG_8481_1G_100T_EXT_CTRL, - MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF); + MDIO_AN_REG_8481_1G_100T_EXT_CTRL, + MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF); shmem_base_path[0] = params->shmem_base; shmem_base_path[1] = other_shmem_base_addr; @@ -9472,23 +11201,25 @@ static void elink_84833_hw_reset_phy(struct elink_phy *phy, elink_cb_gpio_mult_write(sc, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW); DELAY(10); - PMD_DRV_LOG(DEBUG, "84833 hw reset on pin values 0x%x", reset_gpios); + ELINK_DEBUG_P1(sc, "84833 hw reset on pin values 0x%x", + reset_gpios); } static elink_status_t elink_8483x_disable_eee(struct elink_phy *phy, - struct elink_params *params, - struct elink_vars *vars) + struct elink_params *params, + struct elink_vars *vars) { elink_status_t rc; + struct bnx2x_softc *sc = params->sc; uint16_t cmd_args = 0; - PMD_DRV_LOG(DEBUG, "Don't Advertise 10GBase-T EEE"); + ELINK_DEBUG_P0(sc, "Don't Advertise 10GBase-T EEE"); /* Prevent Phy from working in EEE and advertising it */ - rc = elink_84833_cmd_hdlr(phy, params, - PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1); + rc = elink_848xx_cmd_hdlr(phy, params, PHY848xx_CMD_SET_EEE_MODE, + &cmd_args, 1, PHY84833_MB_PROCESS1); if (rc != ELINK_STATUS_OK) { - PMD_DRV_LOG(DEBUG, "EEE disable failed."); + ELINK_DEBUG_P0(sc, "EEE disable failed."); return rc; } @@ -9496,16 +11227,17 @@ static elink_status_t elink_8483x_disable_eee(struct elink_phy *phy, } static elink_status_t elink_8483x_enable_eee(struct elink_phy *phy, - struct elink_params *params, - struct elink_vars *vars) + struct elink_params *params, + struct elink_vars *vars) { elink_status_t rc; + struct bnx2x_softc *sc = params->sc; uint16_t cmd_args = 1; - rc = elink_84833_cmd_hdlr(phy, params, - PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1); + rc = elink_848xx_cmd_hdlr(phy, params, PHY848xx_CMD_SET_EEE_MODE, + &cmd_args, 1, PHY84833_MB_PROCESS1); if (rc != ELINK_STATUS_OK) { - PMD_DRV_LOG(DEBUG, "EEE enable failed."); + ELINK_DEBUG_P0(sc, "EEE enable failed."); return rc; } @@ -9514,14 +11246,14 @@ static elink_status_t elink_8483x_enable_eee(struct elink_phy *phy, #define PHY84833_CONSTANT_LATENCY 1193 static uint8_t elink_848x3_config_init(struct elink_phy *phy, - struct elink_params *params, - struct elink_vars *vars) + struct elink_params *params, + struct elink_vars *vars) { struct bnx2x_softc *sc = params->sc; uint8_t port, initialize = 1; uint16_t val; uint32_t actual_phy_selection; - uint16_t cmd_args[PHY84833_CMDHDLR_MAX_ARGS]; + uint16_t cmd_args[PHY848xx_CMDHDLR_MAX_ARGS]; elink_status_t rc = ELINK_STATUS_OK; DELAY(1000 * 1); @@ -9533,19 +11265,20 @@ static uint8_t elink_848x3_config_init(struct elink_phy *phy, if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84823) { elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_3, - MISC_REGISTERS_GPIO_OUTPUT_HIGH, port); + MISC_REGISTERS_GPIO_OUTPUT_HIGH, + port); } else { /* MDIO reset */ elink_cl45_write(sc, phy, - MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x8000); + MDIO_PMA_DEVAD, + MDIO_PMA_REG_CTRL, 0x8000); } elink_wait_reset_complete(sc, phy, params); /* Wait for GPHY to come out of reset */ DELAY(1000 * 50); - if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) && - (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) { + if (!elink_is_8483x_8485x(phy)) { /* BNX2X84823 requires that XGXS links up first @ 10G for normal * behavior. */ @@ -9556,7 +11289,19 @@ static uint8_t elink_848x3_config_init(struct elink_phy *phy, elink_program_serdes(¶ms->phy[ELINK_INT_PHY], params, vars); vars->line_speed = temp; } + /* Check if this is actually BNX2X84858 */ + if (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84858) { + uint16_t hw_rev; + + elink_cl45_read(sc, phy, MDIO_AN_DEVAD, + MDIO_AN_REG_848xx_ID_MSB, &hw_rev); + if (hw_rev == BNX2X84858_PHY_ID) { + params->link_attr_sync |= LINK_ATTR_84858; + elink_update_link_attr(params, params->link_attr_sync); + } + } + /* Set dual-media configuration according to configuration */ elink_cl45_read(sc, phy, MDIO_CTL_DEVAD, MDIO_CTL_REG_84823_MEDIA, &val); val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK | @@ -9598,39 +11343,33 @@ static uint8_t elink_848x3_config_init(struct elink_phy *phy, elink_cl45_write(sc, phy, MDIO_CTL_DEVAD, MDIO_CTL_REG_84823_MEDIA, val); - PMD_DRV_LOG(DEBUG, "Multi_phy config = 0x%x, Media control = 0x%x", - params->multi_phy_config, val); + ELINK_DEBUG_P2(sc, "Multi_phy config = 0x%x, Media control = 0x%x", + params->multi_phy_config, val); - if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) || - (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) { - elink_84833_pair_swap_cfg(phy, params, vars); + if (elink_is_8483x_8485x(phy)) { + elink_848xx_pair_swap_cfg(phy, params, vars); /* Keep AutogrEEEn disabled. */ cmd_args[0] = 0x0; cmd_args[1] = 0x0; cmd_args[2] = PHY84833_CONSTANT_LATENCY + 1; cmd_args[3] = PHY84833_CONSTANT_LATENCY; - rc = elink_84833_cmd_hdlr(phy, params, - PHY84833_CMD_SET_EEE_MODE, cmd_args, - PHY84833_CMDHDLR_MAX_ARGS); - if (rc != ELINK_STATUS_OK) { - PMD_DRV_LOG(DEBUG, "Cfg AutogrEEEn failed."); - } + rc = elink_848xx_cmd_hdlr(phy, params, + PHY848xx_CMD_SET_EEE_MODE, cmd_args, + 4, PHY84833_MB_PROCESS1); + if (rc != ELINK_STATUS_OK) + ELINK_DEBUG_P0(sc, "Cfg AutogrEEEn failed."); } - if (initialize) { + if (initialize) rc = elink_848xx_cmn_config_init(phy, params, vars); - } else { + else elink_save_848xx_spirom_version(phy, sc, params->port); - } /* 84833 PHY has a better feature and doesn't need to support this. */ if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84823) { uint32_t cms_enable = REG_RD(sc, params->shmem_base + - offsetof(struct shmem_region, - dev_info. - port_hw_config[params-> - port]. - default_cfg)) & - PORT_HW_CFG_ENABLE_CMS_MASK; + offsetof(struct shmem_region, + dev_info.port_hw_config[params->port].default_cfg)) & + PORT_HW_CFG_ENABLE_CMS_MASK; elink_cl45_read(sc, phy, MDIO_CTL_DEVAD, MDIO_CTL_REG_84823_USER_CTRL_REG, &val); @@ -9651,7 +11390,7 @@ static uint8_t elink_848x3_config_init(struct elink_phy *phy, elink_eee_has_cap(params)) { rc = elink_eee_initial_config(params, vars, SHMEM_EEE_10G_ADV); if (rc != ELINK_STATUS_OK) { - PMD_DRV_LOG(DEBUG, "Failed to configure EEE timers"); + ELINK_DEBUG_P0(sc, "Failed to configure EEE timers"); elink_8483x_disable_eee(phy, params, vars); return rc; } @@ -9664,39 +11403,40 @@ static uint8_t elink_848x3_config_init(struct elink_phy *phy, else rc = elink_8483x_disable_eee(phy, params, vars); if (rc != ELINK_STATUS_OK) { - PMD_DRV_LOG(DEBUG, "Failed to set EEE advertisement"); + ELINK_DEBUG_P0(sc, "Failed to set EEE advertisement"); return rc; } } else { vars->eee_status &= ~SHMEM_EEE_SUPPORTED_MASK; } - if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) || - (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) { + if (elink_is_8483x_8485x(phy)) { /* Bring PHY out of super isolate mode as the final step. */ elink_cl45_read_and_write(sc, phy, MDIO_CTL_DEVAD, MDIO_84833_TOP_CFG_XGPHY_STRAP1, - (uint16_t) ~ - MDIO_84833_SUPER_ISOLATE); + (uint16_t)~MDIO_84833_SUPER_ISOLATE); } return rc; } static uint8_t elink_848xx_read_status(struct elink_phy *phy, - struct elink_params *params, - struct elink_vars *vars) + struct elink_params *params, + struct elink_vars *vars) { struct bnx2x_softc *sc = params->sc; uint16_t val, val1, val2; uint8_t link_up = 0; + /* Check 10G-BaseT link status */ /* Check PMD signal ok */ - elink_cl45_read(sc, phy, MDIO_AN_DEVAD, 0xFFFA, &val1); elink_cl45_read(sc, phy, - MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL, &val2); - PMD_DRV_LOG(DEBUG, "BNX2X848xx: PMD_SIGNAL 1.a811 = 0x%x", val2); + MDIO_AN_DEVAD, 0xFFFA, &val1); + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL, + &val2); + ELINK_DEBUG_P1(sc, "BNX2X848xx: PMD_SIGNAL 1.a811 = 0x%x", val2); /* Check link 10G */ if (val2 & (1 << 11)) { @@ -9704,8 +11444,8 @@ static uint8_t elink_848xx_read_status(struct elink_phy *phy, vars->duplex = DUPLEX_FULL; link_up = 1; elink_ext_phy_10G_an_resolve(sc, phy, vars); - } else { /* Check Legacy speed link */ - uint16_t legacy_status, legacy_speed, mii_ctrl; + } else { /* Check Legacy speed link */ + uint16_t legacy_status, legacy_speed; /* Enable expansion register 0x42 (Operation mode status) */ elink_cl45_write(sc, phy, @@ -9718,7 +11458,8 @@ static uint8_t elink_848xx_read_status(struct elink_phy *phy, MDIO_AN_REG_8481_EXPANSION_REG_RD_RW, &legacy_status); - PMD_DRV_LOG(DEBUG, "Legacy speed status = 0x%x", legacy_status); + ELINK_DEBUG_P1(sc, "Legacy speed status = 0x%x", + legacy_status); link_up = ((legacy_status & (1 << 11)) == (1 << 11)); legacy_speed = (legacy_status & (3 << 9)); if (legacy_speed == (0 << 9)) @@ -9727,13 +11468,15 @@ static uint8_t elink_848xx_read_status(struct elink_phy *phy, vars->line_speed = ELINK_SPEED_100; else if (legacy_speed == (2 << 9)) vars->line_speed = ELINK_SPEED_1000; - else { /* Should not happen: Treat as link down */ + else { /* Should not happen: Treat as link down */ vars->line_speed = 0; link_up = 0; } if (params->feature_config_flags & - ELINK_FEATURE_CONFIG_IEEE_PHY_TEST) { + ELINK_FEATURE_CONFIG_IEEE_PHY_TEST) { + uint16_t mii_ctrl; + elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL, @@ -9748,10 +11491,10 @@ static uint8_t elink_848xx_read_status(struct elink_phy *phy, else vars->duplex = DUPLEX_HALF; - PMD_DRV_LOG(DEBUG, - "Link is up in %dMbps, is_duplex_full= %d", - vars->line_speed, - (vars->duplex == DUPLEX_FULL)); + ELINK_DEBUG_P2(sc, + "Link is up in %dMbps, is_duplex_full= %d", + vars->line_speed, + (vars->duplex == DUPLEX_FULL)); /* Check legacy speed AN resolution */ elink_cl45_read(sc, phy, MDIO_AN_DEVAD, @@ -9759,19 +11502,19 @@ static uint8_t elink_848xx_read_status(struct elink_phy *phy, &val); if (val & (1 << 5)) vars->link_status |= - LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; + LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_EXPANSION, &val); if ((val & (1 << 0)) == 0) vars->link_status |= - LINK_STATUS_PARALLEL_DETECTION_USED; + LINK_STATUS_PARALLEL_DETECTION_USED; } } if (link_up) { - PMD_DRV_LOG(DEBUG, "BNX2X848x3: link speed is %d", - vars->line_speed); + ELINK_DEBUG_P1(sc, "BNX2X848x3: link speed is %d", + vars->line_speed); elink_ext_phy_resolve_fc(phy, params, vars); /* Read LP advertised speeds */ @@ -9779,48 +11522,47 @@ static uint8_t elink_848xx_read_status(struct elink_phy *phy, MDIO_AN_REG_CL37_FC_LP, &val); if (val & (1 << 5)) vars->link_status |= - LINK_STATUS_LINK_PARTNER_10THD_CAPABLE; + LINK_STATUS_LINK_PARTNER_10THD_CAPABLE; if (val & (1 << 6)) vars->link_status |= - LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE; + LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE; if (val & (1 << 7)) vars->link_status |= - LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE; + LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE; if (val & (1 << 8)) vars->link_status |= - LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE; + LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE; if (val & (1 << 9)) vars->link_status |= - LINK_STATUS_LINK_PARTNER_100T4_CAPABLE; + LINK_STATUS_LINK_PARTNER_100T4_CAPABLE; elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_1000T_STATUS, &val); if (val & (1 << 10)) vars->link_status |= - LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE; + LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE; if (val & (1 << 11)) vars->link_status |= - LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; + LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS, &val); if (val & (1 << 11)) vars->link_status |= - LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; + LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; /* Determine if EEE was negotiated */ - if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) || - (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) + if (elink_is_8483x_8485x(phy)) elink_eee_an_resolve(phy, params, vars); } return link_up; } -static uint8_t elink_848xx_format_ver(uint32_t raw_ver, uint8_t * str, - uint16_t * len) +static elink_status_t elink_848xx_format_ver(uint32_t raw_ver, uint8_t *str, + uint16_t *len) { elink_status_t status = ELINK_STATUS_OK; uint32_t spirom_ver; @@ -9833,17 +11575,18 @@ static void elink_8481_hw_reset(__rte_unused struct elink_phy *phy, struct elink_params *params) { elink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_1, - MISC_REGISTERS_GPIO_OUTPUT_LOW, 0); + MISC_REGISTERS_GPIO_OUTPUT_LOW, 0); elink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_1, - MISC_REGISTERS_GPIO_OUTPUT_LOW, 1); + MISC_REGISTERS_GPIO_OUTPUT_LOW, 1); } static void elink_8481_link_reset(struct elink_phy *phy, - struct elink_params *params) + struct elink_params *params) { elink_cl45_write(params->sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000); - elink_cl45_write(params->sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1); + elink_cl45_write(params->sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1); } static void elink_848x3_link_reset(struct elink_phy *phy, @@ -9860,7 +11603,8 @@ static void elink_848x3_link_reset(struct elink_phy *phy, if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84823) { elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_3, - MISC_REGISTERS_GPIO_OUTPUT_LOW, port); + MISC_REGISTERS_GPIO_OUTPUT_LOW, + port); } else { elink_cl45_read(sc, phy, MDIO_CTL_DEVAD, @@ -9877,47 +11621,52 @@ static void elink_848xx_set_link_led(struct elink_phy *phy, { struct bnx2x_softc *sc = params->sc; uint16_t val; - __rte_unused uint8_t port; + uint8_t port; if (!(CHIP_IS_E1x(sc))) port = SC_PATH(sc); else port = params->port; - switch (mode) { case ELINK_LED_MODE_OFF: - PMD_DRV_LOG(DEBUG, "Port 0x%x: LED MODE OFF", port); + ELINK_DEBUG_P1(sc, "Port 0x%x: LED MODE OFF", port); if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == SHARED_HW_CFG_LED_EXTPHY1) { /* Set LED masks */ elink_cl45_write(sc, phy, - MDIO_PMA_DEVAD, - MDIO_PMA_REG_8481_LED1_MASK, 0x0); + MDIO_PMA_DEVAD, + MDIO_PMA_REG_8481_LED1_MASK, + 0x0); elink_cl45_write(sc, phy, - MDIO_PMA_DEVAD, - MDIO_PMA_REG_8481_LED2_MASK, 0x0); + MDIO_PMA_DEVAD, + MDIO_PMA_REG_8481_LED2_MASK, + 0x0); elink_cl45_write(sc, phy, - MDIO_PMA_DEVAD, - MDIO_PMA_REG_8481_LED3_MASK, 0x0); + MDIO_PMA_DEVAD, + MDIO_PMA_REG_8481_LED3_MASK, + 0x0); elink_cl45_write(sc, phy, - MDIO_PMA_DEVAD, - MDIO_PMA_REG_8481_LED5_MASK, 0x0); + MDIO_PMA_DEVAD, + MDIO_PMA_REG_8481_LED5_MASK, + 0x0); } else { elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, - MDIO_PMA_REG_8481_LED1_MASK, 0x0); + MDIO_PMA_REG_8481_LED1_MASK, + 0x0); } break; case ELINK_LED_MODE_FRONT_PANEL_OFF: - PMD_DRV_LOG(DEBUG, "Port 0x%x: LED MODE FRONT PANEL OFF", port); + ELINK_DEBUG_P1(sc, "Port 0x%x: LED MODE FRONT PANEL OFF", + port); if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == SHARED_HW_CFG_LED_EXTPHY1) { @@ -9925,25 +11674,31 @@ static void elink_848xx_set_link_led(struct elink_phy *phy, /* Set LED masks */ elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, - MDIO_PMA_REG_8481_LED1_MASK, 0x0); + MDIO_PMA_REG_8481_LED1_MASK, + 0x0); elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, - MDIO_PMA_REG_8481_LED2_MASK, 0x0); + MDIO_PMA_REG_8481_LED2_MASK, + 0x0); elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, - MDIO_PMA_REG_8481_LED3_MASK, 0x0); + MDIO_PMA_REG_8481_LED3_MASK, + 0x0); elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, - MDIO_PMA_REG_8481_LED5_MASK, 0x20); + MDIO_PMA_REG_8481_LED5_MASK, + 0x20); } else { elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, - MDIO_PMA_REG_8481_LED1_MASK, 0x0); - if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834) { + MDIO_PMA_REG_8481_LED1_MASK, + 0x0); + if (phy->type == + PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834) { /* Disable MI_INT interrupt before setting LED4 * source to constant off. */ @@ -9951,12 +11706,13 @@ static void elink_848xx_set_link_led(struct elink_phy *phy, params->port * 4) & ELINK_NIG_MASK_MI_INT) { params->link_flags |= - ELINK_LINK_FLAGS_INT_DISABLED; + ELINK_LINK_FLAGS_INT_DISABLED; - elink_bits_dis(sc, - NIG_REG_MASK_INTERRUPT_PORT0 - + params->port * 4, - ELINK_NIG_MASK_MI_INT); + elink_bits_dis( + sc, + NIG_REG_MASK_INTERRUPT_PORT0 + + params->port * 4, + ELINK_NIG_MASK_MI_INT); } elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, @@ -9967,42 +11723,50 @@ static void elink_848xx_set_link_led(struct elink_phy *phy, break; case ELINK_LED_MODE_ON: - PMD_DRV_LOG(DEBUG, "Port 0x%x: LED MODE ON", port); + ELINK_DEBUG_P1(sc, "Port 0x%x: LED MODE ON", port); if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == SHARED_HW_CFG_LED_EXTPHY1) { /* Set control reg */ elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, - MDIO_PMA_REG_8481_LINK_SIGNAL, &val); + MDIO_PMA_REG_8481_LINK_SIGNAL, + &val); val &= 0x8000; val |= 0x2492; elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, - MDIO_PMA_REG_8481_LINK_SIGNAL, val); + MDIO_PMA_REG_8481_LINK_SIGNAL, + val); /* Set LED masks */ elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, - MDIO_PMA_REG_8481_LED1_MASK, 0x0); + MDIO_PMA_REG_8481_LED1_MASK, + 0x0); elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, - MDIO_PMA_REG_8481_LED2_MASK, 0x20); + MDIO_PMA_REG_8481_LED2_MASK, + 0x20); elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, - MDIO_PMA_REG_8481_LED3_MASK, 0x20); + MDIO_PMA_REG_8481_LED3_MASK, + 0x20); elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, - MDIO_PMA_REG_8481_LED5_MASK, 0x0); + MDIO_PMA_REG_8481_LED5_MASK, + 0x0); } else { elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, - MDIO_PMA_REG_8481_LED1_MASK, 0x20); - if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834) { + MDIO_PMA_REG_8481_LED1_MASK, + 0x20); + if (phy->type == + PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834) { /* Disable MI_INT interrupt before setting LED4 * source to constant on. */ @@ -10010,12 +11774,13 @@ static void elink_848xx_set_link_led(struct elink_phy *phy, params->port * 4) & ELINK_NIG_MASK_MI_INT) { params->link_flags |= - ELINK_LINK_FLAGS_INT_DISABLED; + ELINK_LINK_FLAGS_INT_DISABLED; - elink_bits_dis(sc, - NIG_REG_MASK_INTERRUPT_PORT0 - + params->port * 4, - ELINK_NIG_MASK_MI_INT); + elink_bits_dis( + sc, + NIG_REG_MASK_INTERRUPT_PORT0 + + params->port * 4, + ELINK_NIG_MASK_MI_INT); } elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, @@ -10027,7 +11792,7 @@ static void elink_848xx_set_link_led(struct elink_phy *phy, case ELINK_LED_MODE_OPER: - PMD_DRV_LOG(DEBUG, "Port 0x%x: LED MODE OPER", port); + ELINK_DEBUG_P1(sc, "Port 0x%x: LED MODE OPER", port); if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == SHARED_HW_CFG_LED_EXTPHY1) { @@ -10035,14 +11800,13 @@ static void elink_848xx_set_link_led(struct elink_phy *phy, /* Set control reg */ elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, - MDIO_PMA_REG_8481_LINK_SIGNAL, &val); + MDIO_PMA_REG_8481_LINK_SIGNAL, + &val); if (!((val & MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK) - >> - MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) - { - PMD_DRV_LOG(DEBUG, "Setting LINK_SIGNAL"); + >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) { + ELINK_DEBUG_P0(sc, "Setting LINK_SIGNAL"); elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LINK_SIGNAL, @@ -10052,19 +11816,23 @@ static void elink_848xx_set_link_led(struct elink_phy *phy, /* Set LED masks */ elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, - MDIO_PMA_REG_8481_LED1_MASK, 0x10); + MDIO_PMA_REG_8481_LED1_MASK, + 0x10); elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, - MDIO_PMA_REG_8481_LED2_MASK, 0x80); + MDIO_PMA_REG_8481_LED2_MASK, + 0x80); elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, - MDIO_PMA_REG_8481_LED3_MASK, 0x98); + MDIO_PMA_REG_8481_LED3_MASK, + 0x98); elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, - MDIO_PMA_REG_8481_LED5_MASK, 0x40); + MDIO_PMA_REG_8481_LED5_MASK, + 0x40); } else { /* EXTPHY2 LED mode indicate that the 100M/1G/10G LED @@ -10077,18 +11845,22 @@ static void elink_848xx_set_link_led(struct elink_phy *phy, elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, - MDIO_PMA_REG_8481_LED1_MASK, val); + MDIO_PMA_REG_8481_LED1_MASK, + val); /* Tell LED3 to blink on source */ elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, - MDIO_PMA_REG_8481_LINK_SIGNAL, &val); + MDIO_PMA_REG_8481_LINK_SIGNAL, + &val); val &= ~(7 << 6); - val |= (1 << 6); /* A83B[8:6]= 1 */ + val |= (1 << 6); /* A83B[8:6]= 1 */ elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, - MDIO_PMA_REG_8481_LINK_SIGNAL, val); - if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834) { + MDIO_PMA_REG_8481_LINK_SIGNAL, + val); + if (phy->type == + PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834) { /* Restore LED4 source to external link, * and re-enable interrupts. */ @@ -10100,14 +11872,14 @@ static void elink_848xx_set_link_led(struct elink_phy *phy, ELINK_LINK_FLAGS_INT_DISABLED) { elink_link_int_enable(params); params->link_flags &= - ~ELINK_LINK_FLAGS_INT_DISABLED; + ~ELINK_LINK_FLAGS_INT_DISABLED; } } } break; } - /* This is a workaround for E3+84833 until autoneg + /* This is a workaround for E3 + 84833 until autoneg * restart is fixed in f/w */ if (CHIP_IS_E3(sc)) { @@ -10132,7 +11904,9 @@ static void elink_54618se_specific_func(struct elink_phy *phy, elink_cl22_write(sc, phy, MDIO_REG_GPHY_SHADOW, MDIO_REG_GPHY_SHADOW_LED_SEL2); - elink_cl22_read(sc, phy, MDIO_REG_GPHY_SHADOW, &temp); + elink_cl22_read(sc, phy, + MDIO_REG_GPHY_SHADOW, + &temp); temp &= ~(0xf << 4); temp |= (0x6 << 4); elink_cl22_write(sc, phy, @@ -10147,15 +11921,15 @@ static void elink_54618se_specific_func(struct elink_phy *phy, } static uint8_t elink_54618se_config_init(struct elink_phy *phy, - struct elink_params *params, - struct elink_vars *vars) + struct elink_params *params, + struct elink_vars *vars) { struct bnx2x_softc *sc = params->sc; uint8_t port; uint16_t autoneg_val, an_1000_val, an_10_100_val, fc_val, temp; uint32_t cfg_pin; - PMD_DRV_LOG(DEBUG, "54618SE cfg init"); + ELINK_DEBUG_P0(sc, "54618SE cfg init"); DELAY(1000 * 1); /* This works with E3 only, no need to check the chip @@ -10164,11 +11938,10 @@ static uint8_t elink_54618se_config_init(struct elink_phy *phy, port = params->port; cfg_pin = (REG_RD(sc, params->shmem_base + - offsetof(struct shmem_region, - dev_info.port_hw_config[port]. - e3_cmn_pin_cfg)) & - PORT_HW_CFG_E3_PHY_RESET_MASK) >> - PORT_HW_CFG_E3_PHY_RESET_SHIFT; + offsetof(struct shmem_region, + dev_info.port_hw_config[port].e3_cmn_pin_cfg)) & + PORT_HW_CFG_E3_PHY_RESET_MASK) >> + PORT_HW_CFG_E3_PHY_RESET_SHIFT; /* Drive pin high to bring the GPHY out of reset. */ elink_set_cfg_pin(sc, cfg_pin, 1); @@ -10177,63 +11950,76 @@ static uint8_t elink_54618se_config_init(struct elink_phy *phy, DELAY(1000 * 50); /* reset phy */ - elink_cl22_write(sc, phy, MDIO_PMA_REG_CTRL, 0x8000); + elink_cl22_write(sc, phy, + MDIO_PMA_REG_CTRL, 0x8000); elink_wait_reset_complete(sc, phy, params); /* Wait for GPHY to reset */ DELAY(1000 * 50); + elink_54618se_specific_func(phy, params, ELINK_PHY_INIT); /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */ elink_cl22_write(sc, phy, - MDIO_REG_GPHY_SHADOW, - MDIO_REG_GPHY_SHADOW_AUTO_DET_MED); - elink_cl22_read(sc, phy, MDIO_REG_GPHY_SHADOW, &temp); + MDIO_REG_GPHY_SHADOW, + MDIO_REG_GPHY_SHADOW_AUTO_DET_MED); + elink_cl22_read(sc, phy, + MDIO_REG_GPHY_SHADOW, + &temp); temp |= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD; elink_cl22_write(sc, phy, - MDIO_REG_GPHY_SHADOW, - MDIO_REG_GPHY_SHADOW_WR_ENA | temp); + MDIO_REG_GPHY_SHADOW, + MDIO_REG_GPHY_SHADOW_WR_ENA | temp); /* Set up fc */ /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); fc_val = 0; if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) == - MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) + MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) fc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC; if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) == - MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) + MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) fc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE; /* Read all advertisement */ - elink_cl22_read(sc, phy, 0x09, &an_1000_val); + elink_cl22_read(sc, phy, + 0x09, + &an_1000_val); - elink_cl22_read(sc, phy, 0x04, &an_10_100_val); + elink_cl22_read(sc, phy, + 0x04, + &an_10_100_val); - elink_cl22_read(sc, phy, MDIO_PMA_REG_CTRL, &autoneg_val); + elink_cl22_read(sc, phy, + MDIO_PMA_REG_CTRL, + &autoneg_val); /* Disable forced speed */ - autoneg_val &= - ~((1 << 6) | (1 << 8) | (1 << 9) | (1 << 12) | (1 << 13)); - an_10_100_val &= - ~((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 10) | - (1 << 11)); + autoneg_val &= ~((1 << 6) | (1 << 8) | (1 << 9) | (1 << 12) | + (1 << 13)); + an_10_100_val &= ~((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) | + (1 << 10) | (1 << 11)); if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) && - (phy->speed_cap_mask & - PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || - (phy->req_line_speed == ELINK_SPEED_1000)) { + (phy->speed_cap_mask & + PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || + (phy->req_line_speed == ELINK_SPEED_1000)) { an_1000_val |= (1 << 8); autoneg_val |= (1 << 9 | 1 << 12); if (phy->req_duplex == DUPLEX_FULL) an_1000_val |= (1 << 9); - PMD_DRV_LOG(DEBUG, "Advertising 1G"); + ELINK_DEBUG_P0(sc, "Advertising 1G"); } else an_1000_val &= ~((1 << 8) | (1 << 9)); - elink_cl22_write(sc, phy, 0x09, an_1000_val); - elink_cl22_read(sc, phy, 0x09, &an_1000_val); + elink_cl22_write(sc, phy, + 0x09, + an_1000_val); + elink_cl22_read(sc, phy, + 0x09, + &an_1000_val); /* Advertise 10/100 link speed */ if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) { @@ -10241,25 +12027,25 @@ static uint8_t elink_54618se_config_init(struct elink_phy *phy, PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) { an_10_100_val |= (1 << 5); autoneg_val |= (1 << 9 | 1 << 12); - PMD_DRV_LOG(DEBUG, "Advertising 10M-HD"); + ELINK_DEBUG_P0(sc, "Advertising 10M-HD"); } if (phy->speed_cap_mask & - PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) { + PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) { an_10_100_val |= (1 << 6); autoneg_val |= (1 << 9 | 1 << 12); - PMD_DRV_LOG(DEBUG, "Advertising 10M-FD"); + ELINK_DEBUG_P0(sc, "Advertising 10M-FD"); } if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) { an_10_100_val |= (1 << 7); autoneg_val |= (1 << 9 | 1 << 12); - PMD_DRV_LOG(DEBUG, "Advertising 100M-HD"); + ELINK_DEBUG_P0(sc, "Advertising 100M-HD"); } if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) { an_10_100_val |= (1 << 8); autoneg_val |= (1 << 9 | 1 << 12); - PMD_DRV_LOG(DEBUG, "Advertising 100M-FD"); + ELINK_DEBUG_P0(sc, "Advertising 100M-FD"); } } @@ -10267,13 +12053,17 @@ static uint8_t elink_54618se_config_init(struct elink_phy *phy, if (phy->req_line_speed == ELINK_SPEED_100) { autoneg_val |= (1 << 13); /* Enabled AUTO-MDIX when autoneg is disabled */ - elink_cl22_write(sc, phy, 0x18, (1 << 15 | 1 << 9 | 7 << 0)); - PMD_DRV_LOG(DEBUG, "Setting 100M force"); + elink_cl22_write(sc, phy, + 0x18, + (1 << 15 | 1 << 9 | 7 << 0)); + ELINK_DEBUG_P0(sc, "Setting 100M force"); } if (phy->req_line_speed == ELINK_SPEED_10) { /* Enabled AUTO-MDIX when autoneg is disabled */ - elink_cl22_write(sc, phy, 0x18, (1 << 15 | 1 << 9 | 7 << 0)); - PMD_DRV_LOG(DEBUG, "Setting 10M force"); + elink_cl22_write(sc, phy, + 0x18, + (1 << 15 | 1 << 9 | 7 << 0)); + ELINK_DEBUG_P0(sc, "Setting 10M force"); } if ((phy->flags & ELINK_FLAGS_EEE) && elink_eee_has_cap(params)) { @@ -10288,7 +12078,7 @@ static uint8_t elink_54618se_config_init(struct elink_phy *phy, rc = elink_eee_initial_config(params, vars, SHMEM_EEE_1G_ADV); if (rc != ELINK_STATUS_OK) { - PMD_DRV_LOG(DEBUG, "Failed to configure EEE timers"); + ELINK_DEBUG_P0(sc, "Failed to configure EEE timers"); elink_eee_disable(phy, params, vars); } else if ((params->eee_mode & ELINK_EEE_MODE_ADV_LPI) && (phy->req_duplex == DUPLEX_FULL) && @@ -10302,38 +12092,42 @@ static uint8_t elink_54618se_config_init(struct elink_phy *phy, elink_eee_advertise(phy, params, vars, SHMEM_EEE_1G_ADV); } else { - PMD_DRV_LOG(DEBUG, "Don't Advertise 1GBase-T EEE"); + ELINK_DEBUG_P0(sc, "Don't Advertise 1GBase-T EEE"); elink_eee_disable(phy, params, vars); } } else { - vars->eee_status &= ~SHMEM_EEE_1G_ADV << - SHMEM_EEE_SUPPORTED_SHIFT; + vars->eee_status &= ((uint32_t)(~SHMEM_EEE_1G_ADV) << + SHMEM_EEE_SUPPORTED_SHIFT); if (phy->flags & ELINK_FLAGS_EEE) { /* Handle legacy auto-grEEEn */ if (params->feature_config_flags & ELINK_FEATURE_CONFIG_AUTOGREEEN_ENABLED) { temp = 6; - PMD_DRV_LOG(DEBUG, "Enabling Auto-GrEEEn"); + ELINK_DEBUG_P0(sc, "Enabling Auto-GrEEEn"); } else { temp = 0; - PMD_DRV_LOG(DEBUG, "Don't Adv. EEE"); + ELINK_DEBUG_P0(sc, "Don't Adv. EEE"); } elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, temp); } } - elink_cl22_write(sc, phy, 0x04, an_10_100_val | fc_val); + elink_cl22_write(sc, phy, + 0x04, + an_10_100_val | fc_val); if (phy->req_duplex == DUPLEX_FULL) autoneg_val |= (1 << 8); - elink_cl22_write(sc, phy, MDIO_PMA_REG_CTRL, autoneg_val); + elink_cl22_write(sc, phy, + MDIO_PMA_REG_CTRL, autoneg_val); return ELINK_STATUS_OK; } + static void elink_5461x_set_link_led(struct elink_phy *phy, struct elink_params *params, uint8_t mode) { @@ -10341,11 +12135,14 @@ static void elink_5461x_set_link_led(struct elink_phy *phy, uint16_t temp; elink_cl22_write(sc, phy, - MDIO_REG_GPHY_SHADOW, MDIO_REG_GPHY_SHADOW_LED_SEL1); - elink_cl22_read(sc, phy, MDIO_REG_GPHY_SHADOW, &temp); + MDIO_REG_GPHY_SHADOW, + MDIO_REG_GPHY_SHADOW_LED_SEL1); + elink_cl22_read(sc, phy, + MDIO_REG_GPHY_SHADOW, + &temp); temp &= 0xff00; - PMD_DRV_LOG(DEBUG, "54618x set link led (mode=%x)", mode); + ELINK_DEBUG_P1(sc, "54618x set link led (mode=%x)", mode); switch (mode) { case ELINK_LED_MODE_FRONT_PANEL_OFF: case ELINK_LED_MODE_OFF: @@ -10361,11 +12158,12 @@ static void elink_5461x_set_link_led(struct elink_phy *phy, break; } elink_cl22_write(sc, phy, - MDIO_REG_GPHY_SHADOW, - MDIO_REG_GPHY_SHADOW_WR_ENA | temp); + MDIO_REG_GPHY_SHADOW, + MDIO_REG_GPHY_SHADOW_WR_ENA | temp); return; } + static void elink_54618se_link_reset(struct elink_phy *phy, struct elink_params *params) { @@ -10382,19 +12180,18 @@ static void elink_54618se_link_reset(struct elink_phy *phy, */ port = params->port; cfg_pin = (REG_RD(sc, params->shmem_base + - offsetof(struct shmem_region, - dev_info.port_hw_config[port]. - e3_cmn_pin_cfg)) & - PORT_HW_CFG_E3_PHY_RESET_MASK) >> - PORT_HW_CFG_E3_PHY_RESET_SHIFT; + offsetof(struct shmem_region, + dev_info.port_hw_config[port].e3_cmn_pin_cfg)) & + PORT_HW_CFG_E3_PHY_RESET_MASK) >> + PORT_HW_CFG_E3_PHY_RESET_SHIFT; /* Drive pin low to put GPHY in reset. */ elink_set_cfg_pin(sc, cfg_pin, 0); } static uint8_t elink_54618se_read_status(struct elink_phy *phy, - struct elink_params *params, - struct elink_vars *vars) + struct elink_params *params, + struct elink_vars *vars) { struct bnx2x_softc *sc = params->sc; uint16_t val; @@ -10402,11 +12199,15 @@ static uint8_t elink_54618se_read_status(struct elink_phy *phy, uint16_t legacy_status, legacy_speed; /* Get speed operation status */ - elink_cl22_read(sc, phy, MDIO_REG_GPHY_AUX_STATUS, &legacy_status); - PMD_DRV_LOG(DEBUG, "54618SE read_status: 0x%x", legacy_status); + elink_cl22_read(sc, phy, + MDIO_REG_GPHY_AUX_STATUS, + &legacy_status); + ELINK_DEBUG_P1(sc, "54618SE read_status: 0x%x", legacy_status); /* Read status to clear the PHY interrupt. */ - elink_cl22_read(sc, phy, MDIO_REG_INTR_STATUS, &val); + elink_cl22_read(sc, phy, + MDIO_REG_INTR_STATUS, + &val); link_up = ((legacy_status & (1 << 2)) == (1 << 2)); @@ -10432,25 +12233,30 @@ static uint8_t elink_54618se_read_status(struct elink_phy *phy, } else if (legacy_speed == (1 << 8)) { vars->line_speed = ELINK_SPEED_10; vars->duplex = DUPLEX_HALF; - } else /* Should not happen */ + } else /* Should not happen */ vars->line_speed = 0; - PMD_DRV_LOG(DEBUG, - "Link is up in %dMbps, is_duplex_full= %d", - vars->line_speed, (vars->duplex == DUPLEX_FULL)); + ELINK_DEBUG_P2(sc, + "Link is up in %dMbps, is_duplex_full= %d", + vars->line_speed, + (vars->duplex == DUPLEX_FULL)); /* Check legacy speed AN resolution */ - elink_cl22_read(sc, phy, 0x01, &val); + elink_cl22_read(sc, phy, + 0x01, + &val); if (val & (1 << 5)) vars->link_status |= - LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; - elink_cl22_read(sc, phy, 0x06, &val); + LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; + elink_cl22_read(sc, phy, + 0x06, + &val); if ((val & (1 << 0)) == 0) vars->link_status |= - LINK_STATUS_PARALLEL_DETECTION_USED; + LINK_STATUS_PARALLEL_DETECTION_USED; - PMD_DRV_LOG(DEBUG, "BNX2X54618SE: link speed is %d", - vars->line_speed); + ELINK_DEBUG_P1(sc, "BNX2X4618SE: link speed is %d", + vars->line_speed); elink_ext_phy_resolve_fc(phy, params, vars); @@ -10460,27 +12266,27 @@ static uint8_t elink_54618se_read_status(struct elink_phy *phy, if (val & (1 << 5)) vars->link_status |= - LINK_STATUS_LINK_PARTNER_10THD_CAPABLE; + LINK_STATUS_LINK_PARTNER_10THD_CAPABLE; if (val & (1 << 6)) vars->link_status |= - LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE; + LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE; if (val & (1 << 7)) vars->link_status |= - LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE; + LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE; if (val & (1 << 8)) vars->link_status |= - LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE; + LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE; if (val & (1 << 9)) vars->link_status |= - LINK_STATUS_LINK_PARTNER_100T4_CAPABLE; + LINK_STATUS_LINK_PARTNER_100T4_CAPABLE; elink_cl22_read(sc, phy, 0xa, &val); if (val & (1 << 10)) vars->link_status |= - LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE; + LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE; if (val & (1 << 11)) vars->link_status |= - LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; + LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; if ((phy->flags & ELINK_FLAGS_EEE) && elink_eee_has_cap(params)) @@ -10497,7 +12303,7 @@ static void elink_54618se_config_loopback(struct elink_phy *phy, uint16_t val; uint32_t umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; - PMD_DRV_LOG(DEBUG, "2PMA/PMD ext_phy_loopback: 54618se"); + ELINK_DEBUG_P0(sc, "2PMA/PMD ext_phy_loopback: 54618se"); /* Enable master/slave manual mmode and set to master */ /* mii write 9 [bits set 11 12] */ @@ -10543,30 +12349,33 @@ static void elink_7101_config_loopback(struct elink_phy *phy, } static uint8_t elink_7101_config_init(struct elink_phy *phy, - struct elink_params *params, - struct elink_vars *vars) + struct elink_params *params, + struct elink_vars *vars) { uint16_t fw_ver1, fw_ver2, val; struct bnx2x_softc *sc = params->sc; - PMD_DRV_LOG(DEBUG, "Setting the SFX7101 LASI indication"); + ELINK_DEBUG_P0(sc, "Setting the SFX7101 LASI indication"); - /* Restore normal power mode */ + /* Restore normal power mode*/ elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2, - MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); + MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); /* HW reset */ elink_ext_phy_hw_reset(sc, params->port); elink_wait_reset_complete(sc, phy, params); - elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1); - PMD_DRV_LOG(DEBUG, "Setting the SFX7101 LED to blink on traffic"); + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1); + ELINK_DEBUG_P0(sc, "Setting the SFX7101 LED to blink on traffic"); elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1 << 3)); elink_ext_phy_set_pause(params, phy, vars); /* Restart autoneg */ - elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val); + elink_cl45_read(sc, phy, + MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val); val |= 0x200; - elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val); + elink_cl45_write(sc, phy, + MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val); /* Save spirom version */ elink_cl45_read(sc, phy, @@ -10575,24 +12384,30 @@ static uint8_t elink_7101_config_init(struct elink_phy *phy, elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2); elink_save_spirom_version(sc, params->port, - (uint32_t) (fw_ver1 << 16 | fw_ver2), + (uint32_t)(fw_ver1 << 16 | fw_ver2), phy->ver_addr); return ELINK_STATUS_OK; } static uint8_t elink_7101_read_status(struct elink_phy *phy, - struct elink_params *params, - struct elink_vars *vars) + struct elink_params *params, + struct elink_vars *vars) { struct bnx2x_softc *sc = params->sc; uint8_t link_up; uint16_t val1, val2; - elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2); - elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); - PMD_DRV_LOG(DEBUG, "10G-base-T LASI status 0x%x->0x%x", val2, val1); - elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2); - elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1); - PMD_DRV_LOG(DEBUG, "10G-base-T PMA status 0x%x->0x%x", val2, val1); + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2); + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); + ELINK_DEBUG_P2(sc, "10G-base-T LASI status 0x%x->0x%x", + val2, val1); + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2); + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1); + ELINK_DEBUG_P2(sc, "10G-base-T PMA status 0x%x->0x%x", + val2, val1); link_up = ((val1 & 4) == 4); /* If link is up print the AN outcome of the SFX7101 PHY */ if (link_up) { @@ -10601,21 +12416,21 @@ static uint8_t elink_7101_read_status(struct elink_phy *phy, &val2); vars->line_speed = ELINK_SPEED_10000; vars->duplex = DUPLEX_FULL; - PMD_DRV_LOG(DEBUG, "SFX7101 AN status 0x%x->Master=%x", - val2, (val2 & (1 << 14))); + ELINK_DEBUG_P2(sc, "SFX7101 AN status 0x%x->Master=%x", + val2, (val2 & (1 << 14))); elink_ext_phy_10G_an_resolve(sc, phy, vars); elink_ext_phy_resolve_fc(phy, params, vars); /* Read LP advertised speeds */ if (val2 & (1 << 11)) vars->link_status |= - LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; + LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; } return link_up; } -static uint8_t elink_7101_format_ver(uint32_t spirom_ver, uint8_t * str, - uint16_t * len) +static elink_status_t elink_7101_format_ver(uint32_t spirom_ver, uint8_t *str, + uint16_t *len) { if (*len < 5) return ELINK_STATUS_ERROR; @@ -10628,15 +12443,39 @@ static uint8_t elink_7101_format_ver(uint32_t spirom_ver, uint8_t * str, return ELINK_STATUS_OK; } -static void elink_7101_hw_reset(__rte_unused struct elink_phy *phy, - struct elink_params *params) +void elink_sfx7101_sp_sw_reset(struct bnx2x_softc *sc, struct elink_phy *phy) { + uint16_t val, cnt; + + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_7101_RESET, &val); + + for (cnt = 0; cnt < 10; cnt++) { + DELAY(1000 * 50); + /* Writes a self-clearing reset */ + elink_cl45_write(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_7101_RESET, + (val | (1 << 15))); + /* Wait for clear */ + elink_cl45_read(sc, phy, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_7101_RESET, &val); + + if ((val & (1 << 15)) == 0) + break; + } +} + +static void elink_7101_hw_reset(__rte_unused struct elink_phy *phy, + struct elink_params *params) { /* Low power mode is controlled by GPIO 2 */ elink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_2, - MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port); + MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port); /* The PHY reset is controlled by GPIO 1 */ elink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_1, - MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port); + MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port); } static void elink_7101_set_link_led(struct elink_phy *phy, @@ -10657,7 +12496,9 @@ static void elink_7101_set_link_led(struct elink_phy *phy, break; } elink_cl45_write(sc, phy, - MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LINK_LED_CNTL, val); + MDIO_PMA_DEVAD, + MDIO_PMA_REG_7107_LINK_LED_CNTL, + val); } /******************************************************************/ @@ -10665,482 +12506,532 @@ static void elink_7101_set_link_led(struct elink_phy *phy, /******************************************************************/ static const struct elink_phy phy_null = { - .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN, - .addr = 0, - .def_md_devad = 0, - .flags = ELINK_FLAGS_INIT_XGXS_FIRST, - .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, - .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, - .mdio_ctrl = 0, - .supported = 0, - .media_type = ELINK_ETH_PHY_NOT_PRESENT, - .ver_addr = 0, - .req_flow_ctrl = 0, - .req_line_speed = 0, - .speed_cap_mask = 0, - .req_duplex = 0, - .rsrv = 0, - .config_init = NULL, - .read_status = NULL, - .link_reset = NULL, - .config_loopback = NULL, - .format_fw_ver = NULL, - .hw_reset = NULL, - .set_link_led = NULL, - .phy_specific_func = NULL + .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN, + .addr = 0, + .def_md_devad = 0, + .flags = ELINK_FLAGS_INIT_XGXS_FIRST, + .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, + .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, + .mdio_ctrl = 0, + .supported = 0, + .media_type = ELINK_ETH_PHY_NOT_PRESENT, + .ver_addr = 0, + .req_flow_ctrl = 0, + .req_line_speed = 0, + .speed_cap_mask = 0, + .req_duplex = 0, + .rsrv = 0, + .config_init = (config_init_t)NULL, + .read_status = (read_status_t)NULL, + .link_reset = (link_reset_t)NULL, + .config_loopback = (config_loopback_t)NULL, + .format_fw_ver = (format_fw_ver_t)NULL, + .hw_reset = (hw_reset_t)NULL, + .set_link_led = (set_link_led_t)NULL, + .phy_specific_func = (phy_specific_func_t)NULL }; static const struct elink_phy phy_serdes = { - .type = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT, - .addr = 0xff, - .def_md_devad = 0, - .flags = 0, - .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, - .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, - .mdio_ctrl = 0, - .supported = (ELINK_SUPPORTED_10baseT_Half | - ELINK_SUPPORTED_10baseT_Full | - ELINK_SUPPORTED_100baseT_Half | - ELINK_SUPPORTED_100baseT_Full | - ELINK_SUPPORTED_1000baseT_Full | - ELINK_SUPPORTED_2500baseX_Full | - ELINK_SUPPORTED_TP | - ELINK_SUPPORTED_Autoneg | - ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause), - .media_type = ELINK_ETH_PHY_BASE_T, - .ver_addr = 0, - .req_flow_ctrl = 0, - .req_line_speed = 0, - .speed_cap_mask = 0, - .req_duplex = 0, - .rsrv = 0, - .config_init = elink_xgxs_config_init, - .read_status = elink_link_settings_status, - .link_reset = elink_int_link_reset, - .config_loopback = NULL, - .format_fw_ver = NULL, - .hw_reset = NULL, - .set_link_led = NULL, - .phy_specific_func = NULL + .type = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT, + .addr = 0xff, + .def_md_devad = 0, + .flags = 0, + .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, + .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, + .mdio_ctrl = 0, + .supported = (ELINK_SUPPORTED_10baseT_Half | + ELINK_SUPPORTED_10baseT_Full | + ELINK_SUPPORTED_100baseT_Half | + ELINK_SUPPORTED_100baseT_Full | + ELINK_SUPPORTED_1000baseT_Full | + ELINK_SUPPORTED_2500baseX_Full | + ELINK_SUPPORTED_TP | + ELINK_SUPPORTED_Autoneg | + ELINK_SUPPORTED_Pause | + ELINK_SUPPORTED_Asym_Pause), + .media_type = ELINK_ETH_PHY_BASE_T, + .ver_addr = 0, + .req_flow_ctrl = 0, + .req_line_speed = 0, + .speed_cap_mask = 0, + .req_duplex = 0, + .rsrv = 0, + .config_init = (config_init_t)elink_xgxs_config_init, + .read_status = (read_status_t)elink_link_settings_status, + .link_reset = (link_reset_t)elink_int_link_reset, + .config_loopback = (config_loopback_t)NULL, + .format_fw_ver = (format_fw_ver_t)NULL, + .hw_reset = (hw_reset_t)NULL, + .set_link_led = (set_link_led_t)NULL, + .phy_specific_func = (phy_specific_func_t)NULL }; static const struct elink_phy phy_xgxs = { - .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT, - .addr = 0xff, - .def_md_devad = 0, - .flags = 0, - .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, - .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, - .mdio_ctrl = 0, - .supported = (ELINK_SUPPORTED_10baseT_Half | - ELINK_SUPPORTED_10baseT_Full | - ELINK_SUPPORTED_100baseT_Half | - ELINK_SUPPORTED_100baseT_Full | - ELINK_SUPPORTED_1000baseT_Full | - ELINK_SUPPORTED_2500baseX_Full | - ELINK_SUPPORTED_10000baseT_Full | - ELINK_SUPPORTED_FIBRE | - ELINK_SUPPORTED_Autoneg | - ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause), - .media_type = ELINK_ETH_PHY_CX4, - .ver_addr = 0, - .req_flow_ctrl = 0, - .req_line_speed = 0, - .speed_cap_mask = 0, - .req_duplex = 0, - .rsrv = 0, - .config_init = elink_xgxs_config_init, - .read_status = elink_link_settings_status, - .link_reset = elink_int_link_reset, - .config_loopback = elink_set_xgxs_loopback, - .format_fw_ver = NULL, - .hw_reset = NULL, - .set_link_led = NULL, - .phy_specific_func = elink_xgxs_specific_func + .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT, + .addr = 0xff, + .def_md_devad = 0, + .flags = 0, + .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, + .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, + .mdio_ctrl = 0, + .supported = (ELINK_SUPPORTED_10baseT_Half | + ELINK_SUPPORTED_10baseT_Full | + ELINK_SUPPORTED_100baseT_Half | + ELINK_SUPPORTED_100baseT_Full | + ELINK_SUPPORTED_1000baseT_Full | + ELINK_SUPPORTED_2500baseX_Full | + ELINK_SUPPORTED_10000baseT_Full | + ELINK_SUPPORTED_FIBRE | + ELINK_SUPPORTED_Autoneg | + ELINK_SUPPORTED_Pause | + ELINK_SUPPORTED_Asym_Pause), + .media_type = ELINK_ETH_PHY_CX4, + .ver_addr = 0, + .req_flow_ctrl = 0, + .req_line_speed = 0, + .speed_cap_mask = 0, + .req_duplex = 0, + .rsrv = 0, + .config_init = (config_init_t)elink_xgxs_config_init, + .read_status = (read_status_t)elink_link_settings_status, + .link_reset = (link_reset_t)elink_int_link_reset, + .config_loopback = (config_loopback_t)elink_set_xgxs_loopback, + .format_fw_ver = (format_fw_ver_t)NULL, + .hw_reset = (hw_reset_t)NULL, + .set_link_led = (set_link_led_t)NULL, + .phy_specific_func = (phy_specific_func_t)elink_xgxs_specific_func }; - static const struct elink_phy phy_warpcore = { - .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT, - .addr = 0xff, - .def_md_devad = 0, - .flags = ELINK_FLAGS_TX_ERROR_CHECK, - .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, - .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, - .mdio_ctrl = 0, - .supported = (ELINK_SUPPORTED_10baseT_Half | - ELINK_SUPPORTED_10baseT_Full | - ELINK_SUPPORTED_100baseT_Half | - ELINK_SUPPORTED_100baseT_Full | - ELINK_SUPPORTED_1000baseT_Full | - ELINK_SUPPORTED_10000baseT_Full | - ELINK_SUPPORTED_20000baseKR2_Full | - ELINK_SUPPORTED_20000baseMLD2_Full | - ELINK_SUPPORTED_FIBRE | - ELINK_SUPPORTED_Autoneg | - ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause), - .media_type = ELINK_ETH_PHY_UNSPECIFIED, - .ver_addr = 0, - .req_flow_ctrl = 0, - .req_line_speed = 0, - .speed_cap_mask = 0, - /* req_duplex = */ 0, - /* rsrv = */ 0, - .config_init = elink_warpcore_config_init, - .read_status = elink_warpcore_read_status, - .link_reset = elink_warpcore_link_reset, - .config_loopback = elink_set_warpcore_loopback, - .format_fw_ver = NULL, - .hw_reset = elink_warpcore_hw_reset, - .set_link_led = NULL, - .phy_specific_func = NULL + .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT, + .addr = 0xff, + .def_md_devad = 0, + .flags = ELINK_FLAGS_TX_ERROR_CHECK, + .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, + .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, + .mdio_ctrl = 0, + .supported = (ELINK_SUPPORTED_10baseT_Half | + ELINK_SUPPORTED_10baseT_Full | + ELINK_SUPPORTED_100baseT_Half | + ELINK_SUPPORTED_100baseT_Full | + ELINK_SUPPORTED_1000baseT_Full | + ELINK_SUPPORTED_1000baseKX_Full | + ELINK_SUPPORTED_10000baseT_Full | + ELINK_SUPPORTED_10000baseKR_Full | + ELINK_SUPPORTED_20000baseKR2_Full | + ELINK_SUPPORTED_20000baseMLD2_Full | + ELINK_SUPPORTED_FIBRE | + ELINK_SUPPORTED_Autoneg | + ELINK_SUPPORTED_Pause | + ELINK_SUPPORTED_Asym_Pause), + .media_type = ELINK_ETH_PHY_UNSPECIFIED, + .ver_addr = 0, + .req_flow_ctrl = 0, + .req_line_speed = 0, + .speed_cap_mask = 0, + /* req_duplex = */0, + /* rsrv = */0, + .config_init = (config_init_t)elink_warpcore_config_init, + .read_status = (read_status_t)elink_warpcore_read_status, + .link_reset = (link_reset_t)elink_warpcore_link_reset, + .config_loopback = (config_loopback_t)elink_set_warpcore_loopback, + .format_fw_ver = (format_fw_ver_t)NULL, + .hw_reset = (hw_reset_t)elink_warpcore_hw_reset, + .set_link_led = (set_link_led_t)NULL, + .phy_specific_func = (phy_specific_func_t)NULL }; + static const struct elink_phy phy_7101 = { - .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101, - .addr = 0xff, - .def_md_devad = 0, - .flags = ELINK_FLAGS_FAN_FAILURE_DET_REQ, - .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, - .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, - .mdio_ctrl = 0, - .supported = (ELINK_SUPPORTED_10000baseT_Full | - ELINK_SUPPORTED_TP | - ELINK_SUPPORTED_Autoneg | - ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause), - .media_type = ELINK_ETH_PHY_BASE_T, - .ver_addr = 0, - .req_flow_ctrl = 0, - .req_line_speed = 0, - .speed_cap_mask = 0, - .req_duplex = 0, - .rsrv = 0, - .config_init = elink_7101_config_init, - .read_status = elink_7101_read_status, - .link_reset = elink_common_ext_link_reset, - .config_loopback = elink_7101_config_loopback, - .format_fw_ver = elink_7101_format_ver, - .hw_reset = elink_7101_hw_reset, - .set_link_led = elink_7101_set_link_led, - .phy_specific_func = NULL + .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101, + .addr = 0xff, + .def_md_devad = 0, + .flags = ELINK_FLAGS_FAN_FAILURE_DET_REQ, + .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, + .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, + .mdio_ctrl = 0, + .supported = (ELINK_SUPPORTED_10000baseT_Full | + ELINK_SUPPORTED_TP | + ELINK_SUPPORTED_Autoneg | + ELINK_SUPPORTED_Pause | + ELINK_SUPPORTED_Asym_Pause), + .media_type = ELINK_ETH_PHY_BASE_T, + .ver_addr = 0, + .req_flow_ctrl = 0, + .req_line_speed = 0, + .speed_cap_mask = 0, + .req_duplex = 0, + .rsrv = 0, + .config_init = (config_init_t)elink_7101_config_init, + .read_status = (read_status_t)elink_7101_read_status, + .link_reset = (link_reset_t)elink_common_ext_link_reset, + .config_loopback = (config_loopback_t)elink_7101_config_loopback, + .format_fw_ver = (format_fw_ver_t)elink_7101_format_ver, + .hw_reset = (hw_reset_t)elink_7101_hw_reset, + .set_link_led = (set_link_led_t)elink_7101_set_link_led, + .phy_specific_func = (phy_specific_func_t)NULL }; - static const struct elink_phy phy_8073 = { - .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8073, - .addr = 0xff, - .def_md_devad = 0, - .flags = 0, - .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, - .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, - .mdio_ctrl = 0, - .supported = (ELINK_SUPPORTED_10000baseT_Full | - ELINK_SUPPORTED_2500baseX_Full | - ELINK_SUPPORTED_1000baseT_Full | - ELINK_SUPPORTED_FIBRE | - ELINK_SUPPORTED_Autoneg | - ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause), - .media_type = ELINK_ETH_PHY_KR, - .ver_addr = 0, - .req_flow_ctrl = 0, - .req_line_speed = 0, - .speed_cap_mask = 0, - .req_duplex = 0, - .rsrv = 0, - .config_init = elink_8073_config_init, - .read_status = elink_8073_read_status, - .link_reset = elink_8073_link_reset, - .config_loopback = NULL, - .format_fw_ver = elink_format_ver, - .hw_reset = NULL, - .set_link_led = NULL, - .phy_specific_func = elink_8073_specific_func + .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8073, + .addr = 0xff, + .def_md_devad = 0, + .flags = 0, + .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, + .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, + .mdio_ctrl = 0, + .supported = (ELINK_SUPPORTED_10000baseT_Full | + ELINK_SUPPORTED_2500baseX_Full | + ELINK_SUPPORTED_1000baseT_Full | + ELINK_SUPPORTED_FIBRE | + ELINK_SUPPORTED_Autoneg | + ELINK_SUPPORTED_Pause | + ELINK_SUPPORTED_Asym_Pause), + .media_type = ELINK_ETH_PHY_KR, + .ver_addr = 0, + .req_flow_ctrl = 0, + .req_line_speed = 0, + .speed_cap_mask = 0, + .req_duplex = 0, + .rsrv = 0, + .config_init = (config_init_t)elink_8073_config_init, + .read_status = (read_status_t)elink_8073_read_status, + .link_reset = (link_reset_t)elink_8073_link_reset, + .config_loopback = (config_loopback_t)NULL, + .format_fw_ver = (format_fw_ver_t)elink_format_ver, + .hw_reset = (hw_reset_t)NULL, + .set_link_led = (set_link_led_t)NULL, + .phy_specific_func = (phy_specific_func_t)elink_8073_specific_func }; - static const struct elink_phy phy_8705 = { - .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8705, - .addr = 0xff, - .def_md_devad = 0, - .flags = ELINK_FLAGS_INIT_XGXS_FIRST, - .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, - .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, - .mdio_ctrl = 0, - .supported = (ELINK_SUPPORTED_10000baseT_Full | - ELINK_SUPPORTED_FIBRE | - ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause), - .media_type = ELINK_ETH_PHY_XFP_FIBER, - .ver_addr = 0, - .req_flow_ctrl = 0, - .req_line_speed = 0, - .speed_cap_mask = 0, - .req_duplex = 0, - .rsrv = 0, - .config_init = elink_8705_config_init, - .read_status = elink_8705_read_status, - .link_reset = elink_common_ext_link_reset, - .config_loopback = NULL, - .format_fw_ver = elink_null_format_ver, - .hw_reset = NULL, - .set_link_led = NULL, - .phy_specific_func = NULL + .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8705, + .addr = 0xff, + .def_md_devad = 0, + .flags = ELINK_FLAGS_INIT_XGXS_FIRST, + .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, + .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, + .mdio_ctrl = 0, + .supported = (ELINK_SUPPORTED_10000baseT_Full | + ELINK_SUPPORTED_FIBRE | + ELINK_SUPPORTED_Pause | + ELINK_SUPPORTED_Asym_Pause), + .media_type = ELINK_ETH_PHY_XFP_FIBER, + .ver_addr = 0, + .req_flow_ctrl = 0, + .req_line_speed = 0, + .speed_cap_mask = 0, + .req_duplex = 0, + .rsrv = 0, + .config_init = (config_init_t)elink_8705_config_init, + .read_status = (read_status_t)elink_8705_read_status, + .link_reset = (link_reset_t)elink_common_ext_link_reset, + .config_loopback = (config_loopback_t)NULL, + .format_fw_ver = (format_fw_ver_t)elink_null_format_ver, + .hw_reset = (hw_reset_t)NULL, + .set_link_led = (set_link_led_t)NULL, + .phy_specific_func = (phy_specific_func_t)NULL }; - static const struct elink_phy phy_8706 = { - .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8706, - .addr = 0xff, - .def_md_devad = 0, - .flags = ELINK_FLAGS_INIT_XGXS_FIRST, - .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, - .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, - .mdio_ctrl = 0, - .supported = (ELINK_SUPPORTED_10000baseT_Full | - ELINK_SUPPORTED_1000baseT_Full | - ELINK_SUPPORTED_FIBRE | - ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause), - .media_type = ELINK_ETH_PHY_SFPP_10G_FIBER, - .ver_addr = 0, - .req_flow_ctrl = 0, - .req_line_speed = 0, - .speed_cap_mask = 0, - .req_duplex = 0, - .rsrv = 0, - .config_init = elink_8706_config_init, - .read_status = elink_8706_read_status, - .link_reset = elink_common_ext_link_reset, - .config_loopback = NULL, - .format_fw_ver = elink_format_ver, - .hw_reset = NULL, - .set_link_led = NULL, - .phy_specific_func = NULL + .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8706, + .addr = 0xff, + .def_md_devad = 0, + .flags = ELINK_FLAGS_INIT_XGXS_FIRST, + .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, + .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, + .mdio_ctrl = 0, + .supported = (ELINK_SUPPORTED_10000baseT_Full | + ELINK_SUPPORTED_1000baseT_Full | + ELINK_SUPPORTED_FIBRE | + ELINK_SUPPORTED_Pause | + ELINK_SUPPORTED_Asym_Pause), + .media_type = ELINK_ETH_PHY_SFPP_10G_FIBER, + .ver_addr = 0, + .req_flow_ctrl = 0, + .req_line_speed = 0, + .speed_cap_mask = 0, + .req_duplex = 0, + .rsrv = 0, + .config_init = (config_init_t)elink_8706_config_init, + .read_status = (read_status_t)elink_8706_read_status, + .link_reset = (link_reset_t)elink_common_ext_link_reset, + .config_loopback = (config_loopback_t)NULL, + .format_fw_ver = (format_fw_ver_t)elink_format_ver, + .hw_reset = (hw_reset_t)NULL, + .set_link_led = (set_link_led_t)NULL, + .phy_specific_func = (phy_specific_func_t)NULL }; static const struct elink_phy phy_8726 = { - .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726, - .addr = 0xff, - .def_md_devad = 0, - .flags = (ELINK_FLAGS_INIT_XGXS_FIRST | ELINK_FLAGS_TX_ERROR_CHECK), - .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, - .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, - .mdio_ctrl = 0, - .supported = (ELINK_SUPPORTED_10000baseT_Full | - ELINK_SUPPORTED_1000baseT_Full | - ELINK_SUPPORTED_Autoneg | - ELINK_SUPPORTED_FIBRE | - ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause), - .media_type = ELINK_ETH_PHY_NOT_PRESENT, - .ver_addr = 0, - .req_flow_ctrl = 0, - .req_line_speed = 0, - .speed_cap_mask = 0, - .req_duplex = 0, - .rsrv = 0, - .config_init = elink_8726_config_init, - .read_status = elink_8726_read_status, - .link_reset = elink_8726_link_reset, - .config_loopback = elink_8726_config_loopback, - .format_fw_ver = elink_format_ver, - .hw_reset = NULL, - .set_link_led = NULL, - .phy_specific_func = NULL + .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726, + .addr = 0xff, + .def_md_devad = 0, + .flags = (ELINK_FLAGS_INIT_XGXS_FIRST | + ELINK_FLAGS_TX_ERROR_CHECK), + .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, + .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, + .mdio_ctrl = 0, + .supported = (ELINK_SUPPORTED_10000baseT_Full | + ELINK_SUPPORTED_1000baseT_Full | + ELINK_SUPPORTED_Autoneg | + ELINK_SUPPORTED_FIBRE | + ELINK_SUPPORTED_Pause | + ELINK_SUPPORTED_Asym_Pause), + .media_type = ELINK_ETH_PHY_NOT_PRESENT, + .ver_addr = 0, + .req_flow_ctrl = 0, + .req_line_speed = 0, + .speed_cap_mask = 0, + .req_duplex = 0, + .rsrv = 0, + .config_init = (config_init_t)elink_8726_config_init, + .read_status = (read_status_t)elink_8726_read_status, + .link_reset = (link_reset_t)elink_8726_link_reset, + .config_loopback = (config_loopback_t)elink_8726_config_loopback, + .format_fw_ver = (format_fw_ver_t)elink_format_ver, + .hw_reset = (hw_reset_t)NULL, + .set_link_led = (set_link_led_t)NULL, + .phy_specific_func = (phy_specific_func_t)NULL }; static const struct elink_phy phy_8727 = { - .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727, - .addr = 0xff, - .def_md_devad = 0, - .flags = (ELINK_FLAGS_FAN_FAILURE_DET_REQ | ELINK_FLAGS_TX_ERROR_CHECK), - .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, - .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, - .mdio_ctrl = 0, - .supported = (ELINK_SUPPORTED_10000baseT_Full | - ELINK_SUPPORTED_1000baseT_Full | - ELINK_SUPPORTED_FIBRE | - ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause), - .media_type = ELINK_ETH_PHY_NOT_PRESENT, - .ver_addr = 0, - .req_flow_ctrl = 0, - .req_line_speed = 0, - .speed_cap_mask = 0, - .req_duplex = 0, - .rsrv = 0, - .config_init = elink_8727_config_init, - .read_status = elink_8727_read_status, - .link_reset = elink_8727_link_reset, - .config_loopback = NULL, - .format_fw_ver = elink_format_ver, - .hw_reset = elink_8727_hw_reset, - .set_link_led = elink_8727_set_link_led, - .phy_specific_func = elink_8727_specific_func + .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727, + .addr = 0xff, + .def_md_devad = 0, + .flags = (ELINK_FLAGS_FAN_FAILURE_DET_REQ | + ELINK_FLAGS_TX_ERROR_CHECK), + .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, + .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, + .mdio_ctrl = 0, + .supported = (ELINK_SUPPORTED_10000baseT_Full | + ELINK_SUPPORTED_1000baseT_Full | + ELINK_SUPPORTED_FIBRE | + ELINK_SUPPORTED_Pause | + ELINK_SUPPORTED_Asym_Pause), + .media_type = ELINK_ETH_PHY_NOT_PRESENT, + .ver_addr = 0, + .req_flow_ctrl = 0, + .req_line_speed = 0, + .speed_cap_mask = 0, + .req_duplex = 0, + .rsrv = 0, + .config_init = (config_init_t)elink_8727_config_init, + .read_status = (read_status_t)elink_8727_read_status, + .link_reset = (link_reset_t)elink_8727_link_reset, + .config_loopback = (config_loopback_t)NULL, + .format_fw_ver = (format_fw_ver_t)elink_format_ver, + .hw_reset = (hw_reset_t)elink_8727_hw_reset, + .set_link_led = (set_link_led_t)elink_8727_set_link_led, + .phy_specific_func = (phy_specific_func_t)elink_8727_specific_func }; - static const struct elink_phy phy_8481 = { - .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8481, - .addr = 0xff, - .def_md_devad = 0, - .flags = ELINK_FLAGS_FAN_FAILURE_DET_REQ | - ELINK_FLAGS_REARM_LATCH_SIGNAL, - .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, - .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, - .mdio_ctrl = 0, - .supported = (ELINK_SUPPORTED_10baseT_Half | - ELINK_SUPPORTED_10baseT_Full | - ELINK_SUPPORTED_100baseT_Half | - ELINK_SUPPORTED_100baseT_Full | - ELINK_SUPPORTED_1000baseT_Full | - ELINK_SUPPORTED_10000baseT_Full | - ELINK_SUPPORTED_TP | - ELINK_SUPPORTED_Autoneg | - ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause), - .media_type = ELINK_ETH_PHY_BASE_T, - .ver_addr = 0, - .req_flow_ctrl = 0, - .req_line_speed = 0, - .speed_cap_mask = 0, - .req_duplex = 0, - .rsrv = 0, - .config_init = elink_8481_config_init, - .read_status = elink_848xx_read_status, - .link_reset = elink_8481_link_reset, - .config_loopback = NULL, - .format_fw_ver = elink_848xx_format_ver, - .hw_reset = elink_8481_hw_reset, - .set_link_led = elink_848xx_set_link_led, - .phy_specific_func = NULL + .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8481, + .addr = 0xff, + .def_md_devad = 0, + .flags = ELINK_FLAGS_FAN_FAILURE_DET_REQ | + ELINK_FLAGS_REARM_LATCH_SIGNAL, + .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, + .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, + .mdio_ctrl = 0, + .supported = (ELINK_SUPPORTED_10baseT_Half | + ELINK_SUPPORTED_10baseT_Full | + ELINK_SUPPORTED_100baseT_Half | + ELINK_SUPPORTED_100baseT_Full | + ELINK_SUPPORTED_1000baseT_Full | + ELINK_SUPPORTED_10000baseT_Full | + ELINK_SUPPORTED_TP | + ELINK_SUPPORTED_Autoneg | + ELINK_SUPPORTED_Pause | + ELINK_SUPPORTED_Asym_Pause), + .media_type = ELINK_ETH_PHY_BASE_T, + .ver_addr = 0, + .req_flow_ctrl = 0, + .req_line_speed = 0, + .speed_cap_mask = 0, + .req_duplex = 0, + .rsrv = 0, + .config_init = (config_init_t)elink_8481_config_init, + .read_status = (read_status_t)elink_848xx_read_status, + .link_reset = (link_reset_t)elink_8481_link_reset, + .config_loopback = (config_loopback_t)NULL, + .format_fw_ver = (format_fw_ver_t)elink_848xx_format_ver, + .hw_reset = (hw_reset_t)elink_8481_hw_reset, + .set_link_led = (set_link_led_t)elink_848xx_set_link_led, + .phy_specific_func = (phy_specific_func_t)NULL }; static const struct elink_phy phy_84823 = { - .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84823, - .addr = 0xff, - .def_md_devad = 0, - .flags = (ELINK_FLAGS_FAN_FAILURE_DET_REQ | - ELINK_FLAGS_REARM_LATCH_SIGNAL | ELINK_FLAGS_TX_ERROR_CHECK), - .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, - .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, - .mdio_ctrl = 0, - .supported = (ELINK_SUPPORTED_10baseT_Half | - ELINK_SUPPORTED_10baseT_Full | - ELINK_SUPPORTED_100baseT_Half | - ELINK_SUPPORTED_100baseT_Full | - ELINK_SUPPORTED_1000baseT_Full | - ELINK_SUPPORTED_10000baseT_Full | - ELINK_SUPPORTED_TP | - ELINK_SUPPORTED_Autoneg | - ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause), - .media_type = ELINK_ETH_PHY_BASE_T, - .ver_addr = 0, - .req_flow_ctrl = 0, - .req_line_speed = 0, - .speed_cap_mask = 0, - .req_duplex = 0, - .rsrv = 0, - .config_init = elink_848x3_config_init, - .read_status = elink_848xx_read_status, - .link_reset = elink_848x3_link_reset, - .config_loopback = NULL, - .format_fw_ver = elink_848xx_format_ver, - .hw_reset = NULL, - .set_link_led = elink_848xx_set_link_led, - .phy_specific_func = elink_848xx_specific_func + .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84823, + .addr = 0xff, + .def_md_devad = 0, + .flags = (ELINK_FLAGS_FAN_FAILURE_DET_REQ | + ELINK_FLAGS_REARM_LATCH_SIGNAL | + ELINK_FLAGS_TX_ERROR_CHECK), + .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, + .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, + .mdio_ctrl = 0, + .supported = (ELINK_SUPPORTED_10baseT_Half | + ELINK_SUPPORTED_10baseT_Full | + ELINK_SUPPORTED_100baseT_Half | + ELINK_SUPPORTED_100baseT_Full | + ELINK_SUPPORTED_1000baseT_Full | + ELINK_SUPPORTED_10000baseT_Full | + ELINK_SUPPORTED_TP | + ELINK_SUPPORTED_Autoneg | + ELINK_SUPPORTED_Pause | + ELINK_SUPPORTED_Asym_Pause), + .media_type = ELINK_ETH_PHY_BASE_T, + .ver_addr = 0, + .req_flow_ctrl = 0, + .req_line_speed = 0, + .speed_cap_mask = 0, + .req_duplex = 0, + .rsrv = 0, + .config_init = (config_init_t)elink_848x3_config_init, + .read_status = (read_status_t)elink_848xx_read_status, + .link_reset = (link_reset_t)elink_848x3_link_reset, + .config_loopback = (config_loopback_t)NULL, + .format_fw_ver = (format_fw_ver_t)elink_848xx_format_ver, + .hw_reset = (hw_reset_t)NULL, + .set_link_led = (set_link_led_t)elink_848xx_set_link_led, + .phy_specific_func = (phy_specific_func_t)elink_848xx_specific_func }; static const struct elink_phy phy_84833 = { - .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833, - .addr = 0xff, - .def_md_devad = 0, - .flags = (ELINK_FLAGS_FAN_FAILURE_DET_REQ | - ELINK_FLAGS_REARM_LATCH_SIGNAL | - ELINK_FLAGS_TX_ERROR_CHECK | ELINK_FLAGS_TEMPERATURE), - .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, - .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, - .mdio_ctrl = 0, - .supported = (ELINK_SUPPORTED_100baseT_Half | - ELINK_SUPPORTED_100baseT_Full | - ELINK_SUPPORTED_1000baseT_Full | - ELINK_SUPPORTED_10000baseT_Full | - ELINK_SUPPORTED_TP | - ELINK_SUPPORTED_Autoneg | - ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause), - .media_type = ELINK_ETH_PHY_BASE_T, - .ver_addr = 0, - .req_flow_ctrl = 0, - .req_line_speed = 0, - .speed_cap_mask = 0, - .req_duplex = 0, - .rsrv = 0, - .config_init = elink_848x3_config_init, - .read_status = elink_848xx_read_status, - .link_reset = elink_848x3_link_reset, - .config_loopback = NULL, - .format_fw_ver = elink_848xx_format_ver, - .hw_reset = elink_84833_hw_reset_phy, - .set_link_led = elink_848xx_set_link_led, - .phy_specific_func = elink_848xx_specific_func + .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833, + .addr = 0xff, + .def_md_devad = 0, + .flags = (ELINK_FLAGS_FAN_FAILURE_DET_REQ | + ELINK_FLAGS_REARM_LATCH_SIGNAL | + ELINK_FLAGS_TX_ERROR_CHECK | + ELINK_FLAGS_TEMPERATURE), + .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, + .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, + .mdio_ctrl = 0, + .supported = (ELINK_SUPPORTED_100baseT_Half | + ELINK_SUPPORTED_100baseT_Full | + ELINK_SUPPORTED_1000baseT_Full | + ELINK_SUPPORTED_10000baseT_Full | + ELINK_SUPPORTED_TP | + ELINK_SUPPORTED_Autoneg | + ELINK_SUPPORTED_Pause | + ELINK_SUPPORTED_Asym_Pause), + .media_type = ELINK_ETH_PHY_BASE_T, + .ver_addr = 0, + .req_flow_ctrl = 0, + .req_line_speed = 0, + .speed_cap_mask = 0, + .req_duplex = 0, + .rsrv = 0, + .config_init = (config_init_t)elink_848x3_config_init, + .read_status = (read_status_t)elink_848xx_read_status, + .link_reset = (link_reset_t)elink_848x3_link_reset, + .config_loopback = (config_loopback_t)NULL, + .format_fw_ver = (format_fw_ver_t)elink_848xx_format_ver, + .hw_reset = (hw_reset_t)elink_84833_hw_reset_phy, + .set_link_led = (set_link_led_t)elink_848xx_set_link_led, + .phy_specific_func = (phy_specific_func_t)elink_848xx_specific_func }; static const struct elink_phy phy_84834 = { - .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834, - .addr = 0xff, - .def_md_devad = 0, - .flags = ELINK_FLAGS_FAN_FAILURE_DET_REQ | - ELINK_FLAGS_REARM_LATCH_SIGNAL, - .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, - .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, - .mdio_ctrl = 0, - .supported = (ELINK_SUPPORTED_100baseT_Half | - ELINK_SUPPORTED_100baseT_Full | - ELINK_SUPPORTED_1000baseT_Full | - ELINK_SUPPORTED_10000baseT_Full | - ELINK_SUPPORTED_TP | - ELINK_SUPPORTED_Autoneg | - ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause), - .media_type = ELINK_ETH_PHY_BASE_T, - .ver_addr = 0, - .req_flow_ctrl = 0, - .req_line_speed = 0, - .speed_cap_mask = 0, - .req_duplex = 0, - .rsrv = 0, - .config_init = elink_848x3_config_init, - .read_status = elink_848xx_read_status, - .link_reset = elink_848x3_link_reset, - .config_loopback = NULL, - .format_fw_ver = elink_848xx_format_ver, - .hw_reset = elink_84833_hw_reset_phy, - .set_link_led = elink_848xx_set_link_led, - .phy_specific_func = elink_848xx_specific_func + .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834, + .addr = 0xff, + .def_md_devad = 0, + .flags = ELINK_FLAGS_FAN_FAILURE_DET_REQ | + ELINK_FLAGS_REARM_LATCH_SIGNAL, + .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, + .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, + .mdio_ctrl = 0, + .supported = (ELINK_SUPPORTED_100baseT_Half | + ELINK_SUPPORTED_100baseT_Full | + ELINK_SUPPORTED_1000baseT_Full | + ELINK_SUPPORTED_10000baseT_Full | + ELINK_SUPPORTED_TP | + ELINK_SUPPORTED_Autoneg | + ELINK_SUPPORTED_Pause | + ELINK_SUPPORTED_Asym_Pause), + .media_type = ELINK_ETH_PHY_BASE_T, + .ver_addr = 0, + .req_flow_ctrl = 0, + .req_line_speed = 0, + .speed_cap_mask = 0, + .req_duplex = 0, + .rsrv = 0, + .config_init = (config_init_t)elink_848x3_config_init, + .read_status = (read_status_t)elink_848xx_read_status, + .link_reset = (link_reset_t)elink_848x3_link_reset, + .config_loopback = (config_loopback_t)NULL, + .format_fw_ver = (format_fw_ver_t)elink_848xx_format_ver, + .hw_reset = (hw_reset_t)elink_84833_hw_reset_phy, + .set_link_led = (set_link_led_t)elink_848xx_set_link_led, + .phy_specific_func = (phy_specific_func_t)elink_848xx_specific_func }; -static const struct elink_phy phy_54618se = { - .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE, - .addr = 0xff, - .def_md_devad = 0, - .flags = ELINK_FLAGS_INIT_XGXS_FIRST, - .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, - .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, - .mdio_ctrl = 0, - .supported = (ELINK_SUPPORTED_10baseT_Half | - ELINK_SUPPORTED_10baseT_Full | - ELINK_SUPPORTED_100baseT_Half | - ELINK_SUPPORTED_100baseT_Full | - ELINK_SUPPORTED_1000baseT_Full | - ELINK_SUPPORTED_TP | - ELINK_SUPPORTED_Autoneg | - ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause), - .media_type = ELINK_ETH_PHY_BASE_T, - .ver_addr = 0, - .req_flow_ctrl = 0, - .req_line_speed = 0, - .speed_cap_mask = 0, - /* req_duplex = */ 0, - /* rsrv = */ 0, - .config_init = elink_54618se_config_init, - .read_status = elink_54618se_read_status, - .link_reset = elink_54618se_link_reset, - .config_loopback = elink_54618se_config_loopback, - .format_fw_ver = NULL, - .hw_reset = NULL, - .set_link_led = elink_5461x_set_link_led, - .phy_specific_func = elink_54618se_specific_func +static const struct elink_phy phy_84858 = { + .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84858, + .addr = 0xff, + .def_md_devad = 0, + .flags = ELINK_FLAGS_FAN_FAILURE_DET_REQ | + ELINK_FLAGS_REARM_LATCH_SIGNAL, + .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, + .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, + .mdio_ctrl = 0, + .supported = (ELINK_SUPPORTED_100baseT_Half | + ELINK_SUPPORTED_100baseT_Full | + ELINK_SUPPORTED_1000baseT_Full | + ELINK_SUPPORTED_10000baseT_Full | + ELINK_SUPPORTED_TP | + ELINK_SUPPORTED_Autoneg | + ELINK_SUPPORTED_Pause | + ELINK_SUPPORTED_Asym_Pause), + .media_type = ELINK_ETH_PHY_BASE_T, + .ver_addr = 0, + .req_flow_ctrl = 0, + .req_line_speed = 0, + .speed_cap_mask = 0, + .req_duplex = 0, + .rsrv = 0, + .config_init = (config_init_t)elink_848x3_config_init, + .read_status = (read_status_t)elink_848xx_read_status, + .link_reset = (link_reset_t)elink_848x3_link_reset, + .config_loopback = (config_loopback_t)NULL, + .format_fw_ver = (format_fw_ver_t)elink_848xx_format_ver, + .hw_reset = (hw_reset_t)elink_84833_hw_reset_phy, + .set_link_led = (set_link_led_t)elink_848xx_set_link_led, + .phy_specific_func = (phy_specific_func_t)elink_848xx_specific_func }; + +static const struct elink_phy phy_54618se = { + .type = PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X54618SE, + .addr = 0xff, + .def_md_devad = 0, + .flags = ELINK_FLAGS_INIT_XGXS_FIRST, + .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, + .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, + .mdio_ctrl = 0, + .supported = (ELINK_SUPPORTED_10baseT_Half | + ELINK_SUPPORTED_10baseT_Full | + ELINK_SUPPORTED_100baseT_Half | + ELINK_SUPPORTED_100baseT_Full | + ELINK_SUPPORTED_1000baseT_Full | + ELINK_SUPPORTED_TP | + ELINK_SUPPORTED_Autoneg | + ELINK_SUPPORTED_Pause | + ELINK_SUPPORTED_Asym_Pause), + .media_type = ELINK_ETH_PHY_BASE_T, + .ver_addr = 0, + .req_flow_ctrl = 0, + .req_line_speed = 0, + .speed_cap_mask = 0, + /* req_duplex = */0, + /* rsrv = */0, + .config_init = (config_init_t)elink_54618se_config_init, + .read_status = (read_status_t)elink_54618se_read_status, + .link_reset = (link_reset_t)elink_54618se_link_reset, + .config_loopback = (config_loopback_t)elink_54618se_config_loopback, + .format_fw_ver = (format_fw_ver_t)NULL, + .hw_reset = (hw_reset_t)NULL, + .set_link_led = (set_link_led_t)elink_5461x_set_link_led, + .phy_specific_func = (phy_specific_func_t)elink_54618se_specific_func +}; /*****************************************************************/ /* */ /* Populate the phy according. Main function: elink_populate_phy */ @@ -11148,9 +13039,9 @@ static const struct elink_phy phy_54618se = { /*****************************************************************/ static void elink_populate_preemphasis(struct bnx2x_softc *sc, - uint32_t shmem_base, - struct elink_phy *phy, uint8_t port, - uint8_t phy_index) + uint32_t shmem_base, + struct elink_phy *phy, uint8_t port, + uint8_t phy_index) { /* Get the 4 lanes xgxs config rx and tx */ uint32_t rx = 0, tx = 0, i; @@ -11162,23 +13053,19 @@ static void elink_populate_preemphasis(struct bnx2x_softc *sc, if (phy_index == ELINK_INT_PHY || phy_index == ELINK_EXT_PHY1) { rx = REG_RD(sc, shmem_base + offsetof(struct shmem_region, - dev_info.port_hw_config[port]. - xgxs_config_rx[i << 1])); + dev_info.port_hw_config[port].xgxs_config_rx[i << 1])); tx = REG_RD(sc, shmem_base + offsetof(struct shmem_region, - dev_info.port_hw_config[port]. - xgxs_config_tx[i << 1])); + dev_info.port_hw_config[port].xgxs_config_tx[i << 1])); } else { rx = REG_RD(sc, shmem_base + offsetof(struct shmem_region, - dev_info.port_hw_config[port]. - xgxs_config2_rx[i << 1])); + dev_info.port_hw_config[port].xgxs_config2_rx[i << 1])); tx = REG_RD(sc, shmem_base + offsetof(struct shmem_region, - dev_info.port_hw_config[port]. - xgxs_config2_rx[i << 1])); + dev_info.port_hw_config[port].xgxs_config2_rx[i << 1])); } phy->rx_preemphasis[i << 1] = ((rx >> 16) & 0xffff); @@ -11186,65 +13073,62 @@ static void elink_populate_preemphasis(struct bnx2x_softc *sc, phy->tx_preemphasis[i << 1] = ((tx >> 16) & 0xffff); phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff); + ELINK_DEBUG_P2(sc, "phy->rx_preemphasis = %x, phy->tx_preemphasis = %x", + phy->rx_preemphasis[i << 1], + phy->tx_preemphasis[i << 1]); } } static uint32_t elink_get_ext_phy_config(struct bnx2x_softc *sc, - uint32_t shmem_base, uint8_t phy_index, - uint8_t port) + uint32_t shmem_base, + uint8_t phy_index, uint8_t port) { uint32_t ext_phy_config = 0; switch (phy_index) { case ELINK_EXT_PHY1: ext_phy_config = REG_RD(sc, shmem_base + - offsetof(struct shmem_region, - dev_info.port_hw_config[port]. - external_phy_config)); + offsetof(struct shmem_region, + dev_info.port_hw_config[port].external_phy_config)); break; case ELINK_EXT_PHY2: ext_phy_config = REG_RD(sc, shmem_base + - offsetof(struct shmem_region, - dev_info.port_hw_config[port]. - external_phy_config2)); + offsetof(struct shmem_region, + dev_info.port_hw_config[port].external_phy_config2)); break; default: - PMD_DRV_LOG(DEBUG, "Invalid phy_index %d", phy_index); + ELINK_DEBUG_P1(sc, "Invalid phy_index %d", phy_index); return ELINK_STATUS_ERROR; } return ext_phy_config; } - static elink_status_t elink_populate_int_phy(struct bnx2x_softc *sc, - uint32_t shmem_base, uint8_t port, - struct elink_phy *phy) + uint32_t shmem_base, uint8_t port, + struct elink_phy *phy) { uint32_t phy_addr; - __rte_unused uint32_t chip_id; + uint32_t chip_id; uint32_t switch_cfg = (REG_RD(sc, shmem_base + - offsetof(struct shmem_region, - dev_info. - port_feature_config[port]. - link_config)) & - PORT_FEATURE_CONNECTED_SWITCH_MASK); - chip_id = - (REG_RD(sc, MISC_REG_CHIP_NUM) << 16) | - ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12); - - PMD_DRV_LOG(DEBUG, ":chip_id = 0x%x", chip_id); + offsetof(struct shmem_region, + dev_info.port_feature_config[port].link_config)) & + PORT_FEATURE_CONNECTED_SWITCH_MASK); + chip_id = (REG_RD(sc, MISC_REG_CHIP_NUM) << 16) | + ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12); + + ELINK_DEBUG_P1(sc, ":chip_id = 0x%x", chip_id); if (USES_WARPCORE(sc)) { uint32_t serdes_net_if; - phy_addr = REG_RD(sc, MISC_REG_WC0_CTRL_PHY_ADDR); + phy_addr = REG_RD(sc, + MISC_REG_WC0_CTRL_PHY_ADDR); *phy = phy_warpcore; if (REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR) == 0x3) phy->flags |= ELINK_FLAGS_4_PORT_MODE; else phy->flags &= ~ELINK_FLAGS_4_PORT_MODE; - /* Check Dual mode */ + /* Check Dual mode */ serdes_net_if = (REG_RD(sc, shmem_base + - offsetof(struct shmem_region, - dev_info.port_hw_config[port]. - default_cfg)) & + offsetof(struct shmem_region, dev_info. + port_hw_config[port].default_cfg)) & PORT_HW_CFG_NET_SERDES_IF_MASK); /* Set the appropriate supported and flags indications per * interface type of the chip @@ -11280,8 +13164,8 @@ static elink_status_t elink_populate_int_phy(struct bnx2x_softc *sc, break; case PORT_HW_CFG_NET_SERDES_IF_KR: phy->media_type = ELINK_ETH_PHY_KR; - phy->supported &= (ELINK_SUPPORTED_1000baseT_Full | - ELINK_SUPPORTED_10000baseT_Full | + phy->supported &= (ELINK_SUPPORTED_1000baseKX_Full | + ELINK_SUPPORTED_10000baseKR_Full | ELINK_SUPPORTED_FIBRE | ELINK_SUPPORTED_Autoneg | ELINK_SUPPORTED_Pause | @@ -11299,8 +13183,8 @@ static elink_status_t elink_populate_int_phy(struct bnx2x_softc *sc, phy->media_type = ELINK_ETH_PHY_KR; phy->flags |= ELINK_FLAGS_WC_DUAL_MODE; phy->supported &= (ELINK_SUPPORTED_20000baseKR2_Full | - ELINK_SUPPORTED_10000baseT_Full | - ELINK_SUPPORTED_1000baseT_Full | + ELINK_SUPPORTED_10000baseKR_Full | + ELINK_SUPPORTED_1000baseKX_Full | ELINK_SUPPORTED_Autoneg | ELINK_SUPPORTED_FIBRE | ELINK_SUPPORTED_Pause | @@ -11308,8 +13192,8 @@ static elink_status_t elink_populate_int_phy(struct bnx2x_softc *sc, phy->flags &= ~ELINK_FLAGS_TX_ERROR_CHECK; break; default: - PMD_DRV_LOG(DEBUG, "Unknown WC interface type 0x%x", - serdes_net_if); + ELINK_DEBUG_P1(sc, "Unknown WC interface type 0x%x", + serdes_net_if); break; } @@ -11321,6 +13205,8 @@ static elink_status_t elink_populate_int_phy(struct bnx2x_softc *sc, phy->flags |= ELINK_FLAGS_MDC_MDIO_WA; else phy->flags |= ELINK_FLAGS_MDC_MDIO_WA_B0; + ELINK_DEBUG_P3(sc, "media_type = %x, flags = %x, supported = %x", + phy->media_type, phy->flags, phy->supported); } else { switch (switch_cfg) { case ELINK_SWITCH_CFG_1G: @@ -11336,32 +13222,32 @@ static elink_status_t elink_populate_int_phy(struct bnx2x_softc *sc, *phy = phy_xgxs; break; default: - PMD_DRV_LOG(DEBUG, "Invalid switch_cfg"); + ELINK_DEBUG_P0(sc, "Invalid switch_cfg"); return ELINK_STATUS_ERROR; } } - phy->addr = (uint8_t) phy_addr; + phy->addr = (uint8_t)phy_addr; phy->mdio_ctrl = elink_get_emac_base(sc, - SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH, - port); + SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH, + port); if (CHIP_IS_E2(sc)) phy->def_md_devad = ELINK_E2_DEFAULT_PHY_DEV_ADDR; else phy->def_md_devad = ELINK_DEFAULT_PHY_DEV_ADDR; - PMD_DRV_LOG(DEBUG, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x", - port, phy->addr, phy->mdio_ctrl); + ELINK_DEBUG_P3(sc, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x", + port, phy->addr, phy->mdio_ctrl); elink_populate_preemphasis(sc, shmem_base, phy, port, ELINK_INT_PHY); return ELINK_STATUS_OK; } static elink_status_t elink_populate_ext_phy(struct bnx2x_softc *sc, - uint8_t phy_index, - uint32_t shmem_base, - uint32_t shmem2_base, - uint8_t port, - struct elink_phy *phy) + uint8_t phy_index, + uint32_t shmem_base, + uint32_t shmem2_base, + uint8_t port, + struct elink_phy *phy) { uint32_t ext_phy_config, phy_type, config2; uint32_t mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH; @@ -11407,10 +13293,13 @@ static elink_status_t elink_populate_ext_phy(struct bnx2x_softc *sc, case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834: *phy = phy_84834; break; + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84858: + *phy = phy_84858; + break; case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54616: - case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE: + case PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X54618SE: *phy = phy_54618se; - if (phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE) + if (phy_type == PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X54618SE) phy->flags |= ELINK_FLAGS_EEE; break; case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101: @@ -11436,21 +13325,20 @@ static elink_status_t elink_populate_ext_phy(struct bnx2x_softc *sc, * the address */ config2 = REG_RD(sc, shmem_base + offsetof(struct shmem_region, - dev_info.shared_hw_config. - config2)); + dev_info.shared_hw_config.config2)); if (phy_index == ELINK_EXT_PHY1) { phy->ver_addr = shmem_base + offsetof(struct shmem_region, - port_mb[port]. - ext_phy_fw_version); + port_mb[port].ext_phy_fw_version); /* Check specific mdc mdio settings */ if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK) mdc_mdio_access = config2 & - SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK; + SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK; } else { uint32_t size = REG_RD(sc, shmem2_base); - if (size > offsetof(struct shmem2_region, ext_phy_fw_version2)) { + if (size > + offsetof(struct shmem2_region, ext_phy_fw_version2)) { phy->ver_addr = shmem2_base + offsetof(struct shmem2_region, ext_phy_fw_version2[port]); @@ -11458,35 +13346,34 @@ static elink_status_t elink_populate_ext_phy(struct bnx2x_softc *sc, /* Check specific mdc mdio settings */ if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) mdc_mdio_access = (config2 & - SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) - >> (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT - - SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT); + SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >> + (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT - + SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT); } phy->mdio_ctrl = elink_get_emac_base(sc, mdc_mdio_access, port); - if (((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) || - (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) && - (phy->ver_addr)) { + if (elink_is_8483x_8485x(phy) && (phy->ver_addr)) { /* Remove 100Mb link supported for BNX2X84833/4 when phy fw * version lower than or equal to 1.39 */ uint32_t raw_ver = REG_RD(sc, phy->ver_addr); - if (((raw_ver & 0x7F) <= 39) && (((raw_ver & 0xF80) >> 7) <= 1)) + if (((raw_ver & 0x7F) <= 39) && + (((raw_ver & 0xF80) >> 7) <= 1)) phy->supported &= ~(ELINK_SUPPORTED_100baseT_Half | ELINK_SUPPORTED_100baseT_Full); } - PMD_DRV_LOG(DEBUG, "phy_type 0x%x port %d found in index %d", - phy_type, port, phy_index); - PMD_DRV_LOG(DEBUG, " addr=0x%x, mdio_ctl=0x%x", - phy->addr, phy->mdio_ctrl); + ELINK_DEBUG_P3(sc, "phy_type 0x%x port %d found in index %d", + phy_type, port, phy_index); + ELINK_DEBUG_P2(sc, " addr=0x%x, mdio_ctl=0x%x", + phy->addr, phy->mdio_ctrl); return ELINK_STATUS_OK; } static elink_status_t elink_populate_phy(struct bnx2x_softc *sc, - uint8_t phy_index, uint32_t shmem_base, - uint32_t shmem2_base, uint8_t port, - struct elink_phy *phy) + uint8_t phy_index, uint32_t shmem_base, + uint32_t shmem2_base, uint8_t port, + struct elink_phy *phy) { elink_status_t status = ELINK_STATUS_OK; phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN; @@ -11498,50 +13385,44 @@ static elink_status_t elink_populate_phy(struct bnx2x_softc *sc, } static void elink_phy_def_cfg(struct elink_params *params, - struct elink_phy *phy, uint8_t phy_index) + struct elink_phy *phy, + uint8_t phy_index) { struct bnx2x_softc *sc = params->sc; uint32_t link_config; /* Populate the default phy configuration for MF mode */ if (phy_index == ELINK_EXT_PHY2) { link_config = REG_RD(sc, params->shmem_base + - offsetof(struct shmem_region, - dev_info.port_feature_config - [params->port].link_config2)); - phy->speed_cap_mask = - REG_RD(sc, - params->shmem_base + offsetof(struct shmem_region, - dev_info.port_hw_config - [params->port]. - speed_capability_mask2)); + offsetof(struct shmem_region, dev_info. + port_feature_config[params->port].link_config2)); + phy->speed_cap_mask = REG_RD(sc, params->shmem_base + + offsetof(struct shmem_region, + dev_info. + port_hw_config[params->port].speed_capability_mask2)); } else { link_config = REG_RD(sc, params->shmem_base + - offsetof(struct shmem_region, - dev_info.port_feature_config - [params->port].link_config)); - phy->speed_cap_mask = - REG_RD(sc, - params->shmem_base + offsetof(struct shmem_region, - dev_info.port_hw_config - [params->port]. - speed_capability_mask)); + offsetof(struct shmem_region, dev_info. + port_feature_config[params->port].link_config)); + phy->speed_cap_mask = REG_RD(sc, params->shmem_base + + offsetof(struct shmem_region, + dev_info. + port_hw_config[params->port].speed_capability_mask)); } - - PMD_DRV_LOG(DEBUG, - "Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x", - phy_index, link_config, phy->speed_cap_mask); + ELINK_DEBUG_P3(sc, + "Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x", + phy_index, link_config, phy->speed_cap_mask); phy->req_duplex = DUPLEX_FULL; - switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) { + switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) { case PORT_FEATURE_LINK_SPEED_10M_HALF: phy->req_duplex = DUPLEX_HALF; - /* fall-through */ + /* fallthrough */ case PORT_FEATURE_LINK_SPEED_10M_FULL: phy->req_line_speed = ELINK_SPEED_10; break; case PORT_FEATURE_LINK_SPEED_100M_HALF: phy->req_duplex = DUPLEX_HALF; - /* fall-through */ + /* fallthrough */ case PORT_FEATURE_LINK_SPEED_100M_FULL: phy->req_line_speed = ELINK_SPEED_100; break; @@ -11559,7 +13440,10 @@ static void elink_phy_def_cfg(struct elink_params *params, break; } - switch (link_config & PORT_FEATURE_FLOW_CONTROL_MASK) { + ELINK_DEBUG_P2(sc, "Default config phy idx %x, req_duplex config %x", + phy_index, phy->req_duplex); + + switch (link_config & PORT_FEATURE_FLOW_CONTROL_MASK) { case PORT_FEATURE_FLOW_CONTROL_AUTO: phy->req_flow_ctrl = ELINK_FLOW_CTRL_AUTO; break; @@ -11576,6 +13460,9 @@ static void elink_phy_def_cfg(struct elink_params *params, phy->req_flow_ctrl = ELINK_FLOW_CTRL_NONE; break; } + ELINK_DEBUG_P3(sc, "Requested Duplex = %x, line_speed = %x, flow_ctrl = %x", + phy->req_duplex, phy->req_line_speed, + phy->req_flow_ctrl); } uint32_t elink_phy_selection(struct elink_params *params) @@ -11584,25 +13471,24 @@ uint32_t elink_phy_selection(struct elink_params *params) uint32_t return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT; phy_config_swapped = params->multi_phy_config & - PORT_HW_CFG_PHY_SWAPPED_ENABLED; + PORT_HW_CFG_PHY_SWAPPED_ENABLED; - prio_cfg = params->multi_phy_config & PORT_HW_CFG_PHY_SELECTION_MASK; + prio_cfg = params->multi_phy_config & + PORT_HW_CFG_PHY_SELECTION_MASK; if (phy_config_swapped) { switch (prio_cfg) { case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY: - return_cfg = - PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY; + return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY; break; case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY: - return_cfg = - PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY; + return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY; break; case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY: - return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY; + return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY; break; case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY: - return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY; + return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY; break; } } else @@ -11611,19 +13497,23 @@ uint32_t elink_phy_selection(struct elink_params *params) return return_cfg; } -elink_status_t elink_phy_probe(struct elink_params * params) +elink_status_t elink_phy_probe(struct elink_params *params) { uint8_t phy_index, actual_phy_idx; uint32_t phy_config_swapped, sync_offset, media_types; struct bnx2x_softc *sc = params->sc; struct elink_phy *phy; params->num_phys = 0; - PMD_DRV_LOG(DEBUG, "Begin phy probe"); - + ELINK_DEBUG_P0(sc, "Begin phy probe"); +#ifdef ELINK_INCLUDE_EMUL + if (CHIP_REV_IS_EMUL(sc)) + return ELINK_STATUS_OK; +#endif phy_config_swapped = params->multi_phy_config & - PORT_HW_CFG_PHY_SWAPPED_ENABLED; + PORT_HW_CFG_PHY_SWAPPED_ENABLED; - for (phy_index = ELINK_INT_PHY; phy_index < ELINK_MAX_PHYS; phy_index++) { + for (phy_index = ELINK_INT_PHY; phy_index < ELINK_MAX_PHYS; + phy_index++) { actual_phy_idx = phy_index; if (phy_config_swapped) { if (phy_index == ELINK_EXT_PHY1) @@ -11631,18 +13521,19 @@ elink_status_t elink_phy_probe(struct elink_params * params) else if (phy_index == ELINK_EXT_PHY2) actual_phy_idx = ELINK_EXT_PHY1; } - PMD_DRV_LOG(DEBUG, "phy_config_swapped %x, phy_index %x," - " actual_phy_idx %x", phy_config_swapped, - phy_index, actual_phy_idx); + ELINK_DEBUG_P3(sc, "phy_config_swapped %x, phy_index %x," + " actual_phy_idx %x", phy_config_swapped, + phy_index, actual_phy_idx); phy = ¶ms->phy[actual_phy_idx]; if (elink_populate_phy(sc, phy_index, params->shmem_base, params->shmem2_base, params->port, phy) != ELINK_STATUS_OK) { params->num_phys = 0; - PMD_DRV_LOG(DEBUG, "phy probe failed in phy index %d", - phy_index); + ELINK_DEBUG_P1(sc, "phy probe failed in phy index %d", + phy_index); for (phy_index = ELINK_INT_PHY; - phy_index < ELINK_MAX_PHYS; phy_index++) + phy_index < ELINK_MAX_PHYS; + phy_index++) *phy = phy_null; return ELINK_STATUS_ERROR; } @@ -11658,8 +13549,8 @@ elink_status_t elink_phy_probe(struct elink_params * params) phy->flags |= ELINK_FLAGS_MDC_MDIO_WA_G; sync_offset = params->shmem_base + - offsetof(struct shmem_region, - dev_info.port_hw_config[params->port].media_type); + offsetof(struct shmem_region, + dev_info.port_hw_config[params->port].media_type); media_types = REG_RD(sc, sync_offset); /* Update media type for non-PMF sync only for the first time @@ -11670,9 +13561,9 @@ elink_status_t elink_phy_probe(struct elink_params * params) (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * actual_phy_idx))) == 0) { media_types |= ((phy->media_type & - PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) << - (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * - actual_phy_idx)); + PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) << + (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * + actual_phy_idx)); } REG_WR(sc, sync_offset, media_types); @@ -11680,47 +13571,231 @@ elink_status_t elink_phy_probe(struct elink_params * params) params->num_phys++; } - PMD_DRV_LOG(DEBUG, "End phy probe. #phys found %x", params->num_phys); + ELINK_DEBUG_P1(sc, "End phy probe. #phys found %x", params->num_phys); return ELINK_STATUS_OK; } -static void elink_init_bmac_loopback(struct elink_params *params, - struct elink_vars *vars) +#ifdef ELINK_INCLUDE_EMUL +static elink_status_t elink_init_e3_emul_mac(struct elink_params *params, + struct elink_vars *vars) +{ + struct bnx2x_softc *sc = params->sc; + vars->line_speed = params->req_line_speed[0]; + /* In case link speed is auto, set speed the highest as possible */ + if (params->req_line_speed[0] == ELINK_SPEED_AUTO_NEG) { + if (params->feature_config_flags & + ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC) + vars->line_speed = ELINK_SPEED_2500; + else if (elink_is_4_port_mode(sc)) + vars->line_speed = ELINK_SPEED_10000; + else + vars->line_speed = ELINK_SPEED_20000; + } + if (vars->line_speed < ELINK_SPEED_10000) { + if ((params->feature_config_flags & + ELINK_FEATURE_CONFIG_EMUL_DISABLE_UMAC)) { + ELINK_DEBUG_P1(sc, "Invalid line speed %d while UMAC is" + " disabled!", params->req_line_speed[0]); + return ELINK_STATUS_ERROR; + } + switch (vars->line_speed) { + case ELINK_SPEED_10: + vars->link_status = ELINK_LINK_10TFD; + break; + case ELINK_SPEED_100: + vars->link_status = ELINK_LINK_100TXFD; + break; + case ELINK_SPEED_1000: + vars->link_status = ELINK_LINK_1000TFD; + break; + case ELINK_SPEED_2500: + vars->link_status = ELINK_LINK_2500TFD; + break; + default: + ELINK_DEBUG_P1(sc, "Invalid line speed %d for UMAC", + vars->line_speed); + return ELINK_STATUS_ERROR; + } + vars->link_status |= LINK_STATUS_LINK_UP; + + if (params->loopback_mode == ELINK_LOOPBACK_UMAC) + elink_umac_enable(params, vars, 1); + else + elink_umac_enable(params, vars, 0); + } else { + /* Link speed >= 10000 requires XMAC enabled */ + if (params->feature_config_flags & + ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC) { + ELINK_DEBUG_P1(sc, "Invalid line speed %d while XMAC is" + " disabled!", params->req_line_speed[0]); + return ELINK_STATUS_ERROR; + } + /* Check link speed */ + switch (vars->line_speed) { + case ELINK_SPEED_10000: + vars->link_status = ELINK_LINK_10GTFD; + break; + case ELINK_SPEED_20000: + vars->link_status = ELINK_LINK_20GTFD; + break; + default: + ELINK_DEBUG_P1(sc, "Invalid line speed %d for XMAC", + vars->line_speed); + return ELINK_STATUS_ERROR; + } + vars->link_status |= LINK_STATUS_LINK_UP; + if (params->loopback_mode == ELINK_LOOPBACK_XMAC) + elink_xmac_enable(params, vars, 1); + else + elink_xmac_enable(params, vars, 0); + } + return ELINK_STATUS_OK; +} + +static elink_status_t elink_init_emul(struct elink_params *params, + struct elink_vars *vars) { struct bnx2x_softc *sc = params->sc; + if (CHIP_IS_E3(sc)) { + if (elink_init_e3_emul_mac(params, vars) != + ELINK_STATUS_OK) + return ELINK_STATUS_ERROR; + } else { + if (params->feature_config_flags & + ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC) { + vars->line_speed = ELINK_SPEED_1000; + vars->link_status = (LINK_STATUS_LINK_UP | + ELINK_LINK_1000XFD); + if (params->loopback_mode == + ELINK_LOOPBACK_EMAC) + elink_emac_enable(params, vars, 1); + else + elink_emac_enable(params, vars, 0); + } else { + vars->line_speed = ELINK_SPEED_10000; + vars->link_status = (LINK_STATUS_LINK_UP | + ELINK_LINK_10GTFD); + if (params->loopback_mode == + ELINK_LOOPBACK_BMAC) + elink_bmac_enable(params, vars, 1, 1); + else + elink_bmac_enable(params, vars, 0, 1); + } + } vars->link_up = 1; - vars->line_speed = ELINK_SPEED_10000; vars->duplex = DUPLEX_FULL; vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; - vars->mac_type = ELINK_MAC_TYPE_BMAC; - vars->phy_flags = PHY_XGXS_FLAG; - - elink_xgxs_deassert(params); + if (CHIP_IS_E1x(sc)) + elink_pbf_update(params, vars->flow_ctrl, + vars->line_speed); + /* Disable drain */ + REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0); - /* Set bmac loopback */ - elink_bmac_enable(params, vars, 1, 1); + /* update shared memory */ + elink_update_mng(params, vars->link_status); + return ELINK_STATUS_OK; +} +#endif +#ifdef ELINK_INCLUDE_FPGA +static elink_status_t elink_init_fpga(struct elink_params *params, + struct elink_vars *vars) +{ + /* Enable on E1.5 FPGA */ + struct bnx2x_softc *sc = params->sc; + vars->duplex = DUPLEX_FULL; + vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; + if (!(CHIP_IS_E1(sc))) { + vars->flow_ctrl = (ELINK_FLOW_CTRL_TX | + ELINK_FLOW_CTRL_RX); + vars->link_status |= (LINK_STATUS_TX_FLOW_CONTROL_ENABLED | + LINK_STATUS_RX_FLOW_CONTROL_ENABLED); + } + if (CHIP_IS_E3(sc)) { + vars->line_speed = params->req_line_speed[0]; + switch (vars->line_speed) { + case ELINK_SPEED_AUTO_NEG: + vars->line_speed = ELINK_SPEED_2500; + case ELINK_SPEED_2500: + vars->link_status = ELINK_LINK_2500TFD; + break; + case ELINK_SPEED_1000: + vars->link_status = ELINK_LINK_1000XFD; + break; + case ELINK_SPEED_100: + vars->link_status = ELINK_LINK_100TXFD; + break; + case ELINK_SPEED_10: + vars->link_status = ELINK_LINK_10TFD; + break; + default: + ELINK_DEBUG_P1(sc, "Invalid link speed %d", + params->req_line_speed[0]); + return ELINK_STATUS_ERROR; + } + vars->link_status |= LINK_STATUS_LINK_UP; + if (params->loopback_mode == ELINK_LOOPBACK_UMAC) + elink_umac_enable(params, vars, 1); + else + elink_umac_enable(params, vars, 0); + } else { + vars->line_speed = ELINK_SPEED_10000; + vars->link_status = (LINK_STATUS_LINK_UP | ELINK_LINK_10GTFD); + if (params->loopback_mode == ELINK_LOOPBACK_EMAC) + elink_emac_enable(params, vars, 1); + else + elink_emac_enable(params, vars, 0); + } + vars->link_up = 1; + if (CHIP_IS_E1x(sc)) + elink_pbf_update(params, vars->flow_ctrl, + vars->line_speed); + /* Disable drain */ REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0); + + /* Update shared memory */ + elink_update_mng(params, vars->link_status); + return ELINK_STATUS_OK; +} +#endif +static void elink_init_bmac_loopback(struct elink_params *params, + struct elink_vars *vars) +{ + struct bnx2x_softc *sc = params->sc; + vars->link_up = 1; + vars->line_speed = ELINK_SPEED_10000; + vars->duplex = DUPLEX_FULL; + vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; + vars->mac_type = ELINK_MAC_TYPE_BMAC; + + vars->phy_flags = PHY_XGXS_FLAG; + + elink_xgxs_deassert(params); + + /* Set bmac loopback */ + elink_bmac_enable(params, vars, 1, 1); + + REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0); } static void elink_init_emac_loopback(struct elink_params *params, struct elink_vars *vars) { struct bnx2x_softc *sc = params->sc; - vars->link_up = 1; - vars->line_speed = ELINK_SPEED_1000; - vars->duplex = DUPLEX_FULL; - vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; - vars->mac_type = ELINK_MAC_TYPE_EMAC; + vars->link_up = 1; + vars->line_speed = ELINK_SPEED_1000; + vars->duplex = DUPLEX_FULL; + vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; + vars->mac_type = ELINK_MAC_TYPE_EMAC; - vars->phy_flags = PHY_XGXS_FLAG; + vars->phy_flags = PHY_XGXS_FLAG; - elink_xgxs_deassert(params); - /* Set bmac loopback */ - elink_emac_enable(params, vars, 1); - elink_emac_program(params, vars); - REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0); + elink_xgxs_deassert(params); + /* Set bmac loopback */ + elink_emac_enable(params, vars, 1); + elink_emac_program(params, vars); + REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0); } static void elink_init_xmac_loopback(struct elink_params *params, @@ -11741,8 +13816,9 @@ static void elink_init_xmac_loopback(struct elink_params *params, */ elink_set_aer_mmd(params, ¶ms->phy[0]); elink_warpcore_reset_lane(sc, ¶ms->phy[0], 0); - params->phy[ELINK_INT_PHY].config_loopback(¶ms->phy[ELINK_INT_PHY], - params); + params->phy[ELINK_INT_PHY].config_loopback( + ¶ms->phy[ELINK_INT_PHY], + params); elink_xmac_enable(params, vars, 1); REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0); @@ -11804,12 +13880,11 @@ static void elink_init_xgxs_loopback(struct elink_params *params, /* Set external phy loopback */ uint8_t phy_index; for (phy_index = ELINK_EXT_PHY1; - phy_index < params->num_phys; phy_index++) + phy_index < params->num_phys; phy_index++) if (params->phy[phy_index].config_loopback) - params->phy[phy_index].config_loopback(¶ms-> - phy - [phy_index], - params); + params->phy[phy_index].config_loopback( + ¶ms->phy[phy_index], + params); } REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0); @@ -11826,12 +13901,14 @@ void elink_set_rx_filter(struct elink_params *params, uint8_t en) val |= en * 0x20; REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK + params->port * 4, val); - REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK_MF + params->port * 4, en * 0x3); + if (!CHIP_IS_E1(sc)) { + REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK_MF + params->port * 4, + en * 0x3); + } REG_WR(sc, (params->port ? NIG_REG_LLH1_BRB1_NOT_MCP : NIG_REG_LLH0_BRB1_NOT_MCP), en); } - static elink_status_t elink_avoid_link_flap(struct elink_params *params, struct elink_vars *vars) { @@ -11839,6 +13916,7 @@ static elink_status_t elink_avoid_link_flap(struct elink_params *params, uint32_t dont_clear_stat, lfa_sts; struct bnx2x_softc *sc = params->sc; + elink_set_mdio_emac_per_phy(sc, params); /* Sync the link parameters */ elink_link_status_update(params, vars); @@ -11850,7 +13928,7 @@ static elink_status_t elink_avoid_link_flap(struct elink_params *params, for (phy_idx = ELINK_INT_PHY; phy_idx < params->num_phys; phy_idx++) { struct elink_phy *phy = ¶ms->phy[phy_idx]; if (phy->phy_specific_func) { - PMD_DRV_LOG(DEBUG, "Calling PHY specific func"); + ELINK_DEBUG_P0(sc, "Calling PHY specific func"); phy->phy_specific_func(phy, params, ELINK_PHY_INIT); } if ((phy->media_type == ELINK_ETH_PHY_SFPP_10G_FIBER) || @@ -11859,7 +13937,8 @@ static elink_status_t elink_avoid_link_flap(struct elink_params *params, elink_verify_sfp_module(phy, params); } lfa_sts = REG_RD(sc, params->lfa_base + - offsetof(struct shmem_lfa, lfa_sts)); + offsetof(struct shmem_lfa, + lfa_sts)); dont_clear_stat = lfa_sts & SHMEM_LFA_DONT_CLEAR_STAT; @@ -11970,12 +14049,12 @@ elink_status_t elink_phy_init(struct elink_params *params, { int lfa_status; struct bnx2x_softc *sc = params->sc; - PMD_DRV_LOG(DEBUG, "Phy Initialization started"); - PMD_DRV_LOG(DEBUG, "(1) req_speed %d, req_flowctrl %d", - params->req_line_speed[0], params->req_flow_ctrl[0]); - PMD_DRV_LOG(DEBUG, "(2) req_speed %d, req_flowctrl %d", - params->req_line_speed[1], params->req_flow_ctrl[1]); - PMD_DRV_LOG(DEBUG, "req_adv_flow_ctrl 0x%x", params->req_fc_auto_adv); + ELINK_DEBUG_P0(sc, "Phy Initialization started"); + ELINK_DEBUG_P2(sc, "(1) req_speed %d, req_flowctrl %d", + params->req_line_speed[0], params->req_flow_ctrl[0]); + ELINK_DEBUG_P2(sc, "(2) req_speed %d, req_flowctrl %d", + params->req_line_speed[1], params->req_flow_ctrl[1]); + ELINK_DEBUG_P1(sc, "req_adv_flow_ctrl 0x%x", params->req_fc_auto_adv); vars->link_status = 0; vars->phy_link_up = 0; vars->link_up = 0; @@ -11988,15 +14067,33 @@ elink_status_t elink_phy_init(struct elink_params *params, params->link_flags = ELINK_PHY_INITIALIZED; /* Driver opens NIG-BRB filters */ elink_set_rx_filter(params, 1); + elink_chng_link_count(params, 1); /* Check if link flap can be avoided */ lfa_status = elink_check_lfa(params); + ELINK_DEBUG_P3(sc, " params : port = %x, loopback_mode = %x req_duplex = %x", + params->port, params->loopback_mode, + params->req_duplex[0]); + ELINK_DEBUG_P3(sc, " params : switch_cfg = %x, lane_config = %x req_duplex[1] = %x", + params->switch_cfg, params->lane_config, + params->req_duplex[1]); + ELINK_DEBUG_P3(sc, " params : chip_id = %x, feature_config_flags = %x, num_phys = %x", + params->chip_id, params->feature_config_flags, + params->num_phys); + ELINK_DEBUG_P3(sc, " params : rsrv = %x, eee_mode = %x, hw_led_mode = %x", + params->rsrv, params->eee_mode, params->hw_led_mode); + ELINK_DEBUG_P3(sc, " params : multi_phy = %x, req_fc_auto_adv = %x, link_flags = %x", + params->multi_phy_config, params->req_fc_auto_adv, + params->link_flags); + ELINK_DEBUG_P2(sc, " params : lfa_base = %x, link_attr = %x", + params->lfa_base, params->link_attr_sync); if (lfa_status == 0) { - PMD_DRV_LOG(DEBUG, "Link Flap Avoidance in progress"); + ELINK_DEBUG_P0(sc, "Link Flap Avoidance in progress"); return elink_avoid_link_flap(params, vars); } - PMD_DRV_LOG(DEBUG, "Cannot avoid link flap lfa_sta=0x%x", lfa_status); + ELINK_DEBUG_P1(sc, "Cannot avoid link flap lfa_sta=0x%x", + lfa_status); elink_cannot_avoid_link_flap(params, vars, lfa_status); /* Disable attentions */ @@ -12005,20 +14102,34 @@ elink_status_t elink_phy_init(struct elink_params *params, ELINK_NIG_MASK_XGXS0_LINK10G | ELINK_NIG_MASK_SERDES0_LINK_STATUS | ELINK_NIG_MASK_MI_INT)); +#ifdef ELINK_INCLUDE_EMUL + if (!(params->feature_config_flags & + ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC)) +#endif - elink_emac_init(params); + elink_emac_init(params, vars); if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) vars->link_status |= LINK_STATUS_PFC_ENABLED; - if ((params->num_phys == 0) && !CHIP_REV_IS_SLOW(sc)) { - PMD_DRV_LOG(DEBUG, "No phy found for initialization !!"); + if ((params->num_phys == 0) && + !CHIP_REV_IS_SLOW(sc)) { + ELINK_DEBUG_P0(sc, "No phy found for initialization !!"); return ELINK_STATUS_ERROR; } set_phy_vars(params, vars); - PMD_DRV_LOG(DEBUG, "Num of phys on board: %d", params->num_phys); - + ELINK_DEBUG_P1(sc, "Num of phys on board: %d", params->num_phys); +#ifdef ELINK_INCLUDE_FPGA + if (CHIP_REV_IS_FPGA(sc)) { + return elink_init_fpga(params, vars); + } else +#endif +#ifdef ELINK_INCLUDE_EMUL + if (CHIP_REV_IS_EMUL(sc)) { + return elink_init_emul(params, vars); + } else +#endif switch (params->loopback_mode) { case ELINK_LOOPBACK_BMAC: elink_init_bmac_loopback(params, vars); @@ -12054,15 +14165,16 @@ elink_status_t elink_phy_init(struct elink_params *params, return ELINK_STATUS_OK; } -static elink_status_t elink_link_reset(struct elink_params *params, - struct elink_vars *vars, - uint8_t reset_ext_phy) +elink_status_t elink_link_reset(struct elink_params *params, + struct elink_vars *vars, + uint8_t reset_ext_phy) { struct bnx2x_softc *sc = params->sc; uint8_t phy_index, port = params->port, clear_latch_ind = 0; - PMD_DRV_LOG(DEBUG, "Resetting the link of port %d", port); + ELINK_DEBUG_P1(sc, "Resetting the link of port %d", port); /* Disable attentions */ vars->link_status = 0; + elink_chng_link_count(params, 1); elink_update_mng(params, vars->link_status); vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK | SHMEM_EEE_ACTIVE_BIT); @@ -12081,12 +14193,24 @@ static elink_status_t elink_link_reset(struct elink_params *params, REG_WR(sc, NIG_REG_BMAC0_OUT_EN + port * 4, 0); REG_WR(sc, NIG_REG_EGRESS_EMAC0_OUT_EN + port * 4, 0); } - if (!CHIP_IS_E3(sc)) - elink_set_bmac_rx(sc, port, 0); - if (CHIP_IS_E3(sc) && !CHIP_REV_IS_FPGA(sc)) { - elink_set_xmac_rxtx(params, 0); - elink_set_umac_rxtx(params, 0); - } + +#ifdef ELINK_INCLUDE_EMUL + /* Stop BigMac rx */ + if (!(params->feature_config_flags & + ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC)) +#endif + if (!CHIP_IS_E3(sc)) + elink_set_bmac_rx(sc, params->chip_id, port, 0); +#ifdef ELINK_INCLUDE_EMUL + /* Stop XMAC/UMAC rx */ + if (!(params->feature_config_flags & + ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC)) +#endif + if (CHIP_IS_E3(sc) && + !CHIP_REV_IS_FPGA(sc)) { + elink_set_xmac_rxtx(params, 0); + elink_set_umac_rxtx(params, 0); + } /* Disable emac */ if (!CHIP_IS_E3(sc)) REG_WR(sc, NIG_REG_NIG_EMAC0_EN + port * 4, 0); @@ -12095,20 +14219,19 @@ static elink_status_t elink_link_reset(struct elink_params *params, /* The PHY reset is controlled by GPIO 1 * Hold it as vars low */ - /* Clear link led */ + /* Clear link led */ elink_set_mdio_emac_per_phy(sc, params); elink_set_led(params, vars, ELINK_LED_MODE_OFF, 0); if (reset_ext_phy && (!CHIP_REV_IS_SLOW(sc))) { for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys; - phy_index++) { + phy_index++) { if (params->phy[phy_index].link_reset) { elink_set_aer_mmd(params, ¶ms->phy[phy_index]); - params->phy[phy_index].link_reset(¶ms-> - phy - [phy_index], - params); + params->phy[phy_index].link_reset( + ¶ms->phy[phy_index], + params); } if (params->phy[phy_index].flags & ELINK_FLAGS_REARM_LATCH_SIGNAL) @@ -12122,11 +14245,12 @@ static elink_status_t elink_link_reset(struct elink_params *params, elink_bits_dis(sc, NIG_REG_LATCH_BC_0 + port * 4, 1 << ELINK_NIG_LATCH_BC_ENABLE_MI_INT); } +#if defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA) + if (!CHIP_REV_IS_SLOW(sc)) +#endif if (params->phy[ELINK_INT_PHY].link_reset) - params->phy[ELINK_INT_PHY].link_reset(¶ms-> - phy - [ELINK_INT_PHY], - params); + params->phy[ELINK_INT_PHY].link_reset( + ¶ms->phy[ELINK_INT_PHY], params); /* Disable nig ingress interface */ if (!CHIP_IS_E3(sc)) { @@ -12136,8 +14260,8 @@ static elink_status_t elink_link_reset(struct elink_params *params, REG_WR(sc, NIG_REG_BMAC0_IN_EN + port * 4, 0); REG_WR(sc, NIG_REG_EMAC0_IN_EN + port * 4, 0); } else { - uint32_t xmac_base = - (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; + uint32_t xmac_base = (params->port) ? GRCBASE_XMAC1 : + GRCBASE_XMAC0; elink_set_xumac_nig(params, 0, 0); if (REG_RD(sc, MISC_REG_RESET_REG_2) & MISC_REGISTERS_RESET_REG_2_XMAC) @@ -12148,9 +14272,8 @@ static elink_status_t elink_link_reset(struct elink_params *params, vars->phy_flags = 0; return ELINK_STATUS_OK; } - -elink_status_t elink_lfa_reset(struct elink_params * params, - struct elink_vars * vars) +elink_status_t elink_lfa_reset(struct elink_params *params, + struct elink_vars *vars) { struct bnx2x_softc *sc = params->sc; vars->link_up = 0; @@ -12169,13 +14292,13 @@ elink_status_t elink_lfa_reset(struct elink_params * params, * are passed. */ if (!CHIP_IS_E3(sc)) - elink_set_bmac_rx(sc, params->port, 0); + elink_set_bmac_rx(sc, params->chip_id, params->port, 0); if (CHIP_IS_E3(sc)) { elink_set_xmac_rxtx(params, 0); elink_set_umac_rxtx(params, 0); } - /* Wait 10ms for the pipe to clean up */ + /* Wait 10ms for the pipe to clean up*/ DELAY(1000 * 10); /* Clean the NIG-BRB using the network filters in a way that will @@ -12190,7 +14313,7 @@ elink_status_t elink_lfa_reset(struct elink_params * params, * minimum management protocol down time. */ if (!CHIP_IS_E3(sc)) - elink_set_bmac_rx(sc, params->port, 1); + elink_set_bmac_rx(sc, params->chip_id, params->port, 1); if (CHIP_IS_E3(sc)) { elink_set_xmac_rxtx(params, 1); @@ -12205,10 +14328,10 @@ elink_status_t elink_lfa_reset(struct elink_params * params, /* Common function */ /****************************************************************************/ static elink_status_t elink_8073_common_init_phy(struct bnx2x_softc *sc, - uint32_t shmem_base_path[], - uint32_t shmem2_base_path[], - uint8_t phy_index, - __rte_unused uint32_t chip_id) + uint32_t shmem_base_path[], + uint32_t shmem2_base_path[], + uint8_t phy_index, + __rte_unused uint32_t chip_id) { struct elink_phy phy[PORT_MAX]; struct elink_phy *phy_blk[PORT_MAX]; @@ -12216,8 +14339,8 @@ static elink_status_t elink_8073_common_init_phy(struct bnx2x_softc *sc, int8_t port = 0; int8_t port_of_path = 0; uint32_t swap_val, swap_override; - swap_val = REG_RD(sc, NIG_REG_PORT_SWAP); - swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE); + swap_val = REG_RD(sc, NIG_REG_PORT_SWAP); + swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE); port ^= (swap_val && swap_override); elink_ext_phy_hw_reset(sc, port); /* PART1 - Reset both phys */ @@ -12238,7 +14361,7 @@ static elink_status_t elink_8073_common_init_phy(struct bnx2x_softc *sc, if (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base, port_of_path, &phy[port]) != ELINK_STATUS_OK) { - PMD_DRV_LOG(DEBUG, "populate_phy failed"); + ELINK_DEBUG_P0(sc, "populate_phy failed"); return ELINK_STATUS_ERROR; } /* Disable attentions */ @@ -12253,11 +14376,14 @@ static elink_status_t elink_8073_common_init_phy(struct bnx2x_softc *sc, * to write to access its registers */ elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2, - MISC_REGISTERS_GPIO_OUTPUT_HIGH, port); + MISC_REGISTERS_GPIO_OUTPUT_HIGH, + port); /* Reset the phy */ elink_cl45_write(sc, &phy[port], - MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1 << 15); + MDIO_PMA_DEVAD, + MDIO_PMA_REG_CTRL, + 1 << 15); } /* Add delay of 150ms after reset */ @@ -12278,8 +14404,8 @@ static elink_status_t elink_8073_common_init_phy(struct bnx2x_softc *sc, else port_of_path = 0; - PMD_DRV_LOG(DEBUG, "Loading spirom for phy address 0x%x", - phy_blk[port]->addr); + ELINK_DEBUG_P1(sc, "Loading spirom for phy address 0x%x", + phy_blk[port]->addr); if (elink_8073_8727_external_rom_boot(sc, phy_blk[port], port_of_path)) return ELINK_STATUS_ERROR; @@ -12292,7 +14418,8 @@ static elink_status_t elink_8073_common_init_phy(struct bnx2x_softc *sc, /* Phase1 of TX_POWER_DOWN reset */ elink_cl45_write(sc, phy_blk[port], MDIO_PMA_DEVAD, - MDIO_PMA_REG_TX_POWER_DOWN, (val | 1 << 10)); + MDIO_PMA_REG_TX_POWER_DOWN, + (val | 1 << 10)); } /* Toggle Transmitter: Power down and then up with 600ms delay @@ -12309,9 +14436,9 @@ static elink_status_t elink_8073_common_init_phy(struct bnx2x_softc *sc, MDIO_PMA_REG_TX_POWER_DOWN, &val); elink_cl45_write(sc, phy_blk[port], - MDIO_PMA_DEVAD, - MDIO_PMA_REG_TX_POWER_DOWN, - (val & (~(1 << 10)))); + MDIO_PMA_DEVAD, + MDIO_PMA_REG_TX_POWER_DOWN, + (val & (~(1 << 10)))); DELAY(1000 * 15); /* Read modify write the SPI-ROM version select register */ @@ -12324,16 +14451,15 @@ static elink_status_t elink_8073_common_init_phy(struct bnx2x_softc *sc, /* set GPIO2 back to LOW */ elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2, - MISC_REGISTERS_GPIO_OUTPUT_LOW, port); + MISC_REGISTERS_GPIO_OUTPUT_LOW, port); } return ELINK_STATUS_OK; } - static elink_status_t elink_8726_common_init_phy(struct bnx2x_softc *sc, - uint32_t shmem_base_path[], - uint32_t shmem2_base_path[], - uint8_t phy_index, - __rte_unused uint32_t chip_id) + uint32_t shmem_base_path[], + uint32_t shmem2_base_path[], + uint8_t phy_index, + __rte_unused uint32_t chip_id) { uint32_t val; int8_t port; @@ -12342,8 +14468,8 @@ static elink_status_t elink_8726_common_init_phy(struct bnx2x_softc *sc, /* Enable the module detection interrupt */ val = REG_RD(sc, MISC_REG_GPIO_EVENT_EN); val |= ((1 << MISC_REGISTERS_GPIO_3) | - (1 << - (MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT))); + (1 << (MISC_REGISTERS_GPIO_3 + + MISC_REGISTERS_GPIO_PORT_SHIFT))); REG_WR(sc, MISC_REG_GPIO_EVENT_EN, val); elink_ext_phy_hw_reset(sc, 0); @@ -12361,33 +14487,33 @@ static elink_status_t elink_8726_common_init_phy(struct bnx2x_softc *sc, } /* Extract the ext phy address for the port */ if (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base, - port, &phy) != ELINK_STATUS_OK) { - PMD_DRV_LOG(DEBUG, "populate phy failed"); + port, &phy) != + ELINK_STATUS_OK) { + ELINK_DEBUG_P0(sc, "populate phy failed"); return ELINK_STATUS_ERROR; } - /* Reset phy */ + /* Reset phy*/ elink_cl45_write(sc, &phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001); + /* Set fault module detected LED on */ elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_0, - MISC_REGISTERS_GPIO_HIGH, port); + MISC_REGISTERS_GPIO_HIGH, + port); } return ELINK_STATUS_OK; } - static void elink_get_ext_phy_reset_gpio(struct bnx2x_softc *sc, - uint32_t shmem_base, uint8_t * io_gpio, - uint8_t * io_port) + uint32_t shmem_base, + uint8_t *io_gpio, uint8_t *io_port) { uint32_t phy_gpio_reset = REG_RD(sc, shmem_base + - offsetof(struct shmem_region, - dev_info. - port_hw_config[PORT_0]. - default_cfg)); + offsetof(struct shmem_region, + dev_info.port_hw_config[PORT_0].default_cfg)); switch (phy_gpio_reset) { case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0: *io_gpio = 0; @@ -12428,10 +14554,10 @@ static void elink_get_ext_phy_reset_gpio(struct bnx2x_softc *sc, } static elink_status_t elink_8727_common_init_phy(struct bnx2x_softc *sc, - uint32_t shmem_base_path[], - uint32_t shmem2_base_path[], - uint8_t phy_index, - __rte_unused uint32_t chip_id) + uint32_t shmem_base_path[], + uint32_t shmem2_base_path[], + uint8_t phy_index, + __rte_unused uint32_t chip_id) { int8_t port, reset_gpio; uint32_t swap_val, swap_override; @@ -12448,18 +14574,17 @@ static elink_status_t elink_8727_common_init_phy(struct bnx2x_softc *sc, * Default is GPIO1, PORT1 */ elink_get_ext_phy_reset_gpio(sc, shmem_base_path[0], - (uint8_t *) & reset_gpio, - (uint8_t *) & port); + (uint8_t *)&reset_gpio, (uint8_t *)&port); /* Calculate the port based on port swap */ port ^= (swap_val && swap_override); - /* Initiate PHY reset */ + /* Initiate PHY reset*/ elink_cb_gpio_write(sc, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW, - port); + port); DELAY(1000 * 1); elink_cb_gpio_write(sc, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH, - port); + port); DELAY(1000 * 5); @@ -12481,8 +14606,8 @@ static elink_status_t elink_8727_common_init_phy(struct bnx2x_softc *sc, /* Extract the ext phy address for the port */ if (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base, port_of_path, &phy[port]) != - ELINK_STATUS_OK) { - PMD_DRV_LOG(DEBUG, "populate phy failed"); + ELINK_STATUS_OK) { + ELINK_DEBUG_P0(sc, "populate phy failed"); return ELINK_STATUS_ERROR; } /* disable attentions */ @@ -12493,6 +14618,7 @@ static elink_status_t elink_8727_common_init_phy(struct bnx2x_softc *sc, ELINK_NIG_MASK_SERDES0_LINK_STATUS | ELINK_NIG_MASK_MI_INT)); + /* Reset the phy */ elink_cl45_write(sc, &phy[port], MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1 << 15); @@ -12513,25 +14639,25 @@ static elink_status_t elink_8727_common_init_phy(struct bnx2x_softc *sc, port_of_path = port; else port_of_path = 0; - PMD_DRV_LOG(DEBUG, "Loading spirom for phy address 0x%x", - phy_blk[port]->addr); + ELINK_DEBUG_P1(sc, "Loading spirom for phy address 0x%x", + phy_blk[port]->addr); if (elink_8073_8727_external_rom_boot(sc, phy_blk[port], port_of_path)) return ELINK_STATUS_ERROR; /* Disable PHY transmitter output */ elink_cl45_write(sc, phy_blk[port], - MDIO_PMA_DEVAD, MDIO_PMA_REG_TX_DISABLE, 1); + MDIO_PMA_DEVAD, + MDIO_PMA_REG_TX_DISABLE, 1); } return ELINK_STATUS_OK; } static elink_status_t elink_84833_common_init_phy(struct bnx2x_softc *sc, - uint32_t shmem_base_path[], - __rte_unused uint32_t - shmem2_base_path[], - __rte_unused uint8_t - phy_index, uint32_t chip_id) + uint32_t shmem_base_path[], + __rte_unused uint32_t shmem2_base_path[], + __rte_unused uint8_t phy_index, + uint32_t chip_id) { uint8_t reset_gpios; reset_gpios = elink_84833_get_reset_gpios(sc, shmem_base_path, chip_id); @@ -12540,16 +14666,15 @@ static elink_status_t elink_84833_common_init_phy(struct bnx2x_softc *sc, DELAY(10); elink_cb_gpio_mult_write(sc, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_HIGH); - PMD_DRV_LOG(DEBUG, "84833 reset pulse on pin values 0x%x", reset_gpios); + ELINK_DEBUG_P1(sc, "84833 reset pulse on pin values 0x%x", + reset_gpios); return ELINK_STATUS_OK; } - static elink_status_t elink_ext_phy_common_init(struct bnx2x_softc *sc, - uint32_t shmem_base_path[], - uint32_t shmem2_base_path[], - uint8_t phy_index, - uint32_t ext_phy_type, - uint32_t chip_id) + uint32_t shmem_base_path[], + uint32_t shmem2_base_path[], + uint8_t phy_index, + uint32_t ext_phy_type, uint32_t chip_id) { elink_status_t rc = ELINK_STATUS_OK; @@ -12577,44 +14702,50 @@ static elink_status_t elink_ext_phy_common_init(struct bnx2x_softc *sc, break; case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833: case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834: + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84858: /* GPIO3's are linked, and so both need to be toggled * to obtain required 2us pulse. */ rc = elink_84833_common_init_phy(sc, shmem_base_path, - shmem2_base_path, - phy_index, chip_id); + shmem2_base_path, + phy_index, chip_id); break; case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE: rc = ELINK_STATUS_ERROR; break; default: - PMD_DRV_LOG(DEBUG, - "ext_phy 0x%x common init not required", - ext_phy_type); + ELINK_DEBUG_P1(sc, + "ext_phy 0x%x common init not required", + ext_phy_type); break; } if (rc != ELINK_STATUS_OK) - elink_cb_event_log(sc, ELINK_LOG_ID_PHY_UNINITIALIZED, 0); // "Warning: PHY was not initialized," - // " Port %d", + elink_cb_event_log(sc, ELINK_LOG_ID_PHY_UNINITIALIZED, 0); + /* "Warning: PHY was not initialized," + * " Port %d", + */ return rc; } -elink_status_t elink_common_init_phy(struct bnx2x_softc * sc, - uint32_t shmem_base_path[], - uint32_t shmem2_base_path[], - uint32_t chip_id, - __rte_unused uint8_t one_port_enabled) +elink_status_t elink_common_init_phy(struct bnx2x_softc *sc, + uint32_t shmem_base_path[], + uint32_t shmem2_base_path[], uint32_t chip_id, + __rte_unused uint8_t one_port_enabled) { elink_status_t rc = ELINK_STATUS_OK; uint32_t phy_ver, val; uint8_t phy_index = 0; uint32_t ext_phy_type, ext_phy_config; +#if defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA) + if (CHIP_REV_IS_EMUL(sc) || CHIP_REV_IS_FPGA(sc)) + return ELINK_STATUS_OK; +#endif - elink_set_mdio_clk(sc, GRCBASE_EMAC0); - elink_set_mdio_clk(sc, GRCBASE_EMAC1); - PMD_DRV_LOG(DEBUG, "Begin common phy init"); + elink_set_mdio_clk(sc, chip_id, GRCBASE_EMAC0); + elink_set_mdio_clk(sc, chip_id, GRCBASE_EMAC1); + ELINK_DEBUG_P0(sc, "Begin common phy init"); if (CHIP_IS_E3(sc)) { /* Enable EPIO */ val = REG_RD(sc, MISC_REG_GEN_PURP_HWG); @@ -12625,14 +14756,14 @@ elink_status_t elink_common_init_phy(struct bnx2x_softc * sc, offsetof(struct shmem_region, port_mb[PORT_0].ext_phy_fw_version)); if (phy_ver) { - PMD_DRV_LOG(DEBUG, "Not doing common init; phy ver is 0x%x", - phy_ver); + ELINK_DEBUG_P1(sc, "Not doing common init; phy ver is 0x%x", + phy_ver); return ELINK_STATUS_OK; } /* Read the ext_phy_type for arbitrary port(0) */ for (phy_index = ELINK_EXT_PHY1; phy_index < ELINK_MAX_PHYS; - phy_index++) { + phy_index++) { ext_phy_config = elink_get_ext_phy_config(sc, shmem_base_path[0], phy_index, 0); @@ -12655,10 +14786,9 @@ static void elink_check_over_curr(struct elink_params *params, cfg_pin = (REG_RD(sc, params->shmem_base + offsetof(struct shmem_region, - dev_info.port_hw_config[port]. - e3_cmn_pin_cfg1)) & + dev_info.port_hw_config[port].e3_cmn_pin_cfg1)) & PORT_HW_CFG_E3_OVER_CURRENT_MASK) >> - PORT_HW_CFG_E3_OVER_CURRENT_SHIFT; + PORT_HW_CFG_E3_OVER_CURRENT_SHIFT; /* Ignore check if no external input PIN available */ if (elink_get_cfg_pin(sc, cfg_pin, &pin_val) != ELINK_STATUS_OK) @@ -12666,13 +14796,16 @@ static void elink_check_over_curr(struct elink_params *params, if (!pin_val) { if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) { - elink_cb_event_log(sc, ELINK_LOG_ID_OVER_CURRENT, params->port); //"Error: Power fault on Port %d has" - // " been detected and the power to " - // "that SFP+ module has been removed" - // " to prevent failure of the card." - // " Please remove the SFP+ module and" - // " restart the system to clear this" - // " error.", + elink_cb_event_log(sc, ELINK_LOG_ID_OVER_CURRENT, + params->port); + /* "Error: Power fault on Port %d has" + * " been detected and the power to " + * "that SFP+ module has been removed" + * " to prevent failure of the card." + * " Please remove the SFP+ module and" + * " restart the system to clear this" + * " error.", + */ vars->phy_flags |= PHY_OVER_CURRENT_FLAG; elink_warpcore_power_module(params, 0); } @@ -12682,9 +14815,9 @@ static void elink_check_over_curr(struct elink_params *params, /* Returns 0 if no change occurred since last check; 1 otherwise. */ static uint8_t elink_analyze_link_error(struct elink_params *params, - struct elink_vars *vars, - uint32_t status, uint32_t phy_flag, - uint32_t link_flag, uint8_t notify) + struct elink_vars *vars, uint32_t status, + uint32_t phy_flag, uint32_t link_flag, + uint8_t notify) { struct bnx2x_softc *sc = params->sc; /* Compare new value with previous value */ @@ -12697,16 +14830,20 @@ static uint8_t elink_analyze_link_error(struct elink_params *params, /* If values differ */ switch (phy_flag) { case PHY_HALF_OPEN_CONN_FLAG: - PMD_DRV_LOG(DEBUG, "Analyze Remote Fault"); + ELINK_DEBUG_P0(sc, "Analyze Remote Fault"); break; case PHY_SFP_TX_FAULT_FLAG: - PMD_DRV_LOG(DEBUG, "Analyze TX Fault"); + ELINK_DEBUG_P0(sc, "Analyze TX Fault"); break; default: - PMD_DRV_LOG(DEBUG, "Analyze UNKNOWN"); + ELINK_DEBUG_P0(sc, "Analyze UNKNOWN"); } - PMD_DRV_LOG(DEBUG, "Link changed:[%x %x]->%x", vars->link_up, - old_status, status); + ELINK_DEBUG_P3(sc, "Link changed:[%x %x]->%x", vars->link_up, + old_status, status); + + /* Do not touch the link in case physical link down */ + if ((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0) + return 1; /* a. Update shmem->link_status accordingly * b. Update elink_vars->link_up @@ -12749,17 +14886,18 @@ static uint8_t elink_analyze_link_error(struct elink_params *params, } /****************************************************************************** -* Description: -* This function checks for half opened connection change indication. -* When such change occurs, it calls the elink_analyze_link_error -* to check if Remote Fault is set or cleared. Reception of remote fault -* status message in the MAC indicates that the peer's MAC has detected -* a fault, for example, due to break in the TX side of fiber. -* -******************************************************************************/ -static elink_status_t elink_check_half_open_conn(struct elink_params *params, - struct elink_vars *vars, - uint8_t notify) + * Description: + * This function checks for half opened connection change indication. + * When such change occurs, it calls the elink_analyze_link_error + * to check if Remote Fault is set or cleared. Reception of remote fault + * status message in the MAC indicates that the peer's MAC has detected + * a fault, for example, due to break in the TX side of fiber. + * + ******************************************************************************/ +static +elink_status_t elink_check_half_open_conn(struct elink_params *params, + struct elink_vars *vars, + uint8_t notify) { struct bnx2x_softc *sc = params->sc; uint32_t lss_status = 0; @@ -12771,7 +14909,7 @@ static elink_status_t elink_check_half_open_conn(struct elink_params *params, if (CHIP_IS_E3(sc) && (REG_RD(sc, MISC_REG_RESET_REG_2) & - (MISC_REGISTERS_RESET_REG_2_XMAC))) { + (MISC_REGISTERS_RESET_REG_2_XMAC))) { /* Check E3 XMAC */ /* Note that link speed cannot be queried here, since it may be * zero while link is down. In case UMAC is active, LSS will @@ -12796,7 +14934,7 @@ static elink_status_t elink_check_half_open_conn(struct elink_params *params, uint32_t lss_status_reg; uint32_t wb_data[2]; mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM : - NIG_REG_INGRESS_BMAC0_MEM; + NIG_REG_INGRESS_BMAC0_MEM; /* Read BIGMAC_REGISTER_RX_LSS_STATUS */ if (CHIP_IS_E2(sc)) lss_status_reg = BIGMAC2_REGISTER_RX_LSS_STAT; @@ -12812,7 +14950,6 @@ static elink_status_t elink_check_half_open_conn(struct elink_params *params, } return ELINK_STATUS_OK; } - static void elink_sfp_tx_fault_detection(struct elink_phy *phy, struct elink_params *params, struct elink_vars *vars) @@ -12823,15 +14960,12 @@ static void elink_sfp_tx_fault_detection(struct elink_phy *phy, /* Get The SFP+ TX_Fault controlling pin ([eg]pio) */ cfg_pin = (REG_RD(sc, params->shmem_base + offsetof(struct shmem_region, - dev_info. - port_hw_config - [port]. - e3_cmn_pin_cfg)) & + dev_info.port_hw_config[port].e3_cmn_pin_cfg)) & PORT_HW_CFG_E3_TX_FAULT_MASK) >> - PORT_HW_CFG_E3_TX_FAULT_SHIFT; + PORT_HW_CFG_E3_TX_FAULT_SHIFT; if (elink_get_cfg_pin(sc, cfg_pin, &value)) { - PMD_DRV_LOG(DEBUG, "Failed to read pin 0x%02x", cfg_pin); + ELINK_DEBUG_P1(sc, "Failed to read pin 0x%02x", cfg_pin); return; } @@ -12853,24 +14987,25 @@ static void elink_sfp_tx_fault_detection(struct elink_phy *phy, /* If module is unapproved, led should be on regardless */ if (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED)) { - PMD_DRV_LOG(DEBUG, "Change TX_Fault LED: ->%x", - led_mode); + ELINK_DEBUG_P1(sc, "Change TX_Fault LED: ->%x", + led_mode); elink_set_e3_module_fault_led(params, led_mode); } } } - static void elink_kr2_recovery(struct elink_params *params, - struct elink_vars *vars, struct elink_phy *phy) + struct elink_vars *vars, + struct elink_phy *phy) { - PMD_DRV_LOG(DEBUG, "KR2 recovery"); - + struct bnx2x_softc *sc = params->sc; + ELINK_DEBUG_P0(sc, "KR2 recovery"); elink_warpcore_enable_AN_KR2(phy, params, vars); elink_warpcore_restart_AN_KR(phy, params); } static void elink_check_kr2_wa(struct elink_params *params, - struct elink_vars *vars, struct elink_phy *phy) + struct elink_vars *vars, + struct elink_phy *phy) { struct bnx2x_softc *sc = params->sc; uint16_t base_page, next_page, not_kr2_device, lane; @@ -12888,14 +15023,14 @@ static void elink_check_kr2_wa(struct elink_params *params, sigdet = elink_warpcore_get_sigdet(phy, params); if (!sigdet) { - if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) { + if (!(params->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) { elink_kr2_recovery(params, vars, phy); - PMD_DRV_LOG(DEBUG, "No sigdet"); + ELINK_DEBUG_P0(sc, "No sigdet"); } return; } - lane = elink_get_warpcore_lane(params); + lane = elink_get_warpcore_lane(phy, params); CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK, MDIO_AER_BLOCK_AER_REG, lane); elink_cl45_read(sc, phy, MDIO_AN_DEVAD, @@ -12906,9 +15041,9 @@ static void elink_check_kr2_wa(struct elink_params *params, /* CL73 has not begun yet */ if (base_page == 0) { - if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) { + if (!(params->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) { elink_kr2_recovery(params, vars, phy); - PMD_DRV_LOG(DEBUG, "No BP"); + ELINK_DEBUG_P0(sc, "No BP"); } return; } @@ -12922,10 +15057,10 @@ static void elink_check_kr2_wa(struct elink_params *params, ((next_page & 0xe0) == 0x20)))); /* In case KR2 is already disabled, check if we need to re-enable it */ - if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) { + if (!(params->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) { if (!not_kr2_device) { - PMD_DRV_LOG(DEBUG, "BP=0x%x, NP=0x%x", base_page, - next_page); + ELINK_DEBUG_P2(sc, "BP=0x%x, NP=0x%x", base_page, + next_page); elink_kr2_recovery(params, vars, phy); } return; @@ -12933,7 +15068,7 @@ static void elink_check_kr2_wa(struct elink_params *params, /* KR2 is enabled, but not KR2 device */ if (not_kr2_device) { /* Disable KR2 on both lanes */ - PMD_DRV_LOG(DEBUG, "BP=0x%x, NP=0x%x", base_page, next_page); + ELINK_DEBUG_P2(sc, "BP=0x%x, NP=0x%x", base_page, next_page); elink_disable_kr2(params, vars, phy); /* Restart AN on leading lane */ elink_warpcore_restart_AN_KR(phy, params); @@ -12949,9 +15084,8 @@ void elink_period_func(struct elink_params *params, struct elink_vars *vars) if (params->phy[phy_idx].flags & ELINK_FLAGS_TX_ERROR_CHECK) { elink_set_aer_mmd(params, ¶ms->phy[phy_idx]); if (elink_check_half_open_conn(params, vars, 1) != - ELINK_STATUS_OK) { - PMD_DRV_LOG(DEBUG, "Fault detection failed"); - } + ELINK_STATUS_OK) + ELINK_DEBUG_P0(sc, "Fault detection failed"); break; } } @@ -12959,22 +15093,24 @@ void elink_period_func(struct elink_params *params, struct elink_vars *vars) if (CHIP_IS_E3(sc)) { struct elink_phy *phy = ¶ms->phy[ELINK_INT_PHY]; elink_set_aer_mmd(params, phy); - if ((phy->supported & ELINK_SUPPORTED_20000baseKR2_Full) && - (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) + if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) && + (phy->speed_cap_mask & + PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) || + (phy->req_line_speed == ELINK_SPEED_20000)) elink_check_kr2_wa(params, vars, phy); elink_check_over_curr(params, vars); if (vars->rx_tx_asic_rst) elink_warpcore_config_runtime(phy, params, vars); if ((REG_RD(sc, params->shmem_base + - offsetof(struct shmem_region, - dev_info.port_hw_config[params->port]. - default_cfg)) - & PORT_HW_CFG_NET_SERDES_IF_MASK) == + offsetof(struct shmem_region, dev_info. + port_hw_config[params->port].default_cfg)) + & PORT_HW_CFG_NET_SERDES_IF_MASK) == PORT_HW_CFG_NET_SERDES_IF_SFI) { - if (elink_is_sfp_module_plugged(params)) { + if (elink_is_sfp_module_plugged(phy, params)) { elink_sfp_tx_fault_detection(phy, params, vars); - } else if (vars->link_status & LINK_STATUS_SFP_TX_FAULT) { + } else if (vars->link_status & + LINK_STATUS_SFP_TX_FAULT) { /* Clean trail, interrupt corrects the leds */ vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT; vars->phy_flags &= ~PHY_SFP_TX_FAULT_FLAG; @@ -12986,17 +15122,18 @@ void elink_period_func(struct elink_params *params, struct elink_vars *vars) } uint8_t elink_fan_failure_det_req(struct bnx2x_softc *sc, - uint32_t shmem_base, - uint32_t shmem2_base, uint8_t port) + uint32_t shmem_base, + uint32_t shmem2_base, + uint8_t port) { uint8_t phy_index, fan_failure_det_req = 0; struct elink_phy phy; for (phy_index = ELINK_EXT_PHY1; phy_index < ELINK_MAX_PHYS; - phy_index++) { + phy_index++) { if (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base, port, &phy) != ELINK_STATUS_OK) { - PMD_DRV_LOG(DEBUG, "populate phy failed"); + ELINK_DEBUG_P0(sc, "populate phy failed"); return 0; } fan_failure_det_req |= (phy.flags & @@ -13016,24 +15153,27 @@ void elink_hw_reset_phy(struct elink_params *params) ELINK_NIG_MASK_SERDES0_LINK_STATUS | ELINK_NIG_MASK_MI_INT)); - for (phy_index = ELINK_INT_PHY; phy_index < ELINK_MAX_PHYS; phy_index++) { + for (phy_index = ELINK_INT_PHY; phy_index < ELINK_MAX_PHYS; + phy_index++) { if (params->phy[phy_index].hw_reset) { - params->phy[phy_index].hw_reset(¶ms->phy[phy_index], - params); + params->phy[phy_index].hw_reset( + ¶ms->phy[phy_index], + params); params->phy[phy_index] = phy_null; } } } void elink_init_mod_abs_int(struct bnx2x_softc *sc, struct elink_vars *vars, - __rte_unused uint32_t chip_id, uint32_t shmem_base, - uint32_t shmem2_base, uint8_t port) + uint32_t chip_id, uint32_t shmem_base, + uint32_t shmem2_base, + uint8_t port) { uint8_t gpio_num = 0xff, gpio_port = 0xff, phy_index; uint32_t val; uint32_t offset, aeu_mask, swap_val, swap_override, sync_offset; if (CHIP_IS_E3(sc)) { - if (elink_get_mod_abs_int_cfg(sc, + if (elink_get_mod_abs_int_cfg(sc, chip_id, shmem_base, port, &gpio_num, @@ -13042,11 +15182,11 @@ void elink_init_mod_abs_int(struct bnx2x_softc *sc, struct elink_vars *vars, } else { struct elink_phy phy; for (phy_index = ELINK_EXT_PHY1; phy_index < ELINK_MAX_PHYS; - phy_index++) { + phy_index++) { if (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base, port, &phy) != ELINK_STATUS_OK) { - PMD_DRV_LOG(DEBUG, "populate phy failed"); + ELINK_DEBUG_P0(sc, "populate phy failed"); return; } if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726) { @@ -13069,15 +15209,15 @@ void elink_init_mod_abs_int(struct bnx2x_softc *sc, struct elink_vars *vars, gpio_port ^= (swap_val && swap_override); vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 << - (gpio_num + (gpio_port << 2)); + (gpio_num + (gpio_port << 2)); sync_offset = shmem_base + - offsetof(struct shmem_region, - dev_info.port_hw_config[port].aeu_int_mask); + offsetof(struct shmem_region, + dev_info.port_hw_config[port].aeu_int_mask); REG_WR(sc, sync_offset, vars->aeu_int_mask); - PMD_DRV_LOG(DEBUG, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x", - gpio_num, gpio_port, vars->aeu_int_mask); + ELINK_DEBUG_P3(sc, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x", + gpio_num, gpio_port, vars->aeu_int_mask); if (port == 0) offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0; |