diff options
Diffstat (limited to 'drivers/net/bnxt')
| -rw-r--r-- | drivers/net/bnxt/bnxt.h | 28 | ||||
| -rw-r--r-- | drivers/net/bnxt/bnxt_cpr.c | 1 | ||||
| -rw-r--r-- | drivers/net/bnxt/bnxt_ethdev.c | 343 | ||||
| -rw-r--r-- | drivers/net/bnxt/bnxt_filter.c | 28 | ||||
| -rw-r--r-- | drivers/net/bnxt/bnxt_flow.c | 12 | ||||
| -rw-r--r-- | drivers/net/bnxt/bnxt_hwrm.c | 418 | ||||
| -rw-r--r-- | drivers/net/bnxt/bnxt_hwrm.h | 5 | ||||
| -rw-r--r-- | drivers/net/bnxt/bnxt_rxq.c | 25 | ||||
| -rw-r--r-- | drivers/net/bnxt/bnxt_stats.c | 221 | ||||
| -rw-r--r-- | drivers/net/bnxt/bnxt_txr.c | 5 | ||||
| -rw-r--r-- | drivers/net/bnxt/bnxt_vnic.c | 43 | ||||
| -rw-r--r-- | drivers/net/bnxt/hsi_struct_def_dpdk.h | 5489 |
12 files changed, 2975 insertions, 3643 deletions
diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h index db5c4eb0..f75b0ad3 100644 --- a/drivers/net/bnxt/bnxt.h +++ b/drivers/net/bnxt/bnxt.h @@ -20,7 +20,7 @@ #include "bnxt_cpr.h" -#define BNXT_MAX_MTU 9500 +#define BNXT_MAX_MTU 9574 #define VLAN_TAG_SIZE 4 #define BNXT_VF_RSV_NUM_RSS_CTX 1 #define BNXT_VF_RSV_NUM_L2_CTX 4 @@ -33,6 +33,13 @@ #define BNXT_MAX_RX_RING_DESC 8192 #define BNXT_DB_SIZE 0x80 +/* Chimp Communication Channel */ +#define GRCPF_REG_CHIMP_CHANNEL_OFFSET 0x0 +#define GRCPF_REG_CHIMP_COMM_TRIGGER 0x100 +/* Kong Communication Channel */ +#define GRCPF_REG_KONG_CHANNEL_OFFSET 0xA00 +#define GRCPF_REG_KONG_COMM_TRIGGER 0xB00 + #define BNXT_INT_LAT_TMR_MIN 75 #define BNXT_INT_LAT_TMR_MAX 150 #define BNXT_NUM_CMPL_AGGR_INT 36 @@ -250,6 +257,11 @@ struct bnxt { #define BNXT_FLAG_UPDATE_HASH (1 << 5) #define BNXT_FLAG_PTP_SUPPORTED (1 << 6) #define BNXT_FLAG_MULTI_HOST (1 << 7) +#define BNXT_FLAG_EXT_RX_PORT_STATS (1 << 8) +#define BNXT_FLAG_EXT_TX_PORT_STATS (1 << 9) +#define BNXT_FLAG_KONG_MB_EN (1 << 10) +#define BNXT_FLAG_TRUSTED_VF_EN (1 << 11) +#define BNXT_FLAG_DFLT_VNIC_SET (1 << 12) #define BNXT_FLAG_NEW_RM (1 << 30) #define BNXT_FLAG_INIT_DONE (1 << 31) #define BNXT_PF(bp) (!((bp)->flags & BNXT_FLAG_VF)) @@ -257,6 +269,9 @@ struct bnxt { #define BNXT_NPAR(bp) ((bp)->port_partition_type) #define BNXT_MH(bp) ((bp)->flags & BNXT_FLAG_MULTI_HOST) #define BNXT_SINGLE_PF(bp) (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp)) +#define BNXT_USE_CHIMP_MB 0 //For non-CFA commands, everything uses Chimp. +#define BNXT_USE_KONG(bp) ((bp)->flags & BNXT_FLAG_KONG_MB_EN) +#define BNXT_VF_IS_TRUSTED(bp) ((bp)->flags & BNXT_FLAG_TRUSTED_VF_EN) unsigned int rx_nr_rings; unsigned int rx_cp_nr_rings; @@ -264,6 +279,9 @@ struct bnxt { const void *rx_mem_zone; struct rx_port_stats *hw_rx_port_stats; rte_iova_t hw_rx_port_stats_map; + struct rx_port_stats_ext *hw_rx_port_stats_ext; + rte_iova_t hw_rx_port_stats_ext_map; + uint16_t fw_rx_port_stats_ext_size; unsigned int tx_nr_rings; unsigned int tx_cp_nr_rings; @@ -271,6 +289,9 @@ struct bnxt { const void *tx_mem_zone; struct tx_port_stats *hw_tx_port_stats; rte_iova_t hw_tx_port_stats_map; + struct tx_port_stats_ext *hw_tx_port_stats_ext; + rte_iova_t hw_tx_port_stats_ext_map; + uint16_t fw_tx_port_stats_ext_size; /* Default completion ring */ struct bnxt_cp_ring_info *def_cp_ring; @@ -285,16 +306,13 @@ struct bnxt { struct bnxt_filter_info *filter_info; STAILQ_HEAD(, bnxt_filter_info) free_filter_list; - /* VNIC pointer for flow filter (VMDq) pools */ -#define MAX_FF_POOLS 256 - STAILQ_HEAD(, bnxt_vnic_info) ff_pool[MAX_FF_POOLS]; - struct bnxt_irq *irq_tbl; #define MAX_NUM_MAC_ADDR 32 uint8_t mac_addr[ETHER_ADDR_LEN]; uint16_t hwrm_cmd_seq; + uint16_t kong_cmd_seq; void *hwrm_cmd_resp_addr; rte_iova_t hwrm_cmd_resp_dma_addr; void *hwrm_short_cmd_req_addr; diff --git a/drivers/net/bnxt/bnxt_cpr.c b/drivers/net/bnxt/bnxt_cpr.c index ff20b6fd..0fd6e51e 100644 --- a/drivers/net/bnxt/bnxt_cpr.c +++ b/drivers/net/bnxt/bnxt_cpr.c @@ -35,6 +35,7 @@ void bnxt_handle_async_event(struct bnxt *bp, break; case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE: PMD_DRV_LOG(INFO, "Async event: VF config changed\n"); + bnxt_hwrm_func_qcfg(bp); break; case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED: PMD_DRV_LOG(INFO, "Port conn async event\n"); diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c index cc7e4391..801c6ffa 100644 --- a/drivers/net/bnxt/bnxt_ethdev.c +++ b/drivers/net/bnxt/bnxt_ethdev.c @@ -149,7 +149,6 @@ static const struct rte_pci_id bnxt_pci_id_map[] = { DEV_RX_OFFLOAD_TCP_CKSUM | \ DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \ DEV_RX_OFFLOAD_JUMBO_FRAME | \ - DEV_RX_OFFLOAD_CRC_STRIP | \ DEV_RX_OFFLOAD_KEEP_CRC | \ DEV_RX_OFFLOAD_TCP_LRO) @@ -203,7 +202,9 @@ static int bnxt_init_chip(struct bnxt *bp) struct bnxt_rx_queue *rxq; struct rte_eth_link new; struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev); + struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf; struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; + uint64_t rx_offloads = dev_conf->rxmode.offloads; uint32_t intr_vector = 0; uint32_t queue_id, base = BNXT_MISC_VEC_ID; uint32_t vec = BNXT_MISC_VEC_ID; @@ -263,6 +264,9 @@ static int bnxt_init_chip(struct bnxt *bp) } memset(vnic->fw_grp_ids, -1, size); + PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n", + i, vnic, vnic->fw_grp_ids); + rc = bnxt_hwrm_vnic_alloc(bp, vnic); if (rc) { PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n", @@ -281,6 +285,16 @@ static int bnxt_init_chip(struct bnxt *bp) } } + /* + * Firmware sets pf pair in default vnic cfg. If the VLAN strip + * setting is not available at this time, it will not be + * configured correctly in the CFA. + */ + if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP) + vnic->vlan_strip = true; + else + vnic->vlan_strip = false; + rc = bnxt_hwrm_vnic_cfg(bp, vnic); if (rc) { PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n", @@ -299,6 +313,10 @@ static int bnxt_init_chip(struct bnxt *bp) for (j = 0; j < bp->rx_nr_rings; j++) { rxq = bp->eth_dev->data->rx_queues[j]; + PMD_DRV_LOG(DEBUG, + "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n", + j, rxq->vnic, rxq->vnic->fw_grp_ids); + if (rxq->rx_deferred_start) rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID; } @@ -445,7 +463,7 @@ static void bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev, /* Fast path specifics */ dev_info->min_rx_bufsize = 1; dev_info->max_rx_pktlen = BNXT_MAX_MTU + ETHER_HDR_LEN + ETHER_CRC_LEN - + VLAN_TAG_SIZE; + + VLAN_TAG_SIZE * 2; dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT; if (bp->flags & BNXT_FLAG_PTP_SUPPORTED) @@ -694,7 +712,6 @@ static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev) if (bp->dev_stopped == 0) bnxt_dev_stop_op(eth_dev); - bnxt_free_mem(bp); if (eth_dev->data->mac_addrs != NULL) { rte_free(eth_dev->data->mac_addrs); eth_dev->data->mac_addrs = NULL; @@ -714,34 +731,30 @@ static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev, uint64_t pool_mask = eth_dev->data->mac_pool_sel[index]; struct bnxt_vnic_info *vnic; struct bnxt_filter_info *filter, *temp_filter; - uint32_t pool = RTE_MIN(MAX_FF_POOLS, ETH_64_POOLS); uint32_t i; /* * Loop through all VNICs from the specified filter flow pools to * remove the corresponding MAC addr filter */ - for (i = 0; i < pool; i++) { + for (i = 0; i < bp->nr_vnics; i++) { if (!(pool_mask & (1ULL << i))) continue; - STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) { - filter = STAILQ_FIRST(&vnic->filter); - while (filter) { - temp_filter = STAILQ_NEXT(filter, next); - if (filter->mac_index == index) { - STAILQ_REMOVE(&vnic->filter, filter, - bnxt_filter_info, next); - bnxt_hwrm_clear_l2_filter(bp, filter); - filter->mac_index = INVALID_MAC_INDEX; - memset(&filter->l2_addr, 0, - ETHER_ADDR_LEN); - STAILQ_INSERT_TAIL( - &bp->free_filter_list, - filter, next); - } - filter = temp_filter; + vnic = &bp->vnic_info[i]; + filter = STAILQ_FIRST(&vnic->filter); + while (filter) { + temp_filter = STAILQ_NEXT(filter, next); + if (filter->mac_index == index) { + STAILQ_REMOVE(&vnic->filter, filter, + bnxt_filter_info, next); + bnxt_hwrm_clear_l2_filter(bp, filter); + filter->mac_index = INVALID_MAC_INDEX; + memset(&filter->l2_addr, 0, ETHER_ADDR_LEN); + STAILQ_INSERT_TAIL(&bp->free_filter_list, + filter, next); } + filter = temp_filter; } } } @@ -751,10 +764,10 @@ static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev, uint32_t index, uint32_t pool) { struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; - struct bnxt_vnic_info *vnic = STAILQ_FIRST(&bp->ff_pool[pool]); + struct bnxt_vnic_info *vnic = &bp->vnic_info[pool]; struct bnxt_filter_info *filter; - if (BNXT_VF(bp)) { + if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) { PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n"); return -ENOTSUP; } @@ -898,12 +911,10 @@ static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev, return -EINVAL; } /* Update the RSS VNIC(s) */ - for (i = 0; i < MAX_FF_POOLS; i++) { - STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) { - memcpy(vnic->rss_table, reta_conf, reta_size); - - bnxt_hwrm_vnic_rss_cfg(bp, vnic); - } + for (i = 0; i < bp->max_vnics; i++) { + vnic = &bp->vnic_info[i]; + memcpy(vnic->rss_table, reta_conf, reta_size); + bnxt_hwrm_vnic_rss_cfg(bp, vnic); } return 0; } @@ -947,7 +958,7 @@ static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev, struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf; struct bnxt_vnic_info *vnic; uint16_t hash_type = 0; - int i; + unsigned int i; /* * If RSS enablement were different than dev_configure, @@ -978,21 +989,20 @@ static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev, hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6; /* Update the RSS VNIC(s) */ - for (i = 0; i < MAX_FF_POOLS; i++) { - STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) { - vnic->hash_type = hash_type; - - /* - * Use the supplied key if the key length is - * acceptable and the rss_key is not NULL - */ - if (rss_conf->rss_key && - rss_conf->rss_key_len <= HW_HASH_KEY_SIZE) - memcpy(vnic->rss_hash_key, rss_conf->rss_key, - rss_conf->rss_key_len); - - bnxt_hwrm_vnic_rss_cfg(bp, vnic); - } + for (i = 0; i < bp->nr_vnics; i++) { + vnic = &bp->vnic_info[i]; + vnic->hash_type = hash_type; + + /* + * Use the supplied key if the key length is + * acceptable and the rss_key is not NULL + */ + if (rss_conf->rss_key && + rss_conf->rss_key_len <= HW_HASH_KEY_SIZE) + memcpy(vnic->rss_hash_key, rss_conf->rss_key, + rss_conf->rss_key_len); + + bnxt_hwrm_vnic_rss_cfg(bp, vnic); } return 0; } @@ -1269,53 +1279,51 @@ static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id) * else * VLAN filter doesn't exist, just skip and continue */ - STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) { - filter = STAILQ_FIRST(&vnic->filter); - while (filter) { - temp_filter = STAILQ_NEXT(filter, next); - - if (filter->enables & chk && - filter->l2_ovlan == vlan_id) { - /* Must delete the filter */ - STAILQ_REMOVE(&vnic->filter, filter, - bnxt_filter_info, next); - bnxt_hwrm_clear_l2_filter(bp, filter); - STAILQ_INSERT_TAIL( - &bp->free_filter_list, - filter, next); - - /* - * Need to examine to see if the MAC - * filter already existed or not before - * allocating a new one - */ - - new_filter = bnxt_alloc_filter(bp); - if (!new_filter) { - PMD_DRV_LOG(ERR, + vnic = &bp->vnic_info[i]; + filter = STAILQ_FIRST(&vnic->filter); + while (filter) { + temp_filter = STAILQ_NEXT(filter, next); + + if (filter->enables & chk && + filter->l2_ovlan == vlan_id) { + /* Must delete the filter */ + STAILQ_REMOVE(&vnic->filter, filter, + bnxt_filter_info, next); + bnxt_hwrm_clear_l2_filter(bp, filter); + STAILQ_INSERT_TAIL(&bp->free_filter_list, + filter, next); + + /* + * Need to examine to see if the MAC + * filter already existed or not before + * allocating a new one + */ + + new_filter = bnxt_alloc_filter(bp); + if (!new_filter) { + PMD_DRV_LOG(ERR, "MAC/VLAN filter alloc failed\n"); - rc = -ENOMEM; - goto exit; - } - STAILQ_INSERT_TAIL(&vnic->filter, - new_filter, next); - /* Inherit MAC from previous filter */ - new_filter->mac_index = - filter->mac_index; - memcpy(new_filter->l2_addr, - filter->l2_addr, ETHER_ADDR_LEN); - /* MAC only filter */ - rc = bnxt_hwrm_set_l2_filter(bp, - vnic->fw_vnic_id, - new_filter); - if (rc) - goto exit; - PMD_DRV_LOG(INFO, - "Del Vlan filter for %d\n", - vlan_id); + rc = -ENOMEM; + goto exit; } - filter = temp_filter; + STAILQ_INSERT_TAIL(&vnic->filter, + new_filter, next); + /* Inherit MAC from previous filter */ + new_filter->mac_index = + filter->mac_index; + memcpy(new_filter->l2_addr, filter->l2_addr, + ETHER_ADDR_LEN); + /* MAC only filter */ + rc = bnxt_hwrm_set_l2_filter(bp, + vnic->fw_vnic_id, + new_filter); + if (rc) + goto exit; + PMD_DRV_LOG(INFO, + "Del Vlan filter for %d\n", + vlan_id); } + filter = temp_filter; } } exit: @@ -1345,51 +1353,48 @@ static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id) * Remove the old MAC only filter * Add a new MAC+VLAN filter */ - STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) { - filter = STAILQ_FIRST(&vnic->filter); - while (filter) { - temp_filter = STAILQ_NEXT(filter, next); - - if (filter->enables & chk) { - if (filter->l2_ovlan == vlan_id) - goto cont; - } else { - /* Must delete the MAC filter */ - STAILQ_REMOVE(&vnic->filter, filter, - bnxt_filter_info, next); - bnxt_hwrm_clear_l2_filter(bp, filter); - filter->l2_ovlan = 0; - STAILQ_INSERT_TAIL( - &bp->free_filter_list, - filter, next); - } - new_filter = bnxt_alloc_filter(bp); - if (!new_filter) { - PMD_DRV_LOG(ERR, + vnic = &bp->vnic_info[i]; + filter = STAILQ_FIRST(&vnic->filter); + while (filter) { + temp_filter = STAILQ_NEXT(filter, next); + + if (filter->enables & chk) { + if (filter->l2_ivlan == vlan_id) + goto cont; + } else { + /* Must delete the MAC filter */ + STAILQ_REMOVE(&vnic->filter, filter, + bnxt_filter_info, next); + bnxt_hwrm_clear_l2_filter(bp, filter); + filter->l2_ovlan = 0; + STAILQ_INSERT_TAIL(&bp->free_filter_list, + filter, next); + } + new_filter = bnxt_alloc_filter(bp); + if (!new_filter) { + PMD_DRV_LOG(ERR, "MAC/VLAN filter alloc failed\n"); - rc = -ENOMEM; - goto exit; - } - STAILQ_INSERT_TAIL(&vnic->filter, new_filter, - next); - /* Inherit MAC from the previous filter */ - new_filter->mac_index = filter->mac_index; - memcpy(new_filter->l2_addr, filter->l2_addr, - ETHER_ADDR_LEN); - /* MAC + VLAN ID filter */ - new_filter->l2_ivlan = vlan_id; - new_filter->l2_ivlan_mask = 0xF000; - new_filter->enables |= en; - rc = bnxt_hwrm_set_l2_filter(bp, - vnic->fw_vnic_id, - new_filter); - if (rc) - goto exit; - PMD_DRV_LOG(INFO, - "Added Vlan filter for %d\n", vlan_id); -cont: - filter = temp_filter; + rc = -ENOMEM; + goto exit; } + STAILQ_INSERT_TAIL(&vnic->filter, new_filter, next); + /* Inherit MAC from the previous filter */ + new_filter->mac_index = filter->mac_index; + memcpy(new_filter->l2_addr, filter->l2_addr, + ETHER_ADDR_LEN); + /* MAC + VLAN ID filter */ + new_filter->l2_ivlan = vlan_id; + new_filter->l2_ivlan_mask = 0xF000; + new_filter->enables |= en; + rc = bnxt_hwrm_set_l2_filter(bp, + vnic->fw_vnic_id, + new_filter); + if (rc) + goto exit; + PMD_DRV_LOG(INFO, + "Added Vlan filter for %d\n", vlan_id); +cont: + filter = temp_filter; } } exit: @@ -1397,7 +1402,7 @@ exit: } static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev, - uint16_t vlan_id, int on) + uint16_t vlan_id, int on) { struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; @@ -1454,7 +1459,7 @@ bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev, struct ether_addr *addr) struct bnxt_filter_info *filter; int rc; - if (BNXT_VF(bp)) + if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) return -EPERM; memcpy(bp->mac_addr, addr, sizeof(bp->mac_addr)); @@ -1571,21 +1576,17 @@ static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu) { struct bnxt *bp = eth_dev->data->dev_private; struct rte_eth_dev_info dev_info; - uint32_t max_dev_mtu; uint32_t rc = 0; uint32_t i; bnxt_dev_info_get_op(eth_dev, &dev_info); - max_dev_mtu = dev_info.max_rx_pktlen - - ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE * 2; - if (new_mtu < ETHER_MIN_MTU || new_mtu > max_dev_mtu) { + if (new_mtu < ETHER_MIN_MTU || new_mtu > BNXT_MAX_MTU) { PMD_DRV_LOG(ERR, "MTU requested must be within (%d, %d)\n", - ETHER_MIN_MTU, max_dev_mtu); + ETHER_MIN_MTU, BNXT_MAX_MTU); return -EINVAL; } - if (new_mtu > ETHER_MTU) { bp->flags |= BNXT_FLAG_JUMBO; bp->eth_dev->data->dev_conf.rxmode.offloads |= @@ -1805,8 +1806,8 @@ bnxt_match_and_validate_ether_filter(struct bnxt *bp, goto exit; } - vnic0 = STAILQ_FIRST(&bp->ff_pool[0]); - vnic = STAILQ_FIRST(&bp->ff_pool[efilter->queue]); + vnic0 = &bp->vnic_info[0]; + vnic = &bp->vnic_info[efilter->queue]; if (vnic == NULL) { PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue); *ret = -EINVAL; @@ -1864,8 +1865,8 @@ bnxt_ethertype_filter(struct rte_eth_dev *dev, return -EINVAL; } - vnic0 = STAILQ_FIRST(&bp->ff_pool[0]); - vnic = STAILQ_FIRST(&bp->ff_pool[efilter->queue]); + vnic0 = &bp->vnic_info[0]; + vnic = &bp->vnic_info[efilter->queue]; switch (filter_op) { case RTE_ETH_FILTER_ADD: @@ -2081,8 +2082,8 @@ bnxt_cfg_ntuple_filter(struct bnxt *bp, if (ret < 0) goto free_filter; - vnic = STAILQ_FIRST(&bp->ff_pool[nfilter->queue]); - vnic0 = STAILQ_FIRST(&bp->ff_pool[0]); + vnic = &bp->vnic_info[nfilter->queue]; + vnic0 = &bp->vnic_info[0]; filter1 = STAILQ_FIRST(&vnic0->filter); if (filter1 == NULL) { ret = -1; @@ -2375,8 +2376,8 @@ bnxt_parse_fdir_filter(struct bnxt *bp, return -EINVAL; } - vnic0 = STAILQ_FIRST(&bp->ff_pool[0]); - vnic = STAILQ_FIRST(&bp->ff_pool[fdir->action.rx_queue]); + vnic0 = &bp->vnic_info[0]; + vnic = &bp->vnic_info[fdir->action.rx_queue]; if (vnic == NULL) { PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue); return -EINVAL; @@ -2497,9 +2498,9 @@ bnxt_fdir_filter(struct rte_eth_dev *dev, filter->filter_type = HWRM_CFA_NTUPLE_FILTER; if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) - vnic = STAILQ_FIRST(&bp->ff_pool[0]); + vnic = &bp->vnic_info[0]; else - vnic = STAILQ_FIRST(&bp->ff_pool[fdir->action.rx_queue]); + vnic = &bp->vnic_info[fdir->action.rx_queue]; match = bnxt_match_fdir(bp, filter, &mvnic); if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) { @@ -3226,7 +3227,9 @@ skip_init: mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0; mz = rte_memzone_lookup(mz_name); total_alloc_len = RTE_CACHE_LINE_ROUNDUP( - sizeof(struct rx_port_stats) + 512); + sizeof(struct rx_port_stats) + + sizeof(struct rx_port_stats_ext) + + 512); if (!mz) { mz = rte_memzone_reserve(mz_name, total_alloc_len, SOCKET_ID_ANY, @@ -3262,7 +3265,9 @@ skip_init: mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0; mz = rte_memzone_lookup(mz_name); total_alloc_len = RTE_CACHE_LINE_ROUNDUP( - sizeof(struct tx_port_stats) + 512); + sizeof(struct tx_port_stats) + + sizeof(struct tx_port_stats_ext) + + 512); if (!mz) { mz = rte_memzone_reserve(mz_name, total_alloc_len, @@ -3293,8 +3298,30 @@ skip_init: bp->hw_tx_port_stats_map = mz_phys_addr; bp->flags |= BNXT_FLAG_PORT_STATS; + + /* Display extended statistics if FW supports it */ + if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 || + bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0) + goto skip_ext_stats; + + bp->hw_rx_port_stats_ext = (void *) + (bp->hw_rx_port_stats + sizeof(struct rx_port_stats)); + bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map + + sizeof(struct rx_port_stats); + bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS; + + + if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2) { + bp->hw_tx_port_stats_ext = (void *) + (bp->hw_tx_port_stats + sizeof(struct tx_port_stats)); + bp->hw_tx_port_stats_ext_map = + bp->hw_tx_port_stats_map + + sizeof(struct tx_port_stats); + bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS; + } } +skip_ext_stats: rc = bnxt_alloc_hwrm_resources(bp); if (rc) { PMD_DRV_LOG(ERR, @@ -3474,10 +3501,6 @@ bnxt_dev_uninit(struct rte_eth_dev *eth_dev) bnxt_disable_int(bp); bnxt_free_int(bp); bnxt_free_mem(bp); - if (eth_dev->data->mac_addrs != NULL) { - rte_free(eth_dev->data->mac_addrs); - eth_dev->data->mac_addrs = NULL; - } if (bp->grp_info != NULL) { rte_free(bp->grp_info); bp->grp_info = NULL; @@ -3515,7 +3538,11 @@ static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, static int bnxt_pci_remove(struct rte_pci_device *pci_dev) { - return rte_eth_dev_pci_generic_remove(pci_dev, bnxt_dev_uninit); + if (rte_eal_process_type() == RTE_PROC_PRIMARY) + return rte_eth_dev_pci_generic_remove(pci_dev, + bnxt_dev_uninit); + else + return rte_eth_dev_pci_generic_remove(pci_dev, NULL); } static struct rte_pci_driver bnxt_rte_pmd = { @@ -3542,7 +3569,7 @@ bool is_bnxt_supported(struct rte_eth_dev *dev) RTE_INIT(bnxt_init_log) { - bnxt_logtype_driver = rte_log_register("pmd.bnxt.driver"); + bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver"); if (bnxt_logtype_driver >= 0) rte_log_set_level(bnxt_logtype_driver, RTE_LOG_INFO); } diff --git a/drivers/net/bnxt/bnxt_filter.c b/drivers/net/bnxt/bnxt_filter.c index 1038941e..f43fe0db 100644 --- a/drivers/net/bnxt/bnxt_filter.c +++ b/drivers/net/bnxt/bnxt_filter.c @@ -80,21 +80,21 @@ void bnxt_free_all_filters(struct bnxt *bp) { struct bnxt_vnic_info *vnic; struct bnxt_filter_info *filter, *temp_filter; - int i; - - for (i = 0; i < MAX_FF_POOLS; i++) { - STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) { - filter = STAILQ_FIRST(&vnic->filter); - while (filter) { - temp_filter = STAILQ_NEXT(filter, next); - STAILQ_REMOVE(&vnic->filter, filter, - bnxt_filter_info, next); - STAILQ_INSERT_TAIL(&bp->free_filter_list, - filter, next); - filter = temp_filter; - } - STAILQ_INIT(&vnic->filter); + unsigned int i; + +// for (i = 0; i < MAX_FF_POOLS; i++) { + for (i = 0; i < bp->nr_vnics; i++) { + vnic = &bp->vnic_info[i]; + filter = STAILQ_FIRST(&vnic->filter); + while (filter) { + temp_filter = STAILQ_NEXT(filter, next); + STAILQ_REMOVE(&vnic->filter, filter, + bnxt_filter_info, next); + STAILQ_INSERT_TAIL(&bp->free_filter_list, + filter, next); + filter = temp_filter; } + STAILQ_INIT(&vnic->filter); } for (i = 0; i < bp->pf.max_vfs; i++) { diff --git a/drivers/net/bnxt/bnxt_flow.c b/drivers/net/bnxt/bnxt_flow.c index ac765674..1afe6740 100644 --- a/drivers/net/bnxt/bnxt_flow.c +++ b/drivers/net/bnxt/bnxt_flow.c @@ -678,7 +678,7 @@ bnxt_get_l2_filter(struct bnxt *bp, struct bnxt_filter_info *nf, struct bnxt_vnic_info *vnic0; int rc; - vnic0 = STAILQ_FIRST(&bp->ff_pool[0]); + vnic0 = &bp->vnic_info[0]; f0 = STAILQ_FIRST(&vnic0->filter); /* This flow has same DST MAC as the port/l2 filter. */ @@ -763,8 +763,8 @@ bnxt_validate_and_parse_flow(struct rte_eth_dev *dev, } PMD_DRV_LOG(DEBUG, "Queue index %d\n", act_q->index); - vnic0 = STAILQ_FIRST(&bp->ff_pool[0]); - vnic = STAILQ_FIRST(&bp->ff_pool[act_q->index]); + vnic0 = &bp->vnic_info[0]; + vnic = &bp->vnic_info[act_q->index]; if (vnic == NULL) { rte_flow_error_set(error, EINVAL, @@ -786,7 +786,7 @@ bnxt_validate_and_parse_flow(struct rte_eth_dev *dev, PMD_DRV_LOG(DEBUG, "VNIC found\n"); break; case RTE_FLOW_ACTION_TYPE_DROP: - vnic0 = STAILQ_FIRST(&bp->ff_pool[0]); + vnic0 = &bp->vnic_info[0]; filter1 = bnxt_get_l2_filter(bp, filter, vnic0); if (filter1 == NULL) { rc = -ENOSPC; @@ -802,7 +802,7 @@ bnxt_validate_and_parse_flow(struct rte_eth_dev *dev, HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP; break; case RTE_FLOW_ACTION_TYPE_COUNT: - vnic0 = STAILQ_FIRST(&bp->ff_pool[0]); + vnic0 = &bp->vnic_info[0]; filter1 = bnxt_get_l2_filter(bp, filter, vnic0); if (filter1 == NULL) { rc = -ENOSPC; @@ -854,7 +854,7 @@ bnxt_validate_and_parse_flow(struct rte_eth_dev *dev, filter->mirror_vnic_id = dflt_vnic; filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_MIRROR_VNIC_ID; - vnic0 = STAILQ_FIRST(&bp->ff_pool[0]); + vnic0 = &bp->vnic_info[0]; filter1 = bnxt_get_l2_filter(bp, filter, vnic0); if (filter1 == NULL) { rc = -ENOSPC; diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c index c682488a..99997605 100644 --- a/drivers/net/bnxt/bnxt_hwrm.c +++ b/drivers/net/bnxt/bnxt_hwrm.c @@ -26,7 +26,7 @@ #include <rte_io.h> -#define HWRM_CMD_TIMEOUT 10000 +#define HWRM_CMD_TIMEOUT 6000000 #define HWRM_SPEC_CODE_1_8_3 0x10803 #define HWRM_VERSION_1_9_1 0x10901 @@ -70,7 +70,7 @@ static int page_roundup(size_t size) */ static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg, - uint32_t msg_len) + uint32_t msg_len, bool use_kong_mb) { unsigned int i; struct input *req = msg; @@ -80,6 +80,10 @@ static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg, uint8_t *valid; uint16_t max_req_len = bp->max_req_len; struct hwrm_short_input short_input = { 0 }; + uint16_t bar_offset = use_kong_mb ? + GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET; + uint16_t mb_trigger_offset = use_kong_mb ? + GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER; if (bp->flags & BNXT_FLAG_SHORT_CMD) { void *short_cmd_req = bp->hwrm_short_cmd_req_addr; @@ -105,19 +109,19 @@ static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg, /* Write request msg to hwrm channel */ for (i = 0; i < msg_len; i += 4) { - bar = (uint8_t *)bp->bar0 + i; + bar = (uint8_t *)bp->bar0 + bar_offset + i; rte_write32(*data, bar); data++; } /* Zero the rest of the request space */ for (; i < max_req_len; i += 4) { - bar = (uint8_t *)bp->bar0 + i; + bar = (uint8_t *)bp->bar0 + bar_offset + i; rte_write32(0, bar); } /* Ring channel doorbell */ - bar = (uint8_t *)bp->bar0 + 0x100; + bar = (uint8_t *)bp->bar0 + mb_trigger_offset; rte_write32(1, bar); /* Poll for the valid bit */ @@ -131,7 +135,7 @@ static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg, if (*valid == HWRM_RESP_VALID_KEY) break; } - rte_delay_us(600); + rte_delay_us(1); } if (i >= HWRM_CMD_TIMEOUT) { @@ -156,12 +160,13 @@ err_ret: * * HWRM_UNLOCK() must be called after all response processing is completed. */ -#define HWRM_PREP(req, type) do { \ +#define HWRM_PREP(req, type, kong) do { \ rte_spinlock_lock(&bp->hwrm_lock); \ memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \ req.req_type = rte_cpu_to_le_16(HWRM_##type); \ req.cmpl_ring = rte_cpu_to_le_16(-1); \ - req.seq_id = rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \ + req.seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\ + rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \ req.target_id = rte_cpu_to_le_16(0xffff); \ req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \ } while (0) @@ -220,11 +225,11 @@ int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic) struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 }; struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr; - HWRM_PREP(req, CFA_L2_SET_RX_MASK); + HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB); req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id); req.mask = 0; - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); HWRM_CHECK_RESULT(); HWRM_UNLOCK(); @@ -245,7 +250,7 @@ int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, if (vnic->fw_vnic_id == INVALID_HW_RING_ID) return rc; - HWRM_PREP(req, CFA_L2_SET_RX_MASK); + HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB); req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id); /* FIXME add multicast flag, when multicast adding options is supported @@ -275,7 +280,7 @@ int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, } req.mask = rte_cpu_to_le_32(mask); - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); HWRM_CHECK_RESULT(); HWRM_UNLOCK(); @@ -307,14 +312,14 @@ int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid, return 0; } } - HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG); + HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB); req.fid = rte_cpu_to_le_16(fid); req.vlan_tag_mask_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table)); req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count); - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); HWRM_CHECK_RESULT(); HWRM_UNLOCK(); @@ -332,11 +337,11 @@ int bnxt_hwrm_clear_l2_filter(struct bnxt *bp, if (filter->fw_l2_filter_id == UINT64_MAX) return 0; - HWRM_PREP(req, CFA_L2_FILTER_FREE); + HWRM_PREP(req, CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB); req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id); - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); HWRM_CHECK_RESULT(); HWRM_UNLOCK(); @@ -375,9 +380,11 @@ int bnxt_hwrm_set_l2_filter(struct bnxt *bp, if (filter->fw_l2_filter_id != UINT64_MAX) bnxt_hwrm_clear_l2_filter(bp, filter); - HWRM_PREP(req, CFA_L2_FILTER_ALLOC); + HWRM_PREP(req, CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB); req.flags = rte_cpu_to_le_32(filter->flags); + req.flags |= + rte_cpu_to_le_32(HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST); enables = filter->enables | HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID; @@ -410,7 +417,7 @@ int bnxt_hwrm_set_l2_filter(struct bnxt *bp, req.enables = rte_cpu_to_le_32(enables); - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); HWRM_CHECK_RESULT(); @@ -430,7 +437,7 @@ int bnxt_hwrm_ptp_cfg(struct bnxt *bp) if (!ptp) return 0; - HWRM_PREP(req, PORT_MAC_CFG); + HWRM_PREP(req, PORT_MAC_CFG, BNXT_USE_CHIMP_MB); if (ptp->rx_filter) flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE; @@ -447,7 +454,7 @@ int bnxt_hwrm_ptp_cfg(struct bnxt *bp) (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE); req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl); - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); HWRM_UNLOCK(); return rc; @@ -464,11 +471,11 @@ static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp) if (ptp) return 0; - HWRM_PREP(req, PORT_MAC_PTP_QCFG); + HWRM_PREP(req, PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB); req.port_id = rte_cpu_to_le_16(bp->pf.port_id); - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); HWRM_CHECK_RESULT(); @@ -513,11 +520,11 @@ static int __bnxt_hwrm_func_qcaps(struct bnxt *bp) uint32_t flags; int i; - HWRM_PREP(req, FUNC_QCAPS); + HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB); req.fid = rte_cpu_to_le_16(0xffff); - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); HWRM_CHECK_RESULT(); @@ -615,11 +622,11 @@ int bnxt_hwrm_func_reset(struct bnxt *bp) struct hwrm_func_reset_input req = {.req_type = 0 }; struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr; - HWRM_PREP(req, FUNC_RESET); + HWRM_PREP(req, FUNC_RESET, BNXT_USE_CHIMP_MB); req.enables = rte_cpu_to_le_32(0); - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); HWRM_CHECK_RESULT(); HWRM_UNLOCK(); @@ -636,7 +643,7 @@ int bnxt_hwrm_func_driver_register(struct bnxt *bp) if (bp->flags & BNXT_FLAG_REGISTERED) return 0; - HWRM_PREP(req, FUNC_DRV_RGTR); + HWRM_PREP(req, FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB); req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER | HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD); req.ver_maj = RTE_VER_YEAR; @@ -668,7 +675,7 @@ int bnxt_hwrm_func_driver_register(struct bnxt *bp) rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD | ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE); - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); HWRM_CHECK_RESULT(); HWRM_UNLOCK(); @@ -694,7 +701,7 @@ int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test) struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr; struct hwrm_func_vf_cfg_input req = {0}; - HWRM_PREP(req, FUNC_VF_CFG); + HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB); req.enables = rte_cpu_to_le_32 (HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS | @@ -733,7 +740,7 @@ int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test) req.flags = rte_cpu_to_le_32(flags); - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); if (test) HWRM_CHECK_RESULT_SILENT(); @@ -750,10 +757,10 @@ int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp) struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr; struct hwrm_func_resource_qcaps_input req = {0}; - HWRM_PREP(req, FUNC_RESOURCE_QCAPS); + HWRM_PREP(req, FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB); req.fid = rte_cpu_to_le_16(0xffff); - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); HWRM_CHECK_RESULT(); @@ -782,20 +789,19 @@ int bnxt_hwrm_ver_get(struct bnxt *bp) int rc = 0; struct hwrm_ver_get_input req = {.req_type = 0 }; struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr; - uint32_t my_version; uint32_t fw_version; uint16_t max_resp_len; char type[RTE_MEMZONE_NAMESIZE]; uint32_t dev_caps_cfg; bp->max_req_len = HWRM_MAX_REQ_LEN; - HWRM_PREP(req, VER_GET); + HWRM_PREP(req, VER_GET, BNXT_USE_CHIMP_MB); req.hwrm_intf_maj = HWRM_VERSION_MAJOR; req.hwrm_intf_min = HWRM_VERSION_MINOR; req.hwrm_intf_upd = HWRM_VERSION_UPDATE; - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); HWRM_CHECK_RESULT(); @@ -810,10 +816,6 @@ int bnxt_hwrm_ver_get(struct bnxt *bp) PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n", HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE); - my_version = HWRM_VERSION_MAJOR << 16; - my_version |= HWRM_VERSION_MINOR << 8; - my_version |= HWRM_VERSION_UPDATE; - fw_version = resp->hwrm_intf_maj_8b << 16; fw_version |= resp->hwrm_intf_min_8b << 8; fw_version |= resp->hwrm_intf_upd_8b; @@ -825,21 +827,6 @@ int bnxt_hwrm_ver_get(struct bnxt *bp) goto error; } - if (my_version != fw_version) { - PMD_DRV_LOG(INFO, "BNXT Driver/HWRM API mismatch.\n"); - if (my_version < fw_version) { - PMD_DRV_LOG(INFO, - "Firmware API version is newer than driver.\n"); - PMD_DRV_LOG(INFO, - "The driver may be missing features.\n"); - } else { - PMD_DRV_LOG(INFO, - "Firmware API version is older than driver.\n"); - PMD_DRV_LOG(INFO, - "Not all driver features may be functional.\n"); - } - } - if (bp->max_req_len > resp->max_req_win_len) { PMD_DRV_LOG(ERR, "Unsupported request length\n"); rc = -EINVAL; @@ -899,6 +886,14 @@ int bnxt_hwrm_ver_get(struct bnxt *bp) bp->flags |= BNXT_FLAG_SHORT_CMD; } + if (dev_caps_cfg & + HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) { + bp->flags |= BNXT_FLAG_KONG_MB_EN; + PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n"); + } + if (dev_caps_cfg & + HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED) + PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n"); error: HWRM_UNLOCK(); @@ -914,10 +909,10 @@ int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags) if (!(bp->flags & BNXT_FLAG_REGISTERED)) return 0; - HWRM_PREP(req, FUNC_DRV_UNRGTR); + HWRM_PREP(req, FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB); req.flags = flags; - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); HWRM_CHECK_RESULT(); HWRM_UNLOCK(); @@ -934,7 +929,7 @@ static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf) struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr; uint32_t enables = 0; - HWRM_PREP(req, PORT_PHY_CFG); + HWRM_PREP(req, PORT_PHY_CFG, BNXT_USE_CHIMP_MB); if (conf->link_up) { /* Setting Fixed Speed. But AutoNeg is ON, So disable it */ @@ -983,7 +978,7 @@ static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf) PMD_DRV_LOG(INFO, "Force Link Down\n"); } - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); HWRM_CHECK_RESULT(); HWRM_UNLOCK(); @@ -998,9 +993,9 @@ static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp, struct hwrm_port_phy_qcfg_input req = {0}; struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr; - HWRM_PREP(req, PORT_PHY_QCFG); + HWRM_PREP(req, PORT_PHY_QCFG, BNXT_USE_CHIMP_MB); - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); HWRM_CHECK_RESULT(); @@ -1046,14 +1041,14 @@ int bnxt_hwrm_queue_qportcfg(struct bnxt *bp) struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr; int i; - HWRM_PREP(req, QUEUE_QPORTCFG); + HWRM_PREP(req, QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB); req.flags = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX; /* HWRM Version >= 1.9.1 */ if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1) req.drv_qmap_cap = HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED; - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); HWRM_CHECK_RESULT(); @@ -1099,7 +1094,7 @@ int bnxt_hwrm_ring_alloc(struct bnxt *bp, struct hwrm_ring_alloc_input req = {.req_type = 0 }; struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr; - HWRM_PREP(req, RING_ALLOC); + HWRM_PREP(req, RING_ALLOC, BNXT_USE_CHIMP_MB); req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma); req.fbo = rte_cpu_to_le_32(0); @@ -1135,7 +1130,7 @@ int bnxt_hwrm_ring_alloc(struct bnxt *bp, } req.enables = rte_cpu_to_le_32(enables); - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); if (rc || resp->error_code) { if (rc == 0 && resp->error_code) @@ -1175,12 +1170,12 @@ int bnxt_hwrm_ring_free(struct bnxt *bp, struct hwrm_ring_free_input req = {.req_type = 0 }; struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr; - HWRM_PREP(req, RING_FREE); + HWRM_PREP(req, RING_FREE, BNXT_USE_CHIMP_MB); req.ring_type = ring_type; req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id); - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); if (rc || resp->error_code) { if (rc == 0 && resp->error_code) @@ -1215,14 +1210,14 @@ int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx) struct hwrm_ring_grp_alloc_input req = {.req_type = 0 }; struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr; - HWRM_PREP(req, RING_GRP_ALLOC); + HWRM_PREP(req, RING_GRP_ALLOC, BNXT_USE_CHIMP_MB); req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id); req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id); req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id); req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx); - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); HWRM_CHECK_RESULT(); @@ -1240,11 +1235,11 @@ int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx) struct hwrm_ring_grp_free_input req = {.req_type = 0 }; struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr; - HWRM_PREP(req, RING_GRP_FREE); + HWRM_PREP(req, RING_GRP_FREE, BNXT_USE_CHIMP_MB); req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id); - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); HWRM_CHECK_RESULT(); HWRM_UNLOCK(); @@ -1262,11 +1257,11 @@ int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr) if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE) return rc; - HWRM_PREP(req, STAT_CTX_CLR_STATS); + HWRM_PREP(req, STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB); req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id); - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); HWRM_CHECK_RESULT(); HWRM_UNLOCK(); @@ -1281,14 +1276,14 @@ int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 }; struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr; - HWRM_PREP(req, STAT_CTX_ALLOC); + HWRM_PREP(req, STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB); req.update_period_ms = rte_cpu_to_le_32(0); req.stats_dma_addr = rte_cpu_to_le_64(cpr->hw_stats_map); - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); HWRM_CHECK_RESULT(); @@ -1306,11 +1301,11 @@ int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, struct hwrm_stat_ctx_free_input req = {.req_type = 0 }; struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr; - HWRM_PREP(req, STAT_CTX_FREE); + HWRM_PREP(req, STAT_CTX_FREE, BNXT_USE_CHIMP_MB); req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id); - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); HWRM_CHECK_RESULT(); HWRM_UNLOCK(); @@ -1336,12 +1331,12 @@ int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic) vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE; vnic->mru = bp->eth_dev->data->mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE; - HWRM_PREP(req, VNIC_ALLOC); + HWRM_PREP(req, VNIC_ALLOC, BNXT_USE_CHIMP_MB); if (vnic->func_default) req.flags = rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT); - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); HWRM_CHECK_RESULT(); @@ -1359,11 +1354,11 @@ static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp, struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 }; struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr; - HWRM_PREP(req, VNIC_PLCMODES_QCFG); + HWRM_PREP(req, VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB); req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id); - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); HWRM_CHECK_RESULT(); @@ -1387,7 +1382,7 @@ static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp, struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 }; struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr; - HWRM_PREP(req, VNIC_PLCMODES_CFG); + HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB); req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id); req.flags = rte_cpu_to_le_32(pmode->flags); @@ -1400,7 +1395,7 @@ static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp, HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID ); - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); HWRM_CHECK_RESULT(); HWRM_UNLOCK(); @@ -1425,7 +1420,7 @@ int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic) if (rc) return rc; - HWRM_PREP(req, VNIC_CFG); + HWRM_PREP(req, VNIC_CFG, BNXT_USE_CHIMP_MB); /* Only RSS support for now TBD: COS & LB */ req.enables = @@ -1445,9 +1440,12 @@ int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic) req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule); req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule); req.mru = rte_cpu_to_le_16(vnic->mru); - if (vnic->func_default) + /* Configure default VNIC only once. */ + if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) { req.flags |= rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT); + bp->flags |= BNXT_FLAG_DFLT_VNIC_SET; + } if (vnic->vlan_strip) req.flags |= rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE); @@ -1464,7 +1462,7 @@ int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic) req.flags |= rte_cpu_to_le_32( HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE); - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); HWRM_CHECK_RESULT(); HWRM_UNLOCK(); @@ -1485,14 +1483,14 @@ int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic, PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id); return rc; } - HWRM_PREP(req, VNIC_QCFG); + HWRM_PREP(req, VNIC_QCFG, BNXT_USE_CHIMP_MB); req.enables = rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID); req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id); req.vf_id = rte_cpu_to_le_16(fw_vf_id); - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); HWRM_CHECK_RESULT(); @@ -1526,9 +1524,9 @@ int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic) struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr; - HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC); + HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB); - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); HWRM_CHECK_RESULT(); @@ -1550,11 +1548,11 @@ int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic) PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule); return rc; } - HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE); + HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB); req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(vnic->rss_rule); - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); HWRM_CHECK_RESULT(); HWRM_UNLOCK(); @@ -1575,16 +1573,20 @@ int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic) return rc; } - HWRM_PREP(req, VNIC_FREE); + HWRM_PREP(req, VNIC_FREE, BNXT_USE_CHIMP_MB); req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id); - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); HWRM_CHECK_RESULT(); HWRM_UNLOCK(); vnic->fw_vnic_id = INVALID_HW_RING_ID; + /* Configure default VNIC again if necessary. */ + if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) + bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET; + return rc; } @@ -1595,7 +1597,7 @@ int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp, struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 }; struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr; - HWRM_PREP(req, VNIC_RSS_CFG); + HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB); req.hash_type = rte_cpu_to_le_32(vnic->hash_type); req.hash_mode_flags = vnic->hash_mode; @@ -1606,7 +1608,7 @@ int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp, rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr); req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule); - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); HWRM_CHECK_RESULT(); HWRM_UNLOCK(); @@ -1627,7 +1629,7 @@ int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp, return rc; } - HWRM_PREP(req, VNIC_PLCMODES_CFG); + HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB); req.flags = rte_cpu_to_le_32( HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT); @@ -1641,7 +1643,7 @@ int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp, req.jumbo_thresh = rte_cpu_to_le_16(size); req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id); - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); HWRM_CHECK_RESULT(); HWRM_UNLOCK(); @@ -1656,7 +1658,7 @@ int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp, struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 }; struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr; - HWRM_PREP(req, VNIC_TPA_CFG); + HWRM_PREP(req, VNIC_TPA_CFG, BNXT_USE_CHIMP_MB); if (enable) { req.enables = rte_cpu_to_le_32( @@ -1677,7 +1679,7 @@ int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp, } req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id); - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); HWRM_CHECK_RESULT(); HWRM_UNLOCK(); @@ -1697,9 +1699,9 @@ int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr) memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr)); req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid); - HWRM_PREP(req, FUNC_CFG); + HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB); - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); HWRM_CHECK_RESULT(); HWRM_UNLOCK(); @@ -1715,11 +1717,11 @@ int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid, struct hwrm_func_qstats_input req = {.req_type = 0}; struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr; - HWRM_PREP(req, FUNC_QSTATS); + HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB); req.fid = rte_cpu_to_le_16(fid); - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); HWRM_CHECK_RESULT(); @@ -1738,11 +1740,11 @@ int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid, struct hwrm_func_qstats_input req = {.req_type = 0}; struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr; - HWRM_PREP(req, FUNC_QSTATS); + HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB); req.fid = rte_cpu_to_le_16(fid); - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); HWRM_CHECK_RESULT(); @@ -1775,11 +1777,11 @@ int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid) struct hwrm_func_clr_stats_input req = {.req_type = 0}; struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr; - HWRM_PREP(req, FUNC_CLR_STATS); + HWRM_PREP(req, FUNC_CLR_STATS, BNXT_USE_CHIMP_MB); req.fid = rte_cpu_to_le_16(fid); - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); HWRM_CHECK_RESULT(); HWRM_UNLOCK(); @@ -2435,10 +2437,10 @@ int bnxt_hwrm_func_qcfg(struct bnxt *bp) uint16_t flags; int rc = 0; - HWRM_PREP(req, FUNC_QCFG); + HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB); req.fid = rte_cpu_to_le_16(0xffff); - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); HWRM_CHECK_RESULT(); @@ -2448,6 +2450,11 @@ int bnxt_hwrm_func_qcfg(struct bnxt *bp) if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST)) bp->flags |= BNXT_FLAG_MULTI_HOST; + if (BNXT_VF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) { + bp->flags |= BNXT_FLAG_TRUSTED_VF_EN; + PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n"); + } + switch (resp->port_partition_type) { case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0: case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5: @@ -2522,9 +2529,9 @@ static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings) req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps); req.fid = rte_cpu_to_le_16(0xffff); - HWRM_PREP(req, FUNC_CFG); + HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB); - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); HWRM_CHECK_RESULT(); HWRM_UNLOCK(); @@ -2595,9 +2602,9 @@ static void reserve_resources_from_vf(struct bnxt *bp, int rc; /* Get the actual allocated values now */ - HWRM_PREP(req, FUNC_QCAPS); + HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB); req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid); - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); if (rc) { PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc); @@ -2631,9 +2638,9 @@ int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf) int rc; /* Check for zero MAC address */ - HWRM_PREP(req, FUNC_QCFG); + HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB); req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid); - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); if (rc) { PMD_DRV_LOG(ERR, "hwrm_func_qcfg failed rc:%d\n", rc); return -1; @@ -2656,9 +2663,9 @@ static int update_pf_resource_max(struct bnxt *bp) int rc; /* And copy the allocated numbers into the pf struct */ - HWRM_PREP(req, FUNC_QCFG); + HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB); req.fid = rte_cpu_to_le_16(0xffff); - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); HWRM_CHECK_RESULT(); /* Only TX ring value reflects actual allocation? TODO */ @@ -2758,10 +2765,13 @@ int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs) for (i = 0; i < num_vfs; i++) { add_random_mac_if_needed(bp, &req, i); - HWRM_PREP(req, FUNC_CFG); + HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB); req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags); req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid); - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, + &req, + sizeof(req), + BNXT_USE_CHIMP_MB); /* Clear enable flag for next pass */ req.enables &= ~rte_cpu_to_le_32( @@ -2811,13 +2821,13 @@ int bnxt_hwrm_pf_evb_mode(struct bnxt *bp) struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr; int rc; - HWRM_PREP(req, FUNC_CFG); + HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB); req.fid = rte_cpu_to_le_16(0xffff); req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE); req.evb_mode = bp->pf.evb_mode; - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); HWRM_CHECK_RESULT(); HWRM_UNLOCK(); @@ -2831,10 +2841,10 @@ int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port, struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr; int rc = 0; - HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC); + HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB); req.tunnel_type = tunnel_type; req.tunnel_dst_port_val = port; - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); HWRM_CHECK_RESULT(); switch (tunnel_type) { @@ -2862,11 +2872,11 @@ int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port, struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr; int rc = 0; - HWRM_PREP(req, TUNNEL_DST_PORT_FREE); + HWRM_PREP(req, TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB); req.tunnel_type = tunnel_type; req.tunnel_dst_port_id = rte_cpu_to_be_16(port); - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); HWRM_CHECK_RESULT(); HWRM_UNLOCK(); @@ -2881,11 +2891,11 @@ int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf, struct hwrm_func_cfg_input req = {0}; int rc; - HWRM_PREP(req, FUNC_CFG); + HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB); req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid); req.flags = rte_cpu_to_le_32(flags); - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); HWRM_CHECK_RESULT(); HWRM_UNLOCK(); @@ -2911,7 +2921,7 @@ int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp) struct hwrm_func_buf_rgtr_input req = {.req_type = 0 }; struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr; - HWRM_PREP(req, FUNC_BUF_RGTR); + HWRM_PREP(req, FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB); req.req_buf_num_pages = rte_cpu_to_le_16(1); req.req_buf_page_size = rte_cpu_to_le_16( @@ -2925,7 +2935,7 @@ int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp) return -ENOMEM; } - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); HWRM_CHECK_RESULT(); HWRM_UNLOCK(); @@ -2939,9 +2949,9 @@ int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp) struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 }; struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr; - HWRM_PREP(req, FUNC_BUF_UNRGTR); + HWRM_PREP(req, FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB); - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); HWRM_CHECK_RESULT(); HWRM_UNLOCK(); @@ -2955,7 +2965,7 @@ int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp) struct hwrm_func_cfg_input req = {0}; int rc; - HWRM_PREP(req, FUNC_CFG); + HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB); req.fid = rte_cpu_to_le_16(0xffff); req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags); @@ -2963,7 +2973,7 @@ int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp) HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR); req.async_event_cr = rte_cpu_to_le_16( bp->def_cp_ring->cp_ring_struct->fw_ring_id); - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); HWRM_CHECK_RESULT(); HWRM_UNLOCK(); @@ -2977,13 +2987,13 @@ int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp) struct hwrm_func_vf_cfg_input req = {0}; int rc; - HWRM_PREP(req, FUNC_VF_CFG); + HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB); req.enables = rte_cpu_to_le_32( - HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR); + HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR); req.async_event_cr = rte_cpu_to_le_16( bp->def_cp_ring->cp_ring_struct->fw_ring_id); - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); HWRM_CHECK_RESULT(); HWRM_UNLOCK(); @@ -2999,7 +3009,7 @@ int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf) uint32_t func_cfg_flags; int rc = 0; - HWRM_PREP(req, FUNC_CFG); + HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB); if (is_vf) { dflt_vlan = bp->pf.vf_info[vf].dflt_vlan; @@ -3016,7 +3026,7 @@ int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf) req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN); req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan); - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); HWRM_CHECK_RESULT(); HWRM_UNLOCK(); @@ -3031,13 +3041,13 @@ int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf, struct hwrm_func_cfg_input req = {0}; int rc; - HWRM_PREP(req, FUNC_CFG); + HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB); req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid); req.enables |= rte_cpu_to_le_32(enables); req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags); req.max_bw = rte_cpu_to_le_32(max_bw); - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); HWRM_CHECK_RESULT(); HWRM_UNLOCK(); @@ -3051,14 +3061,14 @@ int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf) struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr; int rc = 0; - HWRM_PREP(req, FUNC_CFG); + HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB); req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags); req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid); req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN); req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan); - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); HWRM_CHECK_RESULT(); HWRM_UNLOCK(); @@ -3088,12 +3098,12 @@ int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id, if (ec_size > sizeof(req.encap_request)) return -1; - HWRM_PREP(req, REJECT_FWD_RESP); + HWRM_PREP(req, REJECT_FWD_RESP, BNXT_USE_CHIMP_MB); req.encap_resp_target_id = rte_cpu_to_le_16(target_id); memcpy(req.encap_request, encaped, ec_size); - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); HWRM_CHECK_RESULT(); HWRM_UNLOCK(); @@ -3108,10 +3118,10 @@ int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf, struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr; int rc; - HWRM_PREP(req, FUNC_QCFG); + HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB); req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid); - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); HWRM_CHECK_RESULT(); @@ -3132,12 +3142,12 @@ int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id, if (ec_size > sizeof(req.encap_request)) return -1; - HWRM_PREP(req, EXEC_FWD_RESP); + HWRM_PREP(req, EXEC_FWD_RESP, BNXT_USE_CHIMP_MB); req.encap_resp_target_id = rte_cpu_to_le_16(target_id); memcpy(req.encap_request, encaped, ec_size); - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); HWRM_CHECK_RESULT(); HWRM_UNLOCK(); @@ -3152,11 +3162,11 @@ int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx, struct hwrm_stat_ctx_query_input req = {.req_type = 0}; struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr; - HWRM_PREP(req, STAT_CTX_QUERY); + HWRM_PREP(req, STAT_CTX_QUERY, BNXT_USE_CHIMP_MB); req.stat_ctx_id = rte_cpu_to_le_32(cid); - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); HWRM_CHECK_RESULT(); @@ -3192,12 +3202,12 @@ int bnxt_hwrm_port_qstats(struct bnxt *bp) struct bnxt_pf_info *pf = &bp->pf; int rc; - HWRM_PREP(req, PORT_QSTATS); + HWRM_PREP(req, PORT_QSTATS, BNXT_USE_CHIMP_MB); req.port_id = rte_cpu_to_le_16(pf->port_id); req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map); req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map); - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); HWRM_CHECK_RESULT(); HWRM_UNLOCK(); @@ -3217,10 +3227,10 @@ int bnxt_hwrm_port_clr_stats(struct bnxt *bp) BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp)) return 0; - HWRM_PREP(req, PORT_CLR_STATS); + HWRM_PREP(req, PORT_CLR_STATS, BNXT_USE_CHIMP_MB); req.port_id = rte_cpu_to_le_16(pf->port_id); - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); HWRM_CHECK_RESULT(); HWRM_UNLOCK(); @@ -3237,9 +3247,9 @@ int bnxt_hwrm_port_led_qcaps(struct bnxt *bp) if (BNXT_VF(bp)) return 0; - HWRM_PREP(req, PORT_LED_QCAPS); + HWRM_PREP(req, PORT_LED_QCAPS, BNXT_USE_CHIMP_MB); req.port_id = bp->pf.port_id; - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); HWRM_CHECK_RESULT(); @@ -3279,7 +3289,7 @@ int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on) if (!bp->num_leds || BNXT_VF(bp)) return -EOPNOTSUPP; - HWRM_PREP(req, PORT_LED_CFG); + HWRM_PREP(req, PORT_LED_CFG, BNXT_USE_CHIMP_MB); if (led_on) { led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT; @@ -3297,7 +3307,7 @@ int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on) led_cfg->led_group_id = bp->leds[i].led_group_id; } - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); HWRM_CHECK_RESULT(); HWRM_UNLOCK(); @@ -3312,9 +3322,9 @@ int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries, struct hwrm_nvm_get_dir_info_input req = {0}; struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr; - HWRM_PREP(req, NVM_GET_DIR_INFO); + HWRM_PREP(req, NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB); - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); HWRM_CHECK_RESULT(); HWRM_UNLOCK(); @@ -3357,9 +3367,9 @@ int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data) "unable to map response address to physical memory\n"); return -ENOMEM; } - HWRM_PREP(req, NVM_GET_DIR_ENTRIES); + HWRM_PREP(req, NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB); req.host_dest_addr = rte_cpu_to_le_64(dma_handle); - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); if (rc == 0) memcpy(data, buf, len > buflen ? buflen : len); @@ -3392,12 +3402,12 @@ int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index, "unable to map response address to physical memory\n"); return -ENOMEM; } - HWRM_PREP(req, NVM_READ); + HWRM_PREP(req, NVM_READ, BNXT_USE_CHIMP_MB); req.host_dest_addr = rte_cpu_to_le_64(dma_handle); req.dir_idx = rte_cpu_to_le_16(index); req.offset = rte_cpu_to_le_32(offset); req.len = rte_cpu_to_le_32(length); - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); if (rc == 0) memcpy(data, buf, length); @@ -3414,9 +3424,9 @@ int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index) struct hwrm_nvm_erase_dir_entry_input req = {0}; struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr; - HWRM_PREP(req, NVM_ERASE_DIR_ENTRY); + HWRM_PREP(req, NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB); req.dir_idx = rte_cpu_to_le_16(index); - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); HWRM_CHECK_RESULT(); HWRM_UNLOCK(); @@ -3448,7 +3458,7 @@ int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type, } memcpy(buf, data, data_len); - HWRM_PREP(req, NVM_WRITE); + HWRM_PREP(req, NVM_WRITE, BNXT_USE_CHIMP_MB); req.dir_type = rte_cpu_to_le_16(dir_type); req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal); @@ -3457,7 +3467,7 @@ int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type, req.dir_data_length = rte_cpu_to_le_32(data_len); req.host_src_addr = rte_cpu_to_le_64(dma_handle); - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); rte_free(buf); HWRM_CHECK_RESULT(); @@ -3499,7 +3509,7 @@ static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf, int rc; /* First query all VNIC ids */ - HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY); + HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB); req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf); req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics); @@ -3511,7 +3521,7 @@ static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf, "unable to map VNIC ID table address to physical memory\n"); return -ENOMEM; } - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); if (rc) { HWRM_UNLOCK(); PMD_DRV_LOG(ERR, "hwrm_func_vf_vnic_query failed rc:%d\n", rc); @@ -3591,7 +3601,7 @@ int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf, struct hwrm_func_cfg_input req = {0}; int rc; - HWRM_PREP(req, FUNC_CFG); + HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB); req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid); req.enables |= rte_cpu_to_le_32( @@ -3599,7 +3609,7 @@ int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf, req.vlan_antispoof_mode = on ? HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN : HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK; - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); HWRM_CHECK_RESULT(); HWRM_UNLOCK(); @@ -3668,7 +3678,7 @@ int bnxt_hwrm_set_em_filter(struct bnxt *bp, if (filter->fw_em_filter_id != UINT64_MAX) bnxt_hwrm_clear_em_filter(bp, filter); - HWRM_PREP(req, CFA_EM_FLOW_ALLOC); + HWRM_PREP(req, CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp)); req.flags = rte_cpu_to_le_32(filter->flags); @@ -3721,7 +3731,7 @@ int bnxt_hwrm_set_em_filter(struct bnxt *bp, req.enables = rte_cpu_to_le_32(enables); - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp)); HWRM_CHECK_RESULT(); @@ -3741,11 +3751,11 @@ int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter) return 0; PMD_DRV_LOG(ERR, "Clear EM filter\n"); - HWRM_PREP(req, CFA_EM_FLOW_FREE); + HWRM_PREP(req, CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp)); req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id); - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp)); HWRM_CHECK_RESULT(); HWRM_UNLOCK(); @@ -3769,7 +3779,7 @@ int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp, if (filter->fw_ntuple_filter_id != UINT64_MAX) bnxt_hwrm_clear_ntuple_filter(bp, filter); - HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC); + HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB); req.flags = rte_cpu_to_le_32(filter->flags); @@ -3832,7 +3842,7 @@ int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp, req.enables = rte_cpu_to_le_32(enables); - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); HWRM_CHECK_RESULT(); @@ -3853,11 +3863,11 @@ int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp, if (filter->fw_ntuple_filter_id == UINT64_MAX) return 0; - HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE); + HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB); req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id); - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); HWRM_CHECK_RESULT(); HWRM_UNLOCK(); @@ -3937,11 +3947,55 @@ int bnxt_hwrm_set_ring_coal(struct bnxt *bp, if (!bnxt_stratus_device(bp)) return 0; - HWRM_PREP(req, RING_CMPL_RING_CFG_AGGINT_PARAMS); + HWRM_PREP(req, RING_CMPL_RING_CFG_AGGINT_PARAMS, BNXT_USE_CHIMP_MB); bnxt_hwrm_set_coal_params(coal, &req); req.ring_id = rte_cpu_to_le_16(ring_id); - rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); HWRM_CHECK_RESULT(); HWRM_UNLOCK(); return 0; } + +int bnxt_hwrm_ext_port_qstats(struct bnxt *bp) +{ + struct hwrm_port_qstats_ext_input req = {0}; + struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr; + struct bnxt_pf_info *pf = &bp->pf; + int rc; + + if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS || + bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS)) + return 0; + + HWRM_PREP(req, PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB); + + req.port_id = rte_cpu_to_le_16(pf->port_id); + if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) { + req.tx_stat_host_addr = + rte_cpu_to_le_64(bp->hw_tx_port_stats_map); + req.tx_stat_size = + rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext)); + } + if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) { + req.rx_stat_host_addr = + rte_cpu_to_le_64(bp->hw_rx_port_stats_map); + req.rx_stat_size = + rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext)); + } + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB); + + if (rc) { + bp->fw_rx_port_stats_ext_size = 0; + bp->fw_tx_port_stats_ext_size = 0; + } else { + bp->fw_rx_port_stats_ext_size = + rte_le_to_cpu_16(resp->rx_stat_size); + bp->fw_tx_port_stats_ext_size = + rte_le_to_cpu_16(resp->tx_stat_size); + } + + HWRM_CHECK_RESULT(); + HWRM_UNLOCK(); + + return rc; +} diff --git a/drivers/net/bnxt/bnxt_hwrm.h b/drivers/net/bnxt/bnxt_hwrm.h index 379aac6e..ec9b3e00 100644 --- a/drivers/net/bnxt/bnxt_hwrm.h +++ b/drivers/net/bnxt/bnxt_hwrm.h @@ -32,6 +32,10 @@ struct bnxt_cp_ring_info; #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC \ HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL_STATIC +#define HWRM_SPEC_CODE_1_8_4 0x10804 +#define HWRM_SPEC_CODE_1_9_0 0x10900 +#define HWRM_SPEC_CODE_1_9_2 0x10902 + int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic); int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic, @@ -174,4 +178,5 @@ int bnxt_vnic_rss_configure(struct bnxt *bp, int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_coal *coal, uint16_t ring_id); int bnxt_hwrm_check_vf_rings(struct bnxt *bp); +int bnxt_hwrm_ext_port_qstats(struct bnxt *bp); #endif diff --git a/drivers/net/bnxt/bnxt_rxq.c b/drivers/net/bnxt/bnxt_rxq.c index 832fc9ec..5345d393 100644 --- a/drivers/net/bnxt/bnxt_rxq.c +++ b/drivers/net/bnxt/bnxt_rxq.c @@ -43,21 +43,19 @@ int bnxt_mq_rx_configure(struct bnxt *bp) /* Single queue mode */ if (bp->rx_cp_nr_rings < 2) { - vnic = bnxt_alloc_vnic(bp); + vnic = &bp->vnic_info[0]; if (!vnic) { PMD_DRV_LOG(ERR, "VNIC alloc failed\n"); rc = -ENOMEM; goto err_out; } vnic->flags |= BNXT_VNIC_INFO_BCAST; - STAILQ_INSERT_TAIL(&bp->ff_pool[0], vnic, next); bp->nr_vnics++; rxq = bp->eth_dev->data->rx_queues[0]; rxq->vnic = vnic; vnic->func_default = true; - vnic->ff_pool_idx = 0; vnic->start_grp_id = 0; vnic->end_grp_id = vnic->start_grp_id; filter = bnxt_alloc_filter(bp); @@ -85,6 +83,9 @@ int bnxt_mq_rx_configure(struct bnxt *bp) RTE_MIN(bp->max_l2_ctx, RTE_MIN(bp->max_rsscos_ctx, ETH_64_POOLS))); + PMD_DRV_LOG(DEBUG, + "pools = %u max_pools = %u\n", + pools, max_pools); if (pools > max_pools) pools = max_pools; break; @@ -98,25 +99,27 @@ int bnxt_mq_rx_configure(struct bnxt *bp) goto err_out; } } - nb_q_per_grp = bp->rx_cp_nr_rings / pools; + PMD_DRV_LOG(ERR, "pools = %u nb_q_per_grp = %u\n", pools, nb_q_per_grp); start_grp_id = 0; end_grp_id = nb_q_per_grp; for (i = 0; i < pools; i++) { - vnic = bnxt_alloc_vnic(bp); + vnic = &bp->vnic_info[i]; if (!vnic) { PMD_DRV_LOG(ERR, "VNIC alloc failed\n"); rc = -ENOMEM; goto err_out; } vnic->flags |= BNXT_VNIC_INFO_BCAST; - STAILQ_INSERT_TAIL(&bp->ff_pool[i], vnic, next); bp->nr_vnics++; for (j = 0; j < nb_q_per_grp; j++, ring_idx++) { rxq = bp->eth_dev->data->rx_queues[ring_idx]; rxq->vnic = vnic; + PMD_DRV_LOG(DEBUG, + "rxq[%d] = %p vnic[%d] = %p\n", + ring_idx, rxq, i, vnic); } if (i == 0) { if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_DCB) { @@ -125,7 +128,6 @@ int bnxt_mq_rx_configure(struct bnxt *bp) } vnic->func_default = true; } - vnic->ff_pool_idx = i; vnic->start_grp_id = start_grp_id; vnic->end_grp_id = end_grp_id; @@ -176,7 +178,7 @@ out: hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6; for (i = 0; i < bp->nr_vnics; i++) { - STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) { + vnic = &bp->vnic_info[i]; vnic->hash_type = hash_type; /* @@ -187,7 +189,6 @@ out: rss->rss_key_len <= HW_HASH_KEY_SIZE) memcpy(vnic->rss_hash_key, rss->rss_key, rss->rss_key_len); - } } } @@ -331,8 +332,10 @@ int bnxt_rx_queue_setup_op(struct rte_eth_dev *eth_dev, rxq->queue_id = queue_idx; rxq->port_id = eth_dev->data->port_id; - rxq->crc_len = rte_eth_dev_must_keep_crc(rx_offloads) ? - ETHER_CRC_LEN : 0; + if (rx_offloads & DEV_RX_OFFLOAD_KEEP_CRC) + rxq->crc_len = ETHER_CRC_LEN; + else + rxq->crc_len = 0; eth_dev->data->rx_queues[queue_idx] = rxq; /* Allocate RX ring hardware descriptors */ diff --git a/drivers/net/bnxt/bnxt_stats.c b/drivers/net/bnxt/bnxt_stats.c index a5d3c866..c16bf99d 100644 --- a/drivers/net/bnxt/bnxt_stats.c +++ b/drivers/net/bnxt/bnxt_stats.c @@ -26,8 +26,8 @@ static const struct bnxt_xstats_name_off bnxt_rx_stats_strings[] = { rx_256b_511b_frames)}, {"rx_512b_1023b_frames", offsetof(struct rx_port_stats, rx_512b_1023b_frames)}, - {"rx_1024b_1518_frames", offsetof(struct rx_port_stats, - rx_1024b_1518_frames)}, + {"rx_1024b_1518b_frames", offsetof(struct rx_port_stats, + rx_1024b_1518b_frames)}, {"rx_good_vlan_frames", offsetof(struct rx_port_stats, rx_good_vlan_frames)}, {"rx_1519b_2047b_frames", offsetof(struct rx_port_stats, @@ -93,12 +93,12 @@ static const struct bnxt_xstats_name_off bnxt_tx_stats_strings[] = { tx_256b_511b_frames)}, {"tx_512b_1023b_frames", offsetof(struct tx_port_stats, tx_512b_1023b_frames)}, - {"tx_1024b_1518_frames", offsetof(struct tx_port_stats, - tx_1024b_1518_frames)}, + {"tx_1024b_1518b_frames", offsetof(struct tx_port_stats, + tx_1024b_1518b_frames)}, {"tx_good_vlan_frames", offsetof(struct tx_port_stats, tx_good_vlan_frames)}, - {"tx_1519b_2047_frames", offsetof(struct tx_port_stats, - tx_1519b_2047_frames)}, + {"tx_1519b_2047b_frames", offsetof(struct tx_port_stats, + tx_1519b_2047b_frames)}, {"tx_2048b_4095b_frames", offsetof(struct tx_port_stats, tx_2048b_4095b_frames)}, {"tx_4096b_9216b_frames", offsetof(struct tx_port_stats, @@ -180,6 +180,150 @@ static const struct bnxt_xstats_name_off bnxt_func_stats_strings[] = { rx_agg_aborts)}, }; +static const struct bnxt_xstats_name_off bnxt_rx_ext_stats_strings[] = { + {"link_down_events", offsetof(struct rx_port_stats_ext, + link_down_events)}, + {"continuous_pause_events", offsetof(struct rx_port_stats_ext, + continuous_pause_events)}, + {"resume_pause_events", offsetof(struct rx_port_stats_ext, + resume_pause_events)}, + {"continuous_roce_pause_events", offsetof(struct rx_port_stats_ext, + continuous_roce_pause_events)}, + {"resume_roce_pause_events", offsetof(struct rx_port_stats_ext, + resume_roce_pause_events)}, + {"rx_bytes_cos0", offsetof(struct rx_port_stats_ext, + rx_bytes_cos0)}, + {"rx_bytes_cos1", offsetof(struct rx_port_stats_ext, + rx_bytes_cos1)}, + {"rx_bytes_cos2", offsetof(struct rx_port_stats_ext, + rx_bytes_cos2)}, + {"rx_bytes_cos3", offsetof(struct rx_port_stats_ext, + rx_bytes_cos3)}, + {"rx_bytes_cos4", offsetof(struct rx_port_stats_ext, + rx_bytes_cos4)}, + {"rx_bytes_cos5", offsetof(struct rx_port_stats_ext, + rx_bytes_cos5)}, + {"rx_bytes_cos6", offsetof(struct rx_port_stats_ext, + rx_bytes_cos6)}, + {"rx_bytes_cos7", offsetof(struct rx_port_stats_ext, + rx_bytes_cos7)}, + {"rx_packets_cos0", offsetof(struct rx_port_stats_ext, + rx_packets_cos0)}, + {"rx_packets_cos1", offsetof(struct rx_port_stats_ext, + rx_packets_cos1)}, + {"rx_packets_cos2", offsetof(struct rx_port_stats_ext, + rx_packets_cos2)}, + {"rx_packets_cos3", offsetof(struct rx_port_stats_ext, + rx_packets_cos3)}, + {"rx_packets_cos4", offsetof(struct rx_port_stats_ext, + rx_packets_cos4)}, + {"rx_packets_cos5", offsetof(struct rx_port_stats_ext, + rx_packets_cos5)}, + {"rx_packets_cos6", offsetof(struct rx_port_stats_ext, + rx_packets_cos6)}, + {"rx_packets_cos7", offsetof(struct rx_port_stats_ext, + rx_packets_cos7)}, + {"pfc_pri0_rx_duration_us", offsetof(struct rx_port_stats_ext, + pfc_pri0_rx_duration_us)}, + {"pfc_pri0_rx_transitions", offsetof(struct rx_port_stats_ext, + pfc_pri0_rx_transitions)}, + {"pfc_pri1_rx_duration_us", offsetof(struct rx_port_stats_ext, + pfc_pri1_rx_duration_us)}, + {"pfc_pri1_rx_transitions", offsetof(struct rx_port_stats_ext, + pfc_pri1_rx_transitions)}, + {"pfc_pri2_rx_duration_us", offsetof(struct rx_port_stats_ext, + pfc_pri2_rx_duration_us)}, + {"pfc_pri2_rx_transitions", offsetof(struct rx_port_stats_ext, + pfc_pri2_rx_transitions)}, + {"pfc_pri3_rx_duration_us", offsetof(struct rx_port_stats_ext, + pfc_pri3_rx_duration_us)}, + {"pfc_pri3_rx_transitions", offsetof(struct rx_port_stats_ext, + pfc_pri3_rx_transitions)}, + {"pfc_pri4_rx_duration_us", offsetof(struct rx_port_stats_ext, + pfc_pri4_rx_duration_us)}, + {"pfc_pri4_rx_transitions", offsetof(struct rx_port_stats_ext, + pfc_pri4_rx_transitions)}, + {"pfc_pri5_rx_duration_us", offsetof(struct rx_port_stats_ext, + pfc_pri5_rx_duration_us)}, + {"pfc_pri5_rx_transitions", offsetof(struct rx_port_stats_ext, + pfc_pri5_rx_transitions)}, + {"pfc_pri6_rx_duration_us", offsetof(struct rx_port_stats_ext, + pfc_pri6_rx_duration_us)}, + {"pfc_pri6_rx_transitions", offsetof(struct rx_port_stats_ext, + pfc_pri6_rx_transitions)}, + {"pfc_pri7_rx_duration_us", offsetof(struct rx_port_stats_ext, + pfc_pri7_rx_duration_us)}, + {"pfc_pri7_rx_transitions", offsetof(struct rx_port_stats_ext, + pfc_pri7_rx_transitions)}, +}; + +static const struct bnxt_xstats_name_off bnxt_tx_ext_stats_strings[] = { + {"tx_bytes_cos0", offsetof(struct tx_port_stats_ext, + tx_bytes_cos0)}, + {"tx_bytes_cos1", offsetof(struct tx_port_stats_ext, + tx_bytes_cos1)}, + {"tx_bytes_cos2", offsetof(struct tx_port_stats_ext, + tx_bytes_cos2)}, + {"tx_bytes_cos3", offsetof(struct tx_port_stats_ext, + tx_bytes_cos3)}, + {"tx_bytes_cos4", offsetof(struct tx_port_stats_ext, + tx_bytes_cos4)}, + {"tx_bytes_cos5", offsetof(struct tx_port_stats_ext, + tx_bytes_cos5)}, + {"tx_bytes_cos6", offsetof(struct tx_port_stats_ext, + tx_bytes_cos6)}, + {"tx_bytes_cos7", offsetof(struct tx_port_stats_ext, + tx_bytes_cos7)}, + {"tx_packets_cos0", offsetof(struct tx_port_stats_ext, + tx_packets_cos0)}, + {"tx_packets_cos1", offsetof(struct tx_port_stats_ext, + tx_packets_cos1)}, + {"tx_packets_cos2", offsetof(struct tx_port_stats_ext, + tx_packets_cos2)}, + {"tx_packets_cos3", offsetof(struct tx_port_stats_ext, + tx_packets_cos3)}, + {"tx_packets_cos4", offsetof(struct tx_port_stats_ext, + tx_packets_cos4)}, + {"tx_packets_cos5", offsetof(struct tx_port_stats_ext, + tx_packets_cos5)}, + {"tx_packets_cos6", offsetof(struct tx_port_stats_ext, + tx_packets_cos6)}, + {"tx_packets_cos7", offsetof(struct tx_port_stats_ext, + tx_packets_cos7)}, + {"pfc_pri0_tx_duration_us", offsetof(struct tx_port_stats_ext, + pfc_pri0_tx_duration_us)}, + {"pfc_pri0_tx_transitions", offsetof(struct tx_port_stats_ext, + pfc_pri0_tx_transitions)}, + {"pfc_pri1_tx_duration_us", offsetof(struct tx_port_stats_ext, + pfc_pri1_tx_duration_us)}, + {"pfc_pri1_tx_transitions", offsetof(struct tx_port_stats_ext, + pfc_pri1_tx_transitions)}, + {"pfc_pri2_tx_duration_us", offsetof(struct tx_port_stats_ext, + pfc_pri2_tx_duration_us)}, + {"pfc_pri2_tx_transitions", offsetof(struct tx_port_stats_ext, + pfc_pri2_tx_transitions)}, + {"pfc_pri3_tx_duration_us", offsetof(struct tx_port_stats_ext, + pfc_pri3_tx_duration_us)}, + {"pfc_pri3_tx_transitions", offsetof(struct tx_port_stats_ext, + pfc_pri3_tx_transitions)}, + {"pfc_pri4_tx_duration_us", offsetof(struct tx_port_stats_ext, + pfc_pri4_tx_duration_us)}, + {"pfc_pri4_tx_transitions", offsetof(struct tx_port_stats_ext, + pfc_pri4_tx_transitions)}, + {"pfc_pri5_tx_duration_us", offsetof(struct tx_port_stats_ext, + pfc_pri5_tx_duration_us)}, + {"pfc_pri5_tx_transitions", offsetof(struct tx_port_stats_ext, + pfc_pri5_tx_transitions)}, + {"pfc_pri6_tx_duration_us", offsetof(struct tx_port_stats_ext, + pfc_pri6_tx_duration_us)}, + {"pfc_pri6_tx_transitions", offsetof(struct tx_port_stats_ext, + pfc_pri6_tx_transitions)}, + {"pfc_pri7_tx_duration_us", offsetof(struct tx_port_stats_ext, + pfc_pri7_tx_duration_us)}, + {"pfc_pri7_tx_transitions", offsetof(struct tx_port_stats_ext, + pfc_pri7_tx_transitions)}, +}; + /* * Statistics functions */ @@ -265,12 +409,22 @@ int bnxt_dev_xstats_get_op(struct rte_eth_dev *eth_dev, unsigned int count, i; uint64_t tx_drop_pkts; + unsigned int rx_port_stats_ext_cnt; + unsigned int tx_port_stats_ext_cnt; + unsigned int stat_size = sizeof(uint64_t); + unsigned int stat_count; bnxt_hwrm_port_qstats(bp); bnxt_hwrm_func_qstats_tx_drop(bp, 0xffff, &tx_drop_pkts); + bnxt_hwrm_ext_port_qstats(bp); + rx_port_stats_ext_cnt = bp->fw_rx_port_stats_ext_size / stat_size; + tx_port_stats_ext_cnt = bp->fw_tx_port_stats_ext_size / stat_size; count = RTE_DIM(bnxt_rx_stats_strings) + - RTE_DIM(bnxt_tx_stats_strings) + 1; /* For tx_drop_pkts */ + RTE_DIM(bnxt_tx_stats_strings) + 1/* For tx_drop_pkts */ + + RTE_DIM(bnxt_rx_ext_stats_strings) + + RTE_DIM(bnxt_tx_ext_stats_strings); + stat_count = count; if (n < count) return count; @@ -299,7 +453,27 @@ int bnxt_dev_xstats_get_op(struct rte_eth_dev *eth_dev, xstats[count].value = rte_le_to_cpu_64(tx_drop_pkts); count++; - return count; + for (i = 0; i < tx_port_stats_ext_cnt; i++) { + uint64_t *tx_stats_ext = (uint64_t *)bp->hw_tx_port_stats_ext; + + xstats[count].value = rte_le_to_cpu_64 + (*(uint64_t *)((char *)tx_stats_ext + + bnxt_tx_ext_stats_strings[i].offset)); + + count++; + } + + for (i = 0; i < rx_port_stats_ext_cnt; i++) { + uint64_t *rx_stats_ext = (uint64_t *)bp->hw_rx_port_stats_ext; + + xstats[count].value = rte_le_to_cpu_64 + (*(uint64_t *)((char *)rx_stats_ext + + bnxt_rx_ext_stats_strings[i].offset)); + + count++; + } + + return stat_count; } int bnxt_dev_xstats_get_names_op(__rte_unused struct rte_eth_dev *eth_dev, @@ -308,7 +482,9 @@ int bnxt_dev_xstats_get_names_op(__rte_unused struct rte_eth_dev *eth_dev, { /* Account for the Tx drop pkts aka the Anti spoof counter */ const unsigned int stat_cnt = RTE_DIM(bnxt_rx_stats_strings) + - RTE_DIM(bnxt_tx_stats_strings) + 1; + RTE_DIM(bnxt_tx_stats_strings) + 1 + + RTE_DIM(bnxt_rx_ext_stats_strings) + + RTE_DIM(bnxt_tx_ext_stats_strings); unsigned int i, count; if (xstats_names != NULL) { @@ -335,6 +511,25 @@ int bnxt_dev_xstats_get_names_op(__rte_unused struct rte_eth_dev *eth_dev, "%s", bnxt_func_stats_strings[4].name); count++; + + for (i = 0; i < RTE_DIM(bnxt_rx_ext_stats_strings); i++) { + snprintf(xstats_names[count].name, + sizeof(xstats_names[count].name), + "%s", + bnxt_rx_ext_stats_strings[i].name); + + count++; + } + + for (i = 0; i < RTE_DIM(bnxt_tx_ext_stats_strings); i++) { + snprintf(xstats_names[count].name, + sizeof(xstats_names[count].name), + "%s", + bnxt_tx_ext_stats_strings[i].name); + + count++; + } + } return stat_cnt; } @@ -359,7 +554,9 @@ int bnxt_dev_xstats_get_by_id_op(struct rte_eth_dev *dev, const uint64_t *ids, { /* Account for the Tx drop pkts aka the Anti spoof counter */ const unsigned int stat_cnt = RTE_DIM(bnxt_rx_stats_strings) + - RTE_DIM(bnxt_tx_stats_strings) + 1; + RTE_DIM(bnxt_tx_stats_strings) + 1 + + RTE_DIM(bnxt_rx_ext_stats_strings) + + RTE_DIM(bnxt_tx_ext_stats_strings); struct rte_eth_xstat xstats[stat_cnt]; uint64_t values_copy[stat_cnt]; uint16_t i; @@ -384,7 +581,9 @@ int bnxt_dev_xstats_get_names_by_id_op(struct rte_eth_dev *dev, { /* Account for the Tx drop pkts aka the Anti spoof counter */ const unsigned int stat_cnt = RTE_DIM(bnxt_rx_stats_strings) + - RTE_DIM(bnxt_tx_stats_strings) + 1; + RTE_DIM(bnxt_tx_stats_strings) + 1 + + RTE_DIM(bnxt_rx_ext_stats_strings) + + RTE_DIM(bnxt_tx_ext_stats_strings); struct rte_eth_xstat_name xstats_names_copy[stat_cnt]; uint16_t i; diff --git a/drivers/net/bnxt/bnxt_txr.c b/drivers/net/bnxt/bnxt_txr.c index 67bb35e0..39be7bdf 100644 --- a/drivers/net/bnxt/bnxt_txr.c +++ b/drivers/net/bnxt/bnxt_txr.c @@ -120,7 +120,7 @@ static uint16_t bnxt_start_xmit(struct rte_mbuf *tx_pkt, { struct bnxt_tx_ring_info *txr = txq->tx_ring; struct tx_bd_long *txbd; - struct tx_bd_long_hi *txbd1; + struct tx_bd_long_hi *txbd1 = NULL; uint32_t vlan_tag_flags, cfa_action; bool long_bd = false; uint16_t last_prod = 0; @@ -295,7 +295,8 @@ static uint16_t bnxt_start_xmit(struct rte_mbuf *tx_pkt, } txbd->flags_type |= TX_BD_LONG_FLAGS_PACKET_END; - txbd1->lflags = rte_cpu_to_le_32(txbd1->lflags); + if (txbd1) + txbd1->lflags = rte_cpu_to_le_32(txbd1->lflags); txr->tx_prod = RING_NEXT(txr->tx_ring_struct, txr->tx_prod); diff --git a/drivers/net/bnxt/bnxt_vnic.c b/drivers/net/bnxt/bnxt_vnic.c index c0577cd7..aebfb1f1 100644 --- a/drivers/net/bnxt/bnxt_vnic.c +++ b/drivers/net/bnxt/bnxt_vnic.c @@ -57,29 +57,6 @@ void bnxt_init_vnics(struct bnxt *bp) STAILQ_INIT(&vnic->flow_list); STAILQ_INSERT_TAIL(&bp->free_vnic_list, vnic, next); } - for (i = 0; i < MAX_FF_POOLS; i++) - STAILQ_INIT(&bp->ff_pool[i]); -} - -int bnxt_free_vnic(struct bnxt *bp, struct bnxt_vnic_info *vnic, - int pool) -{ - struct bnxt_vnic_info *temp; - - temp = STAILQ_FIRST(&bp->ff_pool[pool]); - while (temp) { - if (temp == vnic) { - STAILQ_REMOVE(&bp->ff_pool[pool], vnic, - bnxt_vnic_info, next); - vnic->fw_vnic_id = (uint16_t)HWRM_NA_SIGNATURE; - STAILQ_INSERT_TAIL(&bp->free_vnic_list, vnic, - next); - return 0; - } - temp = STAILQ_NEXT(temp, next); - } - PMD_DRV_LOG(ERR, "VNIC %p is not found in pool[%d]\n", vnic, pool); - return -EINVAL; } struct bnxt_vnic_info *bnxt_alloc_vnic(struct bnxt *bp) @@ -98,26 +75,22 @@ struct bnxt_vnic_info *bnxt_alloc_vnic(struct bnxt *bp) void bnxt_free_all_vnics(struct bnxt *bp) { - struct bnxt_vnic_info *temp, *next; - int i; + struct bnxt_vnic_info *temp; + unsigned int i; - for (i = 0; i < MAX_FF_POOLS; i++) { - temp = STAILQ_FIRST(&bp->ff_pool[i]); - while (temp) { - next = STAILQ_NEXT(temp, next); - STAILQ_REMOVE(&bp->ff_pool[i], temp, bnxt_vnic_info, - next); - STAILQ_INSERT_TAIL(&bp->free_vnic_list, temp, next); - temp = next; - } + for (i = 0; i < bp->nr_vnics; i++) { + temp = &bp->vnic_info[i]; + STAILQ_INSERT_TAIL(&bp->free_vnic_list, temp, next); } } void bnxt_free_vnic_attributes(struct bnxt *bp) { struct bnxt_vnic_info *vnic; + unsigned int i; - STAILQ_FOREACH(vnic, &bp->free_vnic_list, next) { + for (i = 0; i < bp->max_vnics; i++) { + vnic = &bp->vnic_info[i]; if (vnic->rss_table) { /* 'Unreserve' the rss_table */ /* N/A */ diff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h index f5c7b422..e8005793 100644 --- a/drivers/net/bnxt/hsi_struct_def_dpdk.h +++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h @@ -67,6 +67,10 @@ struct hwrm_resp_hdr { #define TLV_TYPE_HWRM_RESPONSE UINT32_C(0x2) /* RoCE slow path command */ #define TLV_TYPE_ROCE_SP_COMMAND UINT32_C(0x3) +/* RoCE slow path command to query CC Gen1 support. */ +#define TLV_TYPE_QUERY_ROCE_CC_GEN1 UINT32_C(0xcommand 0x0005) +/* RoCE slow path command to modify CC Gen1 support. */ +#define TLV_TYPE_MODIFY_ROCE_CC_GEN1 UINT32_C(0xcommand 0x0005) /* Engine CKV - The device's serial number. */ #define TLV_TYPE_ENGINE_CKV_DEVICE_SERIAL_NUMBER UINT32_C(0x8001) /* Engine CKV - Per-function random nonce data. */ @@ -256,6 +260,7 @@ struct cmd_nums { */ uint16_t req_type; #define HWRM_VER_GET UINT32_C(0x0) + #define HWRM_FUNC_DRV_IF_CHANGE UINT32_C(0xd) #define HWRM_FUNC_BUF_UNRGTR UINT32_C(0xe) #define HWRM_FUNC_VF_CFG UINT32_C(0xf) /* Reserved for future use. */ @@ -328,6 +333,7 @@ struct cmd_nums { #define HWRM_RING_FREE UINT32_C(0x51) #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS UINT32_C(0x52) #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS UINT32_C(0x53) + #define HWRM_RING_AGGINT_QCAPS UINT32_C(0x54) #define HWRM_RING_RESET UINT32_C(0x5e) #define HWRM_RING_GRP_ALLOC UINT32_C(0x60) #define HWRM_RING_GRP_FREE UINT32_C(0x61) @@ -367,6 +373,8 @@ struct cmd_nums { #define HWRM_PORT_QSTATS_EXT UINT32_C(0xb4) #define HWRM_FW_RESET UINT32_C(0xc0) #define HWRM_FW_QSTATUS UINT32_C(0xc1) + #define HWRM_FW_HEALTH_CHECK UINT32_C(0xc2) + #define HWRM_FW_SYNC UINT32_C(0xc3) /* Experimental */ #define HWRM_FW_SET_TIME UINT32_C(0xc8) /* Experimental */ @@ -433,6 +441,7 @@ struct cmd_nums { /* Experimental */ #define HWRM_FW_IPC_MSG UINT32_C(0x110) #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO UINT32_C(0x111) + #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE UINT32_C(0x112) /* Engine CKV - Ping the device and SRT firmware to get the public key. */ #define HWRM_ENGINE_CKV_HELLO UINT32_C(0x12d) /* Engine CKV - Get the current allocation status of keys provisioned in the key vault. */ @@ -515,6 +524,10 @@ struct cmd_nums { #define HWRM_FUNC_BACKING_STORE_CFG UINT32_C(0x193) /* Experimental */ #define HWRM_FUNC_BACKING_STORE_QCFG UINT32_C(0x194) + /* Configures the BW of any VF */ + #define HWRM_FUNC_VF_BW_CFG UINT32_C(0x195) + /* Queries the BW of any VF */ + #define HWRM_FUNC_VF_BW_QCFG UINT32_C(0x196) /* Experimental */ #define HWRM_SELFTEST_QLIST UINT32_C(0x200) /* Experimental */ @@ -544,8 +557,12 @@ struct cmd_nums { #define HWRM_DBG_COREDUMP_INITIATE UINT32_C(0xff18) /* Experimental */ #define HWRM_DBG_COREDUMP_RETRIEVE UINT32_C(0xff19) + /* Experimental */ + #define HWRM_DBG_FW_CLI UINT32_C(0xff1a) /* */ #define HWRM_DBG_I2C_CMD UINT32_C(0xff1b) + /* */ + #define HWRM_DBG_RING_INFO_GET UINT32_C(0xff1c) /* Experimental */ #define HWRM_NVM_FACTORY_DEFAULTS UINT32_C(0xffee) #define HWRM_NVM_VALIDATE_OPTION UINT32_C(0xffef) @@ -616,6 +633,11 @@ struct ret_codes { */ #define HWRM_ERR_CODE_NO_BUFFER UINT32_C(0x8) /* + * This error code is only reported by firmware when some + * sub-option of a supported HWRM command is unsupported. + */ + #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR UINT32_C(0x9) + /* * Generic HWRM execution error that represents an * internal error. */ @@ -686,8 +708,8 @@ struct hwrm_err_output { #define HWRM_VERSION_MINOR 9 #define HWRM_VERSION_UPDATE 2 /* non-zero means beta version */ -#define HWRM_VERSION_RSVD 9 -#define HWRM_VERSION_STR "1.9.2.9" +#define HWRM_VERSION_RSVD 53 +#define HWRM_VERSION_STR "1.9.2.53" /**************** * hwrm_ver_get * @@ -902,6 +924,42 @@ struct hwrm_ver_get_output { #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED \ UINT32_C(0x8) /* + * If set to 1, then the KONG host mailbox channel is supported. + * If set to 0, then the KONG host mailbox channel is not supported. + * By default, this flag should be 0 for older version of core firmware. + */ + #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED \ + UINT32_C(0x10) + /* + * If set to 1, then the 64bit flow handle is supported in addition to the + * legacy 16bit flow handle. If set to 0, then the 64bit flow handle is not + * supported. By default, this flag should be 0 for older version of core firmware. + */ + #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED \ + UINT32_C(0x20) + /* + * If set to 1, then filter type can be provided in filter_alloc or filter_cfg + * filter types like L2 for l2 traffic and ROCE for roce & l2 traffic. + * If set to 0, then filter types not supported. + * By default, this flag should be 0 for older version of core firmware. + */ + #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_L2_FILTER_TYPES_ROCE_OR_L2_SUPPORTED \ + UINT32_C(0x40) + /* + * If set to 1, firmware is capable to support virtio vSwitch offload model. + * If set to 0, firmware can't supported virtio vSwitch offload model. + * By default, this flag should be 0 for older version of core firmware. + */ + #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_VIRTIO_VSWITCH_OFFLOAD_SUPPORTED \ + UINT32_C(0x80) + /* + * If set to 1, firmware is capable to support trusted VF. + * If set to 0, firmware is not capable to support trusted VF. + * By default, this flag should be 0 for older version of core firmware. + */ + #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED \ + UINT32_C(0x100) + /* * This field represents the major version of RoCE firmware. * A change in major version represents a major release. */ @@ -1154,39 +1212,45 @@ struct hwrm_ver_get_output { struct bd_base { uint8_t type; /* This value identifies the type of buffer descriptor. */ - #define BD_BASE_TYPE_MASK UINT32_C(0x3f) - #define BD_BASE_TYPE_SFT 0 + #define BD_BASE_TYPE_MASK UINT32_C(0x3f) + #define BD_BASE_TYPE_SFT 0 /* * Indicates that this BD is 16B long and is used for * normal L2 packet transmission. */ - #define BD_BASE_TYPE_TX_BD_SHORT UINT32_C(0x0) + #define BD_BASE_TYPE_TX_BD_SHORT UINT32_C(0x0) /* * Indicates that this BD is 1BB long and is an empty * TX BD. Not valid for use by the driver. */ - #define BD_BASE_TYPE_TX_BD_EMPTY UINT32_C(0x1) + #define BD_BASE_TYPE_TX_BD_EMPTY UINT32_C(0x1) /* * Indicates that this BD is 16B long and is an RX Producer * (ie. empty) buffer descriptor. */ - #define BD_BASE_TYPE_RX_PROD_PKT UINT32_C(0x4) + #define BD_BASE_TYPE_RX_PROD_PKT UINT32_C(0x4) /* * Indicates that this BD is 16B long and is an RX * Producer Buffer BD. */ - #define BD_BASE_TYPE_RX_PROD_BFR UINT32_C(0x5) + #define BD_BASE_TYPE_RX_PROD_BFR UINT32_C(0x5) /* * Indicates that this BD is 16B long and is an * RX Producer Assembly Buffer Descriptor. */ - #define BD_BASE_TYPE_RX_PROD_AGG UINT32_C(0x6) + #define BD_BASE_TYPE_RX_PROD_AGG UINT32_C(0x6) /* * Indicates that this BD is 32B long and is used for * normal L2 packet transmission. */ - #define BD_BASE_TYPE_TX_BD_LONG UINT32_C(0x10) - #define BD_BASE_TYPE_LAST BD_BASE_TYPE_TX_BD_LONG + #define BD_BASE_TYPE_TX_BD_LONG UINT32_C(0x10) + /* + * Indicates that this BD is 32B long and is used for + * L2 packet transmission for small packets that require + * low latency. + */ + #define BD_BASE_TYPE_TX_BD_LONG_INLINE UINT32_C(0x11) + #define BD_BASE_TYPE_LAST BD_BASE_TYPE_TX_BD_LONG_INLINE uint8_t unused_1[7]; } __attribute__((packed)); @@ -1406,6 +1470,7 @@ struct tx_bd_long { uint64_t address; } __attribute__((packed)); +/* Last 16 bytes of tx_bd_long. */ /* tx_bd_long_hi (size:128b/16B) */ struct tx_bd_long_hi { /* @@ -1595,6 +1660,219 @@ struct tx_bd_long_hi { TX_BD_LONG_CFA_META_KEY_VLAN_TAG } __attribute__((packed)); +/* + * This structure is used to inform the NIC of packet data that needs to be + * transmitted with additional processing that requires extra data such as + * VLAN insertion plus attached inline data. This BD type may be used to + * improve latency for small packets needing the additional extended features + * supported by long BDs. + */ +/* tx_bd_long_inline (size:256b/32B) */ +struct tx_bd_long_inline { + uint16_t flags_type; + /* This value identifies the type of buffer descriptor. */ + #define TX_BD_LONG_INLINE_TYPE_MASK UINT32_C(0x3f) + #define TX_BD_LONG_INLINE_TYPE_SFT 0 + /* + * This type of BD is 32B long and is used for inline L2 packet + * transmission. + */ + #define TX_BD_LONG_INLINE_TYPE_TX_BD_LONG_INLINE UINT32_C(0x11) + #define TX_BD_LONG_INLINE_TYPE_LAST \ + TX_BD_LONG_INLINE_TYPE_TX_BD_LONG_INLINE + /* + * All bits in this field may be set on the first BD of a packet. + * Only the packet_end bit may be set in non-first BDs. + */ + #define TX_BD_LONG_INLINE_FLAGS_MASK UINT32_C(0xffc0) + #define TX_BD_LONG_INLINE_FLAGS_SFT 6 + /* + * If set to 1, the packet ends with the data in the buffer + * pointed to by this descriptor. This flag must be + * valid on every BD. + */ + #define TX_BD_LONG_INLINE_FLAGS_PACKET_END UINT32_C(0x40) + /* + * If set to 1, the device will not generate a completion for + * this transmit packet unless there is an error in its processing. + * If this bit is set to 0, then the packet will be completed + * normally. + * + * This bit may be set only on the first BD of a packet. + */ + #define TX_BD_LONG_INLINE_FLAGS_NO_CMPL UINT32_C(0x80) + /* + * This value indicates how many 16B BD locations are consumed + * in the ring by this packet, including the BD and inline + * data. + */ + #define TX_BD_LONG_INLINE_FLAGS_BD_CNT_MASK UINT32_C(0x1f00) + #define TX_BD_LONG_INLINE_FLAGS_BD_CNT_SFT 8 + /* This field is deprecated. */ + #define TX_BD_LONG_INLINE_FLAGS_LHINT_MASK UINT32_C(0x6000) + #define TX_BD_LONG_INLINE_FLAGS_LHINT_SFT 13 + /* + * If set to 1, the device immediately updates the Send Consumer + * Index after the buffer associated with this descriptor has + * been transferred via DMA to NIC memory from host memory. An + * interrupt may or may not be generated according to the state + * of the interrupt avoidance mechanisms. If this bit + * is set to 0, then the Consumer Index is only updated as soon + * as one of the host interrupt coalescing conditions has been met. + * + * This bit must be valid on the first BD of a packet. + */ + #define TX_BD_LONG_INLINE_FLAGS_COAL_NOW UINT32_C(0x8000) + /* + * This is the length of the inline data, not including BD length, in + * bytes. + * The maximum value is 480. + * + * This field must be valid on all BDs of a packet. + */ + uint16_t len; + /* + * The opaque data field is passed through to the completion and can be + * used for any data that the driver wants to associate with the transmit + * BD. + * + * This field must be valid on the first BD of a packet. + */ + uint32_t opaque; + uint64_t unused1; + /* + * All bits in this field must be valid on the first BD of a packet. + * Their value on other BDs of the packet is ignored. + */ + uint16_t lflags; + /* + * If set to 1, the controller replaces the TCP/UPD checksum + * fields of normal TCP/UPD checksum, or the inner TCP/UDP + * checksum field of the encapsulated TCP/UDP packets with the + * hardware calculated TCP/UDP checksum for the packet associated + * with this descriptor. The flag is ignored if the LSO flag is set. + */ + #define TX_BD_LONG_INLINE_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1) + /* + * If set to 1, the controller replaces the IP checksum of the + * normal packets, or the inner IP checksum of the encapsulated + * packets with the hardware calculated IP checksum for the + * packet associated with this descriptor. + */ + #define TX_BD_LONG_INLINE_LFLAGS_IP_CHKSUM UINT32_C(0x2) + /* + * If set to 1, the controller will not append an Ethernet CRC + * to the end of the frame. + * + * Packet must be 64B or longer when this flag is set. It is not + * useful to use this bit with any form of TX offload such as + * CSO or LSO. The intent is that the packet from the host already + * has a valid Ethernet CRC on the packet. + */ + #define TX_BD_LONG_INLINE_LFLAGS_NOCRC UINT32_C(0x4) + /* + * If set to 1, the device will record the time at which the packet + * was actually transmitted at the TX MAC. + */ + #define TX_BD_LONG_INLINE_LFLAGS_STAMP UINT32_C(0x8) + /* + * If set to 1, the controller replaces the tunnel IP checksum + * field with hardware calculated IP checksum for the IP header + * of the packet associated with this descriptor. The hardware + * updates an outer UDP checksum if it is non-zero. + */ + #define TX_BD_LONG_INLINE_LFLAGS_T_IP_CHKSUM UINT32_C(0x10) + /* + * This bit must be 0 for BDs of this type. LSO is not supported with + * inline BDs. + */ + #define TX_BD_LONG_INLINE_LFLAGS_LSO UINT32_C(0x20) + /* Since LSO is not supported with inline BDs, this bit is not used. */ + #define TX_BD_LONG_INLINE_LFLAGS_IPID_FMT UINT32_C(0x40) + /* Since LSO is not supported with inline BDs, this bit is not used. */ + #define TX_BD_LONG_INLINE_LFLAGS_T_IPID UINT32_C(0x80) + /* + * If set to '1', then the RoCE ICRC will be appended to the + * packet. Packet must be a valid RoCE format packet. + */ + #define TX_BD_LONG_INLINE_LFLAGS_ROCE_CRC UINT32_C(0x100) + /* + * If set to '1', then the FCoE CRC will be appended to the + * packet. Packet must be a valid FCoE format packet. + */ + #define TX_BD_LONG_INLINE_LFLAGS_FCOE_CRC UINT32_C(0x200) + uint16_t unused2; + uint32_t unused3; + uint16_t unused4; + /* + * This value selects a CFA action to perform on the packet. + * Set this value to zero if no CFA action is desired. + * + * This value must be valid on the first BD of a packet. + */ + uint16_t cfa_action; + /* + * This value is action meta-data that defines CFA edit operations + * that are done in addition to any action editing. + */ + uint32_t cfa_meta; + /* When key = 1, this is the VLAN tag VID value. */ + #define TX_BD_LONG_INLINE_CFA_META_VLAN_VID_MASK UINT32_C(0xfff) + #define TX_BD_LONG_INLINE_CFA_META_VLAN_VID_SFT 0 + /* When key = 1, this is the VLAN tag DE value. */ + #define TX_BD_LONG_INLINE_CFA_META_VLAN_DE UINT32_C(0x1000) + /* When key = 1, this is the VLAN tag PRI value. */ + #define TX_BD_LONG_INLINE_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000) + #define TX_BD_LONG_INLINE_CFA_META_VLAN_PRI_SFT 13 + /* When key = 1, this is the VLAN tag TPID select value. */ + #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000) + #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_SFT 16 + /* 0x88a8 */ + #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID88A8 \ + (UINT32_C(0x0) << 16) + /* 0x8100 */ + #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID8100 \ + (UINT32_C(0x1) << 16) + /* 0x9100 */ + #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9100 \ + (UINT32_C(0x2) << 16) + /* 0x9200 */ + #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9200 \ + (UINT32_C(0x3) << 16) + /* 0x9300 */ + #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9300 \ + (UINT32_C(0x4) << 16) + /* Value programmed in CFA VLANTPID register. */ + #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPIDCFG \ + (UINT32_C(0x5) << 16) + #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_LAST \ + TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPIDCFG + #define TX_BD_LONG_INLINE_CFA_META_VLAN_RESERVED_MASK \ + UINT32_C(0xff80000) + #define TX_BD_LONG_INLINE_CFA_META_VLAN_RESERVED_SFT 19 + /* + * This field identifies the type of edit to be performed + * on the packet. + * + * This value must be valid on the first BD of a packet. + */ + #define TX_BD_LONG_INLINE_CFA_META_KEY_MASK \ + UINT32_C(0xf0000000) + #define TX_BD_LONG_INLINE_CFA_META_KEY_SFT 28 + /* No editing */ + #define TX_BD_LONG_INLINE_CFA_META_KEY_NONE \ + (UINT32_C(0x0) << 28) + /* + * - meta[17:16] - TPID select value (0 = 0x8100). + * - meta[15:12] - PRI/DE value. + * - meta[11:0] - VID value. + */ + #define TX_BD_LONG_INLINE_CFA_META_KEY_VLAN_TAG \ + (UINT32_C(0x1) << 28) + #define TX_BD_LONG_INLINE_CFA_META_KEY_LAST \ + TX_BD_LONG_INLINE_CFA_META_KEY_VLAN_TAG +} __attribute__((packed)); + /* tx_bd_empty (size:128b/16B) */ struct tx_bd_empty { /* This value identifies the type of buffer descriptor. */ @@ -2121,6 +2399,7 @@ struct rx_pkt_cmpl { uint32_t rss_hash; } __attribute__((packed)); +/* Last 16 bytes of rx_pkt_cmpl. */ /* rx_pkt_cmpl_hi (size:128b/16B) */ struct rx_pkt_cmpl_hi { uint32_t flags2; @@ -2566,6 +2845,7 @@ struct rx_tpa_start_cmpl { uint32_t rss_hash; } __attribute__((packed)); +/* Last 16 bytes of rx_tpq_start_cmpl. */ /* rx_tpa_start_cmpl_hi (size:128b/16B) */ struct rx_tpa_start_cmpl_hi { uint32_t flags2; @@ -2830,6 +3110,7 @@ struct rx_tpa_end_cmpl { uint32_t tsdelta; } __attribute__((packed)); +/* Last 16 bytes of rx_tpa_end_cmpl. */ /* rx_tpa_end_cmpl_hi (size:128b/16B) */ struct rx_tpa_end_cmpl_hi { /* @@ -3153,6 +3434,9 @@ struct hwrm_async_event_cmpl { /* Port PHY configuration change */ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE \ UINT32_C(0x7) + /* Reset notification to clients */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY \ + UINT32_C(0x8) /* Function driver unloaded */ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD \ UINT32_C(0x10) @@ -3790,6 +4074,96 @@ struct hwrm_async_event_cmpl_port_phy_cfg_change { UINT32_C(0x40000) } __attribute__((packed)); +/* hwrm_async_event_cmpl_reset_notify (size:128b/16B) */ +struct hwrm_async_event_cmpl_reset_notify { + uint16_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* Notify clients of imminent reset. */ + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY \ + UINT32_C(0x8) + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY + /* Event specific data */ + uint32_t event_data2; + uint8_t opaque_v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* Indicates driver action requested */ + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_MASK \ + UINT32_C(0xff) + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_SFT \ + 0 + /* + * If set to 1, it indicates that the l2 client should + * stop sending in band traffic to Nitro. + * if set to 0, there is no change in L2 client behavior. + */ + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_STOP_TX_QUEUE \ + UINT32_C(0x1) + /* + * If set to 1, it indicates that the L2 client should + * bring down the interface. + * If set to 0, then there is no change in L2 client behavior. + */ + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN \ + UINT32_C(0x2) + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_LAST \ + HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN + /* Indicates reason for reset. */ + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK \ + UINT32_C(0xff00) + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_SFT \ + 8 + /* A management client has requested reset. */ + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MANAGEMENT_RESET_REQUEST \ + (UINT32_C(0x1) << 8) + /* A fatal firmware exception has occurred. */ + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL \ + (UINT32_C(0x2) << 8) + /* A non-fatal firmware exception has occurred. */ + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL \ + (UINT32_C(0x3) << 8) + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST \ + HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL + /* + * Minimum time before driver should attempt access - units 100ms ticks. + * Range 0-65535 + */ + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_MASK \ + UINT32_C(0xffff0000) + #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_SFT \ + 16 +} __attribute__((packed)); + /* hwrm_async_event_cmpl_func_drvr_unload (size:128b/16B) */ struct hwrm_async_event_cmpl_func_drvr_unload { uint16_t type; @@ -4285,6 +4659,13 @@ struct hwrm_async_event_cmpl_vf_cfg_change { */ #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE \ UINT32_C(0x8) + /* + * If this bit is set to 1, then the value of trusted VF enable + * was changed on this VF. + * If set to 0, then this bit should be ignored. + */ + #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE \ + UINT32_C(0x10) } __attribute__((packed)); /* hwrm_async_event_cmpl_llfc_pfc_change (size:128b/16B) */ @@ -5306,6 +5687,20 @@ struct hwrm_func_qcaps_output { #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ADMIN_PF_SUPPORTED \ UINT32_C(0x40000) /* + * If the query is for a VF, then this flag shall be ignored. + * If this query is for a PF and this flag is set to 1, then + * the PF will know that the firmware has the capability to track + * the virtual link status. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_LINK_ADMIN_STATUS_SUPPORTED \ + UINT32_C(0x80000) + /* + * If 1, then this function supports the push mode that uses + * write combine buffers and the long inline tx buffer descriptor. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WCB_PUSH_MODE \ + UINT32_C(0x100000) + /* * This value is current MAC address configured for this * function. A value of 00-00-00-00-00-00 indicates no * MAC address is currently configured. @@ -5548,6 +5943,15 @@ struct hwrm_func_qcfg_output { #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST \ UINT32_C(0x20) /* + * If the function that is being queried is a PF, then the HWRM shall + * set this field to 0 and the HWRM client shall ignore this field. + * If the function that is being queried is a VF, then the HWRM shall + * set this field to 1 if the queried VF is trusted, otherwise the HWRM + * shall set this field to 0. + */ + #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF \ + UINT32_C(0x40) + /* * This value is current MAC address configured for this * function. A value of 00-00-00-00-00-00 indicates no * MAC address is currently configured. @@ -5755,7 +6159,7 @@ struct hwrm_func_qcfg_output { */ #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_MASK \ UINT32_C(0x3) - #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SFT 0 + #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SFT 0 /* Cache Line Size 64 bytes */ #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_64 \ UINT32_C(0x0) @@ -5764,10 +6168,25 @@ struct hwrm_func_qcfg_output { UINT32_C(0x1) #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_LAST \ HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_128 + /* This value is the virtual link admin state setting. */ + #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_MASK \ + UINT32_C(0xc) + #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_SFT 2 + /* Admin link state is in forced down mode. */ + #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN \ + (UINT32_C(0x0) << 2) + /* Admin link state is in forced up mode. */ + #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_UP \ + (UINT32_C(0x1) << 2) + /* Admin link state is in auto mode - follows the physical link state. */ + #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_AUTO \ + (UINT32_C(0x2) << 2) + #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_LAST \ + HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_AUTO /* Reserved for future. */ #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_RSVD_MASK \ - UINT32_C(0xfc) - #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_RSVD_SFT 2 + UINT32_C(0xf0) + #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_RSVD_SFT 4 /* * The number of VFs that are allocated to the function. * This is valid only on the PF with SR-IOV enabled. @@ -5814,217 +6233,6 @@ struct hwrm_func_qcfg_output { uint8_t valid; } __attribute__((packed)); -/*********************** - * hwrm_func_vlan_qcfg * - ***********************/ - - -/* hwrm_func_vlan_qcfg_input (size:192b/24B) */ -struct hwrm_func_vlan_qcfg_input { - /* The HWRM command request type. */ - uint16_t req_type; - /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. - */ - uint16_t cmpl_ring; - /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. - */ - uint16_t seq_id; - /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFE - Reserved for internal processors - * * 0xFFFF - HWRM - */ - uint16_t target_id; - /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. - */ - uint64_t resp_addr; - /* - * Function ID of the function that is being - * configured. - * If set to 0xFF... (All Fs), then the configuration is - * for the requesting function. - */ - uint16_t fid; - uint8_t unused_0[6]; -} __attribute__((packed)); - -/* hwrm_func_vlan_qcfg_output (size:320b/40B) */ -struct hwrm_func_vlan_qcfg_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint8_t unused_0[7]; - /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. - */ - uint8_t valid; - /* S-TAG VLAN identifier configured for the function. */ - uint16_t stag_vid; - /* S-TAG PCP value configured for the function. */ - uint8_t stag_pcp; - uint8_t unused_1; - /* - * S-TAG TPID value configured for the function. This field is specified in - * network byte order. - */ - uint16_t stag_tpid; - /* C-TAG VLAN identifier configured for the function. */ - uint16_t ctag_vid; - /* C-TAG PCP value configured for the function. */ - uint8_t ctag_pcp; - uint8_t unused_2; - /* - * C-TAG TPID value configured for the function. This field is specified in - * network byte order. - */ - uint16_t ctag_tpid; - /* Future use. */ - uint32_t rsvd2; - /* Future use. */ - uint32_t rsvd3; - uint32_t unused_3; -} __attribute__((packed)); - -/********************** - * hwrm_func_vlan_cfg * - **********************/ - - -/* hwrm_func_vlan_cfg_input (size:384b/48B) */ -struct hwrm_func_vlan_cfg_input { - /* The HWRM command request type. */ - uint16_t req_type; - /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. - */ - uint16_t cmpl_ring; - /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. - */ - uint16_t seq_id; - /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFE - Reserved for internal processors - * * 0xFFFF - HWRM - */ - uint16_t target_id; - /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. - */ - uint64_t resp_addr; - /* - * Function ID of the function that is being - * configured. - * If set to 0xFF... (All Fs), then the configuration is - * for the requesting function. - */ - uint16_t fid; - uint8_t unused_0[2]; - uint32_t enables; - /* - * This bit must be '1' for the stag_vid field to be - * configured. - */ - #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_VID UINT32_C(0x1) - /* - * This bit must be '1' for the ctag_vid field to be - * configured. - */ - #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_VID UINT32_C(0x2) - /* - * This bit must be '1' for the stag_pcp field to be - * configured. - */ - #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_PCP UINT32_C(0x4) - /* - * This bit must be '1' for the ctag_pcp field to be - * configured. - */ - #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_PCP UINT32_C(0x8) - /* - * This bit must be '1' for the stag_tpid field to be - * configured. - */ - #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_TPID UINT32_C(0x10) - /* - * This bit must be '1' for the ctag_tpid field to be - * configured. - */ - #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_TPID UINT32_C(0x20) - /* S-TAG VLAN identifier configured for the function. */ - uint16_t stag_vid; - /* S-TAG PCP value configured for the function. */ - uint8_t stag_pcp; - uint8_t unused_1; - /* - * S-TAG TPID value configured for the function. This field is specified in - * network byte order. - */ - uint16_t stag_tpid; - /* C-TAG VLAN identifier configured for the function. */ - uint16_t ctag_vid; - /* C-TAG PCP value configured for the function. */ - uint8_t ctag_pcp; - uint8_t unused_2; - /* - * C-TAG TPID value configured for the function. This field is specified in - * network byte order. - */ - uint16_t ctag_tpid; - /* Future use. */ - uint32_t rsvd1; - /* Future use. */ - uint32_t rsvd2; - uint8_t unused_3[4]; -} __attribute__((packed)); - -/* hwrm_func_vlan_cfg_output (size:128b/16B) */ -struct hwrm_func_vlan_cfg_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint8_t unused_0[7]; - /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. - */ - uint8_t valid; -} __attribute__((packed)); - /***************** * hwrm_func_cfg * *****************/ @@ -6205,6 +6413,17 @@ struct hwrm_func_cfg_input { */ #define HWRM_FUNC_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST \ UINT32_C(0x100000) + /* + * This configuration change can be initiated by a PF driver. This + * configuration request shall be targeted to a VF. From local host + * resident HWRM clients, only the parent PF driver shall be allowed + * to initiate this change on one of its children VFs. If this bit is + * set to 1, then the VF that is being configured is requested to be + * trusted. If this bit is set to 0, then the VF that is being configured + * is requested to be not trusted. + */ + #define HWRM_FUNC_CFG_INPUT_FLAGS_TRUSTED_VF_ENABLE \ + UINT32_C(0x200000) uint32_t enables; /* * This bit must be '1' for the mtu field to be @@ -6339,6 +6558,12 @@ struct hwrm_func_cfg_input { #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX \ UINT32_C(0x200000) /* + * This bit must be '1' for the link admin state field to be + * configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_ADMIN_LINK_STATE \ + UINT32_C(0x400000) + /* * The maximum transmission unit of the function. * The HWRM should make sure that the mtu of * the function does not exceed the mtu of the physical @@ -6569,7 +6794,7 @@ struct hwrm_func_cfg_input { */ #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_MASK \ UINT32_C(0x3) - #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SFT 0 + #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SFT 0 /* Cache Line Size 64 bytes */ #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_64 \ UINT32_C(0x0) @@ -6578,10 +6803,25 @@ struct hwrm_func_cfg_input { UINT32_C(0x1) #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_LAST \ HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_128 + /* This value is the virtual link admin state setting. */ + #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_MASK \ + UINT32_C(0xc) + #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_SFT 2 + /* Admin state is forced down. */ + #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN \ + (UINT32_C(0x0) << 2) + /* Admin state is forced up. */ + #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_UP \ + (UINT32_C(0x1) << 2) + /* Admin state is in auto mode - is to follow the physical link state. */ + #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_AUTO \ + (UINT32_C(0x2) << 2) + #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_LAST \ + HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_AUTO /* Reserved for future. */ #define HWRM_FUNC_CFG_INPUT_OPTIONS_RSVD_MASK \ - UINT32_C(0xfc) - #define HWRM_FUNC_CFG_INPUT_OPTIONS_RSVD_SFT 2 + UINT32_C(0xf0) + #define HWRM_FUNC_CFG_INPUT_OPTIONS_RSVD_SFT 4 /* * The number of multicast filters that should * be reserved for this function on the RX side. @@ -6862,79 +7102,6 @@ struct hwrm_func_vf_resc_free_output { uint8_t valid; } __attribute__((packed)); -/******************************* - * hwrm_func_vf_vnic_ids_query * - *******************************/ - - -/* hwrm_func_vf_vnic_ids_query_input (size:256b/32B) */ -struct hwrm_func_vf_vnic_ids_query_input { - /* The HWRM command request type. */ - uint16_t req_type; - /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. - */ - uint16_t cmpl_ring; - /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. - */ - uint16_t seq_id; - /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFE - Reserved for internal processors - * * 0xFFFF - HWRM - */ - uint16_t target_id; - /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. - */ - uint64_t resp_addr; - /* - * This value is used to identify a Virtual Function (VF). - * The scope of VF ID is local within a PF. - */ - uint16_t vf_id; - uint8_t unused_0[2]; - /* Max number of vnic ids in vnic id table */ - uint32_t max_vnic_id_cnt; - /* This is the address for VF VNIC ID table */ - uint64_t vnic_id_tbl_addr; -} __attribute__((packed)); - -/* hwrm_func_vf_vnic_ids_query_output (size:128b/16B) */ -struct hwrm_func_vf_vnic_ids_query_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - /* - * Actual number of vnic ids - * - * Each VNIC ID is written as a 32-bit number. - */ - uint32_t vnic_id_cnt; - uint8_t unused_0[3]; - /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. - */ - uint8_t valid; -} __attribute__((packed)); - /********************** * hwrm_func_drv_rgtr * **********************/ @@ -6978,7 +7145,8 @@ struct hwrm_func_drv_rgtr_input { * If a VF driver sets this flag, it should be ignored * by the HWRM. */ - #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_ALL_MODE UINT32_C(0x1) + #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_ALL_MODE \ + UINT32_C(0x1) /* * When this bit is '1', the function is requesting none of * the requests from its children VF drivers to be @@ -6987,7 +7155,8 @@ struct hwrm_func_drv_rgtr_input { * If a VF driver sets this flag, it should be ignored * by the HWRM. */ - #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE UINT32_C(0x2) + #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE \ + UINT32_C(0x2) /* * When this bit is '1', then ver_maj_8b, ver_min_8b, ver_upd_8b * fields shall be ignored and ver_maj, ver_min, ver_upd @@ -6996,7 +7165,22 @@ struct hwrm_func_drv_rgtr_input { * fields shall be used for the driver version information and * ver_maj, ver_min, ver_upd and ver_patch shall be ignored. */ - #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_16BIT_VER_MODE UINT32_C(0x4) + #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_16BIT_VER_MODE \ + UINT32_C(0x4) + /* + * When this bit is '1', the function is indicating support of + * 64bit flow handle. The firmware that only supports 64bit flow + * handle should check this bit before allowing processing of + * HWRM_CFA_FLOW_XXX commands from the requesting function as firmware + * with 64bit flow handle support can only be compatible with drivers + * that support 64bit flow handle. The legacy drivers that don't support + * 64bit flow handle won't be able to use HWRM_CFA_FLOW_XXX commands when + * running with new firmware that only supports 64bit flow handle. The new + * firmware support 64bit flow handle returns HWRM_ERR_CODE_CMD_NOT_SUPPORTED + * status to the legacy driver when encounters these commands. + */ + #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FLOW_HANDLE_64BIT_MODE \ + UINT32_C(0x8) uint32_t enables; /* * This bit must be '1' for the os_type field to be @@ -7117,7 +7301,14 @@ struct hwrm_func_drv_rgtr_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + uint32_t flags; + /* + * When this bit is '1', it indicates that the + * HWRM_FUNC_DRV_IF_CHANGE call is supported. + */ + #define HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED \ + UINT32_C(0x1) + uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -7441,7 +7632,7 @@ struct hwrm_func_drv_qver_input { uint8_t unused_0[2]; } __attribute__((packed)); -/* hwrm_func_drv_qver_output (size:192b/24B) */ +/* hwrm_func_drv_qver_output (size:256b/32B) */ struct hwrm_func_drv_qver_output { /* The specific error status for the command. */ uint16_t error_code; @@ -7483,15 +7674,7 @@ struct hwrm_func_drv_qver_output { uint8_t ver_min_8b; /* This is the 8bit update version of the driver. */ uint8_t ver_upd_8b; - uint8_t unused_0[2]; - /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. - */ - uint8_t valid; + uint8_t unused_0[3]; /* This is the 16bit major version of the driver. */ uint16_t ver_maj; /* This is the 16bit minor version of the driver. */ @@ -7500,6 +7683,15 @@ struct hwrm_func_drv_qver_output { uint16_t ver_upd; /* This is the 16bit patch version of the driver. */ uint16_t ver_patch; + uint8_t unused_1[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; } __attribute__((packed)); /**************************** @@ -7612,117 +7804,15 @@ struct hwrm_func_resource_qcaps_output { * The number of TX rings assigned to the function cannot exceed this value. */ uint16_t max_tx_scheduler_inputs; - uint8_t unused_0[7]; - /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. - */ - uint8_t valid; -} __attribute__((packed)); - -/***************************** - * hwrm_func_vf_resource_cfg * - *****************************/ - - -/* hwrm_func_vf_resource_cfg_input (size:448b/56B) */ -struct hwrm_func_vf_resource_cfg_input { - /* The HWRM command request type. */ - uint16_t req_type; - /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. - */ - uint16_t cmpl_ring; - /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. - */ - uint16_t seq_id; - /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFE - Reserved for internal processors - * * 0xFFFF - HWRM - */ - uint16_t target_id; + uint16_t flags; /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * When this bit is '1', it indicates that VF_RESOURCE_CFG supports + * feature to reserve all minimum resources when minimum >= 1, otherwise + * returns an error. */ - uint64_t resp_addr; - /* VF ID that is being configured by PF */ - uint16_t vf_id; - /* Maximum guaranteed number of MSI-X vectors for the function */ - uint16_t max_msix; - /* Minimum guaranteed number of RSS/COS contexts */ - uint16_t min_rsscos_ctx; - /* Maximum non-guaranteed number of RSS/COS contexts */ - uint16_t max_rsscos_ctx; - /* Minimum guaranteed number of completion rings */ - uint16_t min_cmpl_rings; - /* Maximum non-guaranteed number of completion rings */ - uint16_t max_cmpl_rings; - /* Minimum guaranteed number of transmit rings */ - uint16_t min_tx_rings; - /* Maximum non-guaranteed number of transmit rings */ - uint16_t max_tx_rings; - /* Minimum guaranteed number of receive rings */ - uint16_t min_rx_rings; - /* Maximum non-guaranteed number of receive rings */ - uint16_t max_rx_rings; - /* Minimum guaranteed number of L2 contexts */ - uint16_t min_l2_ctxs; - /* Maximum non-guaranteed number of L2 contexts */ - uint16_t max_l2_ctxs; - /* Minimum guaranteed number of VNICs */ - uint16_t min_vnics; - /* Maximum non-guaranteed number of VNICs */ - uint16_t max_vnics; - /* Minimum guaranteed number of statistic contexts */ - uint16_t min_stat_ctx; - /* Maximum non-guaranteed number of statistic contexts */ - uint16_t max_stat_ctx; - /* Minimum guaranteed number of ring groups */ - uint16_t min_hw_ring_grps; - /* Maximum non-guaranteed number of ring groups */ - uint16_t max_hw_ring_grps; - uint8_t unused_0[4]; -} __attribute__((packed)); - -/* hwrm_func_vf_resource_cfg_output (size:256b/32B) */ -struct hwrm_func_vf_resource_cfg_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - /* Reserved number of RSS/COS contexts */ - uint16_t reserved_rsscos_ctx; - /* Reserved number of completion rings */ - uint16_t reserved_cmpl_rings; - /* Reserved number of transmit rings */ - uint16_t reserved_tx_rings; - /* Reserved number of receive rings */ - uint16_t reserved_rx_rings; - /* Reserved number of L2 contexts */ - uint16_t reserved_l2_ctxs; - /* Reserved number of VNICs */ - uint16_t reserved_vnics; - /* Reserved number of statistic contexts */ - uint16_t reserved_stat_ctx; - /* Reserved number of ring groups */ - uint16_t reserved_hw_ring_grps; - uint8_t unused_0[7]; + #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_FLAGS_MIN_GUARANTEED \ + UINT32_C(0x1) + uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -7769,7 +7859,7 @@ struct hwrm_func_backing_store_qcaps_input { uint64_t resp_addr; } __attribute__((packed)); -/* hwrm_func_backing_store_qcaps_output (size:512b/64B) */ +/* hwrm_func_backing_store_qcaps_output (size:576b/72B) */ struct hwrm_func_backing_store_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; @@ -7813,19 +7903,51 @@ struct hwrm_func_backing_store_qcaps_output { uint32_t stat_max_entries; /* Number of bytes that must be allocated for each context entry. */ uint16_t stat_entry_size; - /* Maximum number of TQM context entries supported per ring. */ - uint16_t tqm_max_entries_per_ring; /* Number of bytes that must be allocated for each context entry. */ uint16_t tqm_entry_size; - /* Number of bytes that must be allocated for each context entry. */ - uint16_t mrav_entry_size; + /* Minimum number of TQM context entries required per ring. */ + uint32_t tqm_min_entries_per_ring; + /* + * Maximum number of TQM context entries supported per ring. This is + * actually a recommended TQM queue size based on worst case usage of + * the TQM queue. + * + * TQM fastpath rings should be sized large enough to accommodate the + * maximum number of QPs (either L2 or RoCE, or both if shared) + * that can be enqueued to the TQM ring. + * + * TQM slowpath rings should be sized as follows: + * + * num_entries = num_vnics + num_l2_tx_rings + num_roce_qps + tqm_min_size + * + * Where: + * num_vnics is the number of VNICs allocated in the VNIC backing store + * num_l2_tx_rings is the number of L2 rings in the QP backing store + * num_roce_qps is the number of RoCE QPs in the QP backing store + * tqm_min_size is tqm_min_entries_per_ring reported by + * HWRM_FUNC_BACKING_STORE_QCAPS + * + * Note that TQM ring sizes cannot be extended while the system is + * operational. If a PF driver needs to extend a TQM ring, it needs + * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate + * the backing store. + */ + uint32_t tqm_max_entries_per_ring; /* Maximum number of MR/AV context entries supported for this function. */ uint32_t mrav_max_entries; - /* Maximum number of Timer context entries supported for this function. */ - uint32_t tim_max_entries; + /* Number of bytes that must be allocated for each context entry. */ + uint16_t mrav_entry_size; /* Number of bytes that must be allocated for each context entry. */ uint16_t tim_entry_size; - uint8_t unused_0; + /* Maximum number of Timer context entries supported for this function. */ + uint32_t tim_max_entries; + uint8_t unused_0[2]; + /* + * The number of entries specified for any TQM ring must be a + * multiple of this value to prevent any resource allocation + * limitations. + */ + uint8_t tqm_entries_multiple; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -8672,23 +8794,129 @@ struct hwrm_func_backing_store_cfg_input { uint32_t cq_num_entries; /* Number of Stats. */ uint32_t stat_num_entries; - /* Number of TQM slowpath entries. */ + /* + * Number of TQM slowpath entries. + * + * TQM slowpath rings should be sized as follows: + * + * num_entries = num_vnics + num_l2_tx_rings + num_roce_qps + tqm_min_size + * + * Where: + * num_vnics is the number of VNICs allocated in the VNIC backing store + * num_l2_tx_rings is the number of L2 rings in the QP backing store + * num_roce_qps is the number of RoCE QPs in the QP backing store + * tqm_min_size is tqm_min_entries_per_ring reported by + * HWRM_FUNC_BACKING_STORE_QCAPS + * + * Note that TQM ring sizes cannot be extended while the system is + * operational. If a PF driver needs to extend a TQM ring, it needs + * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate + * the backing store. + */ uint32_t tqm_sp_num_entries; - /* Number of TQM ring 0 entries. */ + /* + * Number of TQM ring 0 entries. + * + * TQM fastpath rings should be sized large enough to accommodate the + * maximum number of QPs (either L2 or RoCE, or both if shared) + * that can be enqueued to the TQM ring. + * + * Note that TQM ring sizes cannot be extended while the system is + * operational. If a PF driver needs to extend a TQM ring, it needs + * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate + * the backing store. + */ uint32_t tqm_ring0_num_entries; - /* Number of TQM ring 1 entries. */ + /* + * Number of TQM ring 1 entries. + * + * TQM fastpath rings should be sized large enough to accommodate the + * maximum number of QPs (either L2 or RoCE, or both if shared) + * that can be enqueued to the TQM ring. + * + * Note that TQM ring sizes cannot be extended while the system is + * operational. If a PF driver needs to extend a TQM ring, it needs + * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate + * the backing store. + */ uint32_t tqm_ring1_num_entries; - /* Number of TQM ring 2 entries. */ + /* + * Number of TQM ring 2 entries. + * + * TQM fastpath rings should be sized large enough to accommodate the + * maximum number of QPs (either L2 or RoCE, or both if shared) + * that can be enqueued to the TQM ring. + * + * Note that TQM ring sizes cannot be extended while the system is + * operational. If a PF driver needs to extend a TQM ring, it needs + * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate + * the backing store. + */ uint32_t tqm_ring2_num_entries; - /* Number of TQM ring 3 entries. */ + /* + * Number of TQM ring 3 entries. + * + * TQM fastpath rings should be sized large enough to accommodate the + * maximum number of QPs (either L2 or RoCE, or both if shared) + * that can be enqueued to the TQM ring. + * + * Note that TQM ring sizes cannot be extended while the system is + * operational. If a PF driver needs to extend a TQM ring, it needs + * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate + * the backing store. + */ uint32_t tqm_ring3_num_entries; - /* Number of TQM ring 4 entries. */ + /* + * Number of TQM ring 4 entries. + * + * TQM fastpath rings should be sized large enough to accommodate the + * maximum number of QPs (either L2 or RoCE, or both if shared) + * that can be enqueued to the TQM ring. + * + * Note that TQM ring sizes cannot be extended while the system is + * operational. If a PF driver needs to extend a TQM ring, it needs + * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate + * the backing store. + */ uint32_t tqm_ring4_num_entries; - /* Number of TQM ring 5 entries. */ + /* + * Number of TQM ring 5 entries. + * + * TQM fastpath rings should be sized large enough to accommodate the + * maximum number of QPs (either L2 or RoCE, or both if shared) + * that can be enqueued to the TQM ring. + * + * Note that TQM ring sizes cannot be extended while the system is + * operational. If a PF driver needs to extend a TQM ring, it needs + * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate + * the backing store. + */ uint32_t tqm_ring5_num_entries; - /* Number of TQM ring 6 entries. */ + /* + * Number of TQM ring 6 entries. + * + * TQM fastpath rings should be sized large enough to accommodate the + * maximum number of QPs (either L2 or RoCE, or both if shared) + * that can be enqueued to the TQM ring. + * + * Note that TQM ring sizes cannot be extended while the system is + * operational. If a PF driver needs to extend a TQM ring, it needs + * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate + * the backing store. + */ uint32_t tqm_ring6_num_entries; - /* Number of TQM ring 7 entries. */ + /* + * Number of TQM ring 7 entries. + * + * TQM fastpath rings should be sized large enough to accommodate the + * maximum number of QPs (either L2 or RoCE, or both if shared) + * that can be enqueued to the TQM ring. + * + * Note that TQM ring sizes cannot be extended while the system is + * operational. If a PF driver needs to extend a TQM ring, it needs + * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate + * the backing store. + */ uint32_t tqm_ring7_num_entries; /* Number of MR/AV entries. */ uint32_t mrav_num_entries; @@ -9638,6 +9866,633 @@ struct hwrm_func_backing_store_qcfg_output { uint8_t valid; } __attribute__((packed)); +/*********************** + * hwrm_func_vlan_qcfg * + ***********************/ + + +/* hwrm_func_vlan_qcfg_input (size:192b/24B) */ +struct hwrm_func_vlan_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFE - Reserved for internal processors + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Function ID of the function that is being + * configured. + * If set to 0xFF... (All Fs), then the configuration is + * for the requesting function. + */ + uint16_t fid; + uint8_t unused_0[6]; +} __attribute__((packed)); + +/* hwrm_func_vlan_qcfg_output (size:320b/40B) */ +struct hwrm_func_vlan_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint64_t unused_0; + /* S-TAG VLAN identifier configured for the function. */ + uint16_t stag_vid; + /* S-TAG PCP value configured for the function. */ + uint8_t stag_pcp; + uint8_t unused_1; + /* + * S-TAG TPID value configured for the function. This field is specified in + * network byte order. + */ + uint16_t stag_tpid; + /* C-TAG VLAN identifier configured for the function. */ + uint16_t ctag_vid; + /* C-TAG PCP value configured for the function. */ + uint8_t ctag_pcp; + uint8_t unused_2; + /* + * C-TAG TPID value configured for the function. This field is specified in + * network byte order. + */ + uint16_t ctag_tpid; + /* Future use. */ + uint32_t rsvd2; + /* Future use. */ + uint32_t rsvd3; + uint8_t unused_3[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __attribute__((packed)); + +/********************** + * hwrm_func_vlan_cfg * + **********************/ + + +/* hwrm_func_vlan_cfg_input (size:384b/48B) */ +struct hwrm_func_vlan_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFE - Reserved for internal processors + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Function ID of the function that is being + * configured. + * If set to 0xFF... (All Fs), then the configuration is + * for the requesting function. + */ + uint16_t fid; + uint8_t unused_0[2]; + uint32_t enables; + /* + * This bit must be '1' for the stag_vid field to be + * configured. + */ + #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_VID UINT32_C(0x1) + /* + * This bit must be '1' for the ctag_vid field to be + * configured. + */ + #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_VID UINT32_C(0x2) + /* + * This bit must be '1' for the stag_pcp field to be + * configured. + */ + #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_PCP UINT32_C(0x4) + /* + * This bit must be '1' for the ctag_pcp field to be + * configured. + */ + #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_PCP UINT32_C(0x8) + /* + * This bit must be '1' for the stag_tpid field to be + * configured. + */ + #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_TPID UINT32_C(0x10) + /* + * This bit must be '1' for the ctag_tpid field to be + * configured. + */ + #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_TPID UINT32_C(0x20) + /* S-TAG VLAN identifier configured for the function. */ + uint16_t stag_vid; + /* S-TAG PCP value configured for the function. */ + uint8_t stag_pcp; + uint8_t unused_1; + /* + * S-TAG TPID value configured for the function. This field is specified in + * network byte order. + */ + uint16_t stag_tpid; + /* C-TAG VLAN identifier configured for the function. */ + uint16_t ctag_vid; + /* C-TAG PCP value configured for the function. */ + uint8_t ctag_pcp; + uint8_t unused_2; + /* + * C-TAG TPID value configured for the function. This field is specified in + * network byte order. + */ + uint16_t ctag_tpid; + /* Future use. */ + uint32_t rsvd1; + /* Future use. */ + uint32_t rsvd2; + uint8_t unused_3[4]; +} __attribute__((packed)); + +/* hwrm_func_vlan_cfg_output (size:128b/16B) */ +struct hwrm_func_vlan_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __attribute__((packed)); + +/******************************* + * hwrm_func_vf_vnic_ids_query * + *******************************/ + + +/* hwrm_func_vf_vnic_ids_query_input (size:256b/32B) */ +struct hwrm_func_vf_vnic_ids_query_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFE - Reserved for internal processors + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * This value is used to identify a Virtual Function (VF). + * The scope of VF ID is local within a PF. + */ + uint16_t vf_id; + uint8_t unused_0[2]; + /* Max number of vnic ids in vnic id table */ + uint32_t max_vnic_id_cnt; + /* This is the address for VF VNIC ID table */ + uint64_t vnic_id_tbl_addr; +} __attribute__((packed)); + +/* hwrm_func_vf_vnic_ids_query_output (size:128b/16B) */ +struct hwrm_func_vf_vnic_ids_query_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * Actual number of vnic ids + * + * Each VNIC ID is written as a 32-bit number. + */ + uint32_t vnic_id_cnt; + uint8_t unused_0[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __attribute__((packed)); + +/*********************** + * hwrm_func_vf_bw_cfg * + ***********************/ + + +/* hwrm_func_vf_bw_cfg_input (size:960b/120B) */ +struct hwrm_func_vf_bw_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFE - Reserved for internal processors + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * The number of VF functions that are being configured. + * The cmd space allows up to 50 VFs' BW to be configured with one cmd. + */ + uint16_t num_vfs; + uint16_t unused[3]; + /* These 16-bit fields contain the VF fid and the rate scale percentage. */ + uint16_t vfn[48]; + /* The physical VF id the adjustment will be made to. */ + #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_VFID_MASK UINT32_C(0xfff) + #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_VFID_SFT 0 + /* + * This field configures the rate scale percentage of the VF as specified + * by the physical VF id. + */ + #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_MASK UINT32_C(0xf000) + #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_SFT 12 + /* 0% of the max tx rate */ + #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_0 \ + (UINT32_C(0x0) << 12) + /* 6.66% of the max tx rate */ + #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_6_66 \ + (UINT32_C(0x1) << 12) + /* 13.33% of the max tx rate */ + #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_13_33 \ + (UINT32_C(0x2) << 12) + /* 20% of the max tx rate */ + #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_20 \ + (UINT32_C(0x3) << 12) + /* 26.66% of the max tx rate */ + #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_26_66 \ + (UINT32_C(0x4) << 12) + /* 33% of the max tx rate */ + #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_33_33 \ + (UINT32_C(0x5) << 12) + /* 40% of the max tx rate */ + #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_40 \ + (UINT32_C(0x6) << 12) + /* 46.66% of the max tx rate */ + #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_46_66 \ + (UINT32_C(0x7) << 12) + /* 53.33% of the max tx rate */ + #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_53_33 \ + (UINT32_C(0x8) << 12) + /* 60% of the max tx rate */ + #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_60 \ + (UINT32_C(0x9) << 12) + /* 66.66% of the max tx rate */ + #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_66_66 \ + (UINT32_C(0xa) << 12) + /* 53.33% of the max tx rate */ + #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_73_33 \ + (UINT32_C(0xb) << 12) + /* 80% of the max tx rate */ + #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_80 \ + (UINT32_C(0xc) << 12) + /* 86.66% of the max tx rate */ + #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_86_66 \ + (UINT32_C(0xd) << 12) + /* 93.33% of the max tx rate */ + #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_93_33 \ + (UINT32_C(0xe) << 12) + /* 100% of the max tx rate */ + #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_100 \ + (UINT32_C(0xf) << 12) + #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_LAST \ + HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_100 +} __attribute__((packed)); + +/* hwrm_func_vf_bw_cfg_output (size:128b/16B) */ +struct hwrm_func_vf_bw_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __attribute__((packed)); + +/************************ + * hwrm_func_vf_bw_qcfg * + ************************/ + + +/* hwrm_func_vf_bw_qcfg_input (size:960b/120B) */ +struct hwrm_func_vf_bw_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFE - Reserved for internal processors + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * The number of VF functions that are being queried. + * The inline response space allows the host to query up to 50 VFs' + * rate scale percentage + */ + uint16_t num_vfs; + uint16_t unused[3]; + /* These 16-bit fields contain the VF fid */ + uint16_t vfn[48]; + /* The physical VF id of interest */ + #define HWRM_FUNC_VF_BW_QCFG_INPUT_VFN_VFID_MASK UINT32_C(0xfff) + #define HWRM_FUNC_VF_BW_QCFG_INPUT_VFN_VFID_SFT 0 +} __attribute__((packed)); + +/* hwrm_func_vf_bw_qcfg_output (size:960b/120B) */ +struct hwrm_func_vf_bw_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * The number of VF functions that are being queried. + * The inline response space allows the host to query up to 50 VFs' rate + * scale percentage + */ + uint16_t num_vfs; + uint16_t unused[3]; + /* These 16-bit fields contain the VF fid and the rate scale percentage. */ + uint16_t vfn[48]; + /* The physical VF id the adjustment will be made to. */ + #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_VFID_MASK UINT32_C(0xfff) + #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_VFID_SFT 0 + /* + * This field configures the rate scale percentage of the VF as specified + * by the physical VF id. + */ + #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_MASK UINT32_C(0xf000) + #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_SFT 12 + /* 0% of the max tx rate */ + #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_0 \ + (UINT32_C(0x0) << 12) + /* 6.66% of the max tx rate */ + #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_6_66 \ + (UINT32_C(0x1) << 12) + /* 13.33% of the max tx rate */ + #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_13_33 \ + (UINT32_C(0x2) << 12) + /* 20% of the max tx rate */ + #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_20 \ + (UINT32_C(0x3) << 12) + /* 26.66% of the max tx rate */ + #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_26_66 \ + (UINT32_C(0x4) << 12) + /* 33% of the max tx rate */ + #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_33_33 \ + (UINT32_C(0x5) << 12) + /* 40% of the max tx rate */ + #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_40 \ + (UINT32_C(0x6) << 12) + /* 46.66% of the max tx rate */ + #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_46_66 \ + (UINT32_C(0x7) << 12) + /* 53.33% of the max tx rate */ + #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_53_33 \ + (UINT32_C(0x8) << 12) + /* 60% of the max tx rate */ + #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_60 \ + (UINT32_C(0x9) << 12) + /* 66.66% of the max tx rate */ + #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_66_66 \ + (UINT32_C(0xa) << 12) + /* 53.33% of the max tx rate */ + #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_73_33 \ + (UINT32_C(0xb) << 12) + /* 80% of the max tx rate */ + #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_80 \ + (UINT32_C(0xc) << 12) + /* 86.66% of the max tx rate */ + #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_86_66 \ + (UINT32_C(0xd) << 12) + /* 93.33% of the max tx rate */ + #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_93_33 \ + (UINT32_C(0xe) << 12) + /* 100% of the max tx rate */ + #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_100 \ + (UINT32_C(0xf) << 12) + #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_LAST \ + HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_100 + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __attribute__((packed)); + +/*************************** + * hwrm_func_drv_if_change * + ***************************/ + + +/* hwrm_func_drv_if_change_input (size:192b/24B) */ +struct hwrm_func_drv_if_change_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFE - Reserved for internal processors + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t flags; + /* + * When this bit is '1', the function driver is indicating + * that the IF state is changing to UP state. The call should + * be made at the beginning of the driver's open call before + * resources are allocated. After making the call, the driver + * should check the response to see if any resources may have + * changed (see the response below). If the driver fails + * the open call, the driver should make this call again with + * this bit cleared to indicate that the IF state is not UP. + * During the driver's close call when the IF state is changing + * to DOWN, the driver should make this call with the bit cleared + * after all resources have been freed. + */ + #define HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP UINT32_C(0x1) + uint32_t unused; +} __attribute__((packed)); + +/* hwrm_func_drv_if_change_output (size:128b/16B) */ +struct hwrm_func_drv_if_change_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint32_t flags; + /* + * When this bit is '1', it indicates that the resources reserved + * for this function may have changed. The driver should check + * resource capabilities and reserve resources again before + * allocating resources. + */ + #define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_RESC_CHANGE \ + UINT32_C(0x1) + uint8_t unused_0[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __attribute__((packed)); + /********************* * hwrm_port_phy_cfg * *********************/ @@ -11916,6 +12771,362 @@ struct hwrm_port_mac_ptp_qcfg_output { uint8_t valid; } __attribute__((packed)); +/* Port Tx Statistics Formats */ +/* tx_port_stats (size:3264b/408B) */ +struct tx_port_stats { + /* Total Number of 64 Bytes frames transmitted */ + uint64_t tx_64b_frames; + /* Total Number of 65-127 Bytes frames transmitted */ + uint64_t tx_65b_127b_frames; + /* Total Number of 128-255 Bytes frames transmitted */ + uint64_t tx_128b_255b_frames; + /* Total Number of 256-511 Bytes frames transmitted */ + uint64_t tx_256b_511b_frames; + /* Total Number of 512-1023 Bytes frames transmitted */ + uint64_t tx_512b_1023b_frames; + /* Total Number of 1024-1518 Bytes frames transmitted */ + uint64_t tx_1024b_1518b_frames; + /* + * Total Number of each good VLAN (exludes FCS errors) + * frame transmitted which is 1519 to 1522 bytes in length + * inclusive (excluding framing bits but including FCS bytes). + */ + uint64_t tx_good_vlan_frames; + /* Total Number of 1519-2047 Bytes frames transmitted */ + uint64_t tx_1519b_2047b_frames; + /* Total Number of 2048-4095 Bytes frames transmitted */ + uint64_t tx_2048b_4095b_frames; + /* Total Number of 4096-9216 Bytes frames transmitted */ + uint64_t tx_4096b_9216b_frames; + /* Total Number of 9217-16383 Bytes frames transmitted */ + uint64_t tx_9217b_16383b_frames; + /* Total Number of good frames transmitted */ + uint64_t tx_good_frames; + /* Total Number of frames transmitted */ + uint64_t tx_total_frames; + /* Total number of unicast frames transmitted */ + uint64_t tx_ucast_frames; + /* Total number of multicast frames transmitted */ + uint64_t tx_mcast_frames; + /* Total number of broadcast frames transmitted */ + uint64_t tx_bcast_frames; + /* Total number of PAUSE control frames transmitted */ + uint64_t tx_pause_frames; + /* + * Total number of PFC/per-priority PAUSE + * control frames transmitted + */ + uint64_t tx_pfc_frames; + /* Total number of jabber frames transmitted */ + uint64_t tx_jabber_frames; + /* Total number of frames transmitted with FCS error */ + uint64_t tx_fcs_err_frames; + /* Total number of control frames transmitted */ + uint64_t tx_control_frames; + /* Total number of over-sized frames transmitted */ + uint64_t tx_oversz_frames; + /* Total number of frames with single deferral */ + uint64_t tx_single_dfrl_frames; + /* Total number of frames with multiple deferrals */ + uint64_t tx_multi_dfrl_frames; + /* Total number of frames with single collision */ + uint64_t tx_single_coll_frames; + /* Total number of frames with multiple collisions */ + uint64_t tx_multi_coll_frames; + /* Total number of frames with late collisions */ + uint64_t tx_late_coll_frames; + /* Total number of frames with excessive collisions */ + uint64_t tx_excessive_coll_frames; + /* Total number of fragmented frames transmitted */ + uint64_t tx_frag_frames; + /* Total number of transmit errors */ + uint64_t tx_err; + /* Total number of single VLAN tagged frames transmitted */ + uint64_t tx_tagged_frames; + /* Total number of double VLAN tagged frames transmitted */ + uint64_t tx_dbl_tagged_frames; + /* Total number of runt frames transmitted */ + uint64_t tx_runt_frames; + /* Total number of TX FIFO under runs */ + uint64_t tx_fifo_underruns; + /* + * Total number of PFC frames with PFC enabled bit for + * Pri 0 transmitted + */ + uint64_t tx_pfc_ena_frames_pri0; + /* + * Total number of PFC frames with PFC enabled bit for + * Pri 1 transmitted + */ + uint64_t tx_pfc_ena_frames_pri1; + /* + * Total number of PFC frames with PFC enabled bit for + * Pri 2 transmitted + */ + uint64_t tx_pfc_ena_frames_pri2; + /* + * Total number of PFC frames with PFC enabled bit for + * Pri 3 transmitted + */ + uint64_t tx_pfc_ena_frames_pri3; + /* + * Total number of PFC frames with PFC enabled bit for + * Pri 4 transmitted + */ + uint64_t tx_pfc_ena_frames_pri4; + /* + * Total number of PFC frames with PFC enabled bit for + * Pri 5 transmitted + */ + uint64_t tx_pfc_ena_frames_pri5; + /* + * Total number of PFC frames with PFC enabled bit for + * Pri 6 transmitted + */ + uint64_t tx_pfc_ena_frames_pri6; + /* + * Total number of PFC frames with PFC enabled bit for + * Pri 7 transmitted + */ + uint64_t tx_pfc_ena_frames_pri7; + /* Total number of EEE LPI Events on TX */ + uint64_t tx_eee_lpi_events; + /* EEE LPI Duration Counter on TX */ + uint64_t tx_eee_lpi_duration; + /* + * Total number of Link Level Flow Control (LLFC) messages + * transmitted + */ + uint64_t tx_llfc_logical_msgs; + /* Total number of HCFC messages transmitted */ + uint64_t tx_hcfc_msgs; + /* Total number of TX collisions */ + uint64_t tx_total_collisions; + /* Total number of transmitted bytes */ + uint64_t tx_bytes; + /* Total number of end-to-end HOL frames */ + uint64_t tx_xthol_frames; + /* Total Tx Drops per Port reported by STATS block */ + uint64_t tx_stat_discard; + /* Total Tx Error Drops per Port reported by STATS block */ + uint64_t tx_stat_error; +} __attribute__((packed)); + +/* Port Rx Statistics Formats */ +/* rx_port_stats (size:4224b/528B) */ +struct rx_port_stats { + /* Total Number of 64 Bytes frames received */ + uint64_t rx_64b_frames; + /* Total Number of 65-127 Bytes frames received */ + uint64_t rx_65b_127b_frames; + /* Total Number of 128-255 Bytes frames received */ + uint64_t rx_128b_255b_frames; + /* Total Number of 256-511 Bytes frames received */ + uint64_t rx_256b_511b_frames; + /* Total Number of 512-1023 Bytes frames received */ + uint64_t rx_512b_1023b_frames; + /* Total Number of 1024-1518 Bytes frames received */ + uint64_t rx_1024b_1518b_frames; + /* + * Total Number of each good VLAN (exludes FCS errors) + * frame received which is 1519 to 1522 bytes in length + * inclusive (excluding framing bits but including FCS bytes). + */ + uint64_t rx_good_vlan_frames; + /* Total Number of 1519-2047 Bytes frames received */ + uint64_t rx_1519b_2047b_frames; + /* Total Number of 2048-4095 Bytes frames received */ + uint64_t rx_2048b_4095b_frames; + /* Total Number of 4096-9216 Bytes frames received */ + uint64_t rx_4096b_9216b_frames; + /* Total Number of 9217-16383 Bytes frames received */ + uint64_t rx_9217b_16383b_frames; + /* Total number of frames received */ + uint64_t rx_total_frames; + /* Total number of unicast frames received */ + uint64_t rx_ucast_frames; + /* Total number of multicast frames received */ + uint64_t rx_mcast_frames; + /* Total number of broadcast frames received */ + uint64_t rx_bcast_frames; + /* Total number of received frames with FCS error */ + uint64_t rx_fcs_err_frames; + /* Total number of control frames received */ + uint64_t rx_ctrl_frames; + /* Total number of PAUSE frames received */ + uint64_t rx_pause_frames; + /* Total number of PFC frames received */ + uint64_t rx_pfc_frames; + /* + * Total number of frames received with an unsupported + * opcode + */ + uint64_t rx_unsupported_opcode_frames; + /* + * Total number of frames received with an unsupported + * DA for pause and PFC + */ + uint64_t rx_unsupported_da_pausepfc_frames; + /* Total number of frames received with an unsupported SA */ + uint64_t rx_wrong_sa_frames; + /* Total number of received packets with alignment error */ + uint64_t rx_align_err_frames; + /* Total number of received frames with out-of-range length */ + uint64_t rx_oor_len_frames; + /* Total number of received frames with error termination */ + uint64_t rx_code_err_frames; + /* + * Total number of received frames with a false carrier is + * detected during idle, as defined by RX_ER samples active + * and RXD is 0xE. The event is reported along with the + * statistics generated on the next received frame. Only + * one false carrier condition can be detected and logged + * between frames. + * + * Carrier event, valid for 10M/100M speed modes only. + */ + uint64_t rx_false_carrier_frames; + /* Total number of over-sized frames received */ + uint64_t rx_ovrsz_frames; + /* Total number of jabber packets received */ + uint64_t rx_jbr_frames; + /* Total number of received frames with MTU error */ + uint64_t rx_mtu_err_frames; + /* Total number of received frames with CRC match */ + uint64_t rx_match_crc_frames; + /* Total number of frames received promiscuously */ + uint64_t rx_promiscuous_frames; + /* + * Total number of received frames with one or two VLAN + * tags + */ + uint64_t rx_tagged_frames; + /* Total number of received frames with two VLAN tags */ + uint64_t rx_double_tagged_frames; + /* Total number of truncated frames received */ + uint64_t rx_trunc_frames; + /* Total number of good frames (without errors) received */ + uint64_t rx_good_frames; + /* + * Total number of received PFC frames with transition from + * XON to XOFF on Pri 0 + */ + uint64_t rx_pfc_xon2xoff_frames_pri0; + /* + * Total number of received PFC frames with transition from + * XON to XOFF on Pri 1 + */ + uint64_t rx_pfc_xon2xoff_frames_pri1; + /* + * Total number of received PFC frames with transition from + * XON to XOFF on Pri 2 + */ + uint64_t rx_pfc_xon2xoff_frames_pri2; + /* + * Total number of received PFC frames with transition from + * XON to XOFF on Pri 3 + */ + uint64_t rx_pfc_xon2xoff_frames_pri3; + /* + * Total number of received PFC frames with transition from + * XON to XOFF on Pri 4 + */ + uint64_t rx_pfc_xon2xoff_frames_pri4; + /* + * Total number of received PFC frames with transition from + * XON to XOFF on Pri 5 + */ + uint64_t rx_pfc_xon2xoff_frames_pri5; + /* + * Total number of received PFC frames with transition from + * XON to XOFF on Pri 6 + */ + uint64_t rx_pfc_xon2xoff_frames_pri6; + /* + * Total number of received PFC frames with transition from + * XON to XOFF on Pri 7 + */ + uint64_t rx_pfc_xon2xoff_frames_pri7; + /* + * Total number of received PFC frames with PFC enabled + * bit for Pri 0 + */ + uint64_t rx_pfc_ena_frames_pri0; + /* + * Total number of received PFC frames with PFC enabled + * bit for Pri 1 + */ + uint64_t rx_pfc_ena_frames_pri1; + /* + * Total number of received PFC frames with PFC enabled + * bit for Pri 2 + */ + uint64_t rx_pfc_ena_frames_pri2; + /* + * Total number of received PFC frames with PFC enabled + * bit for Pri 3 + */ + uint64_t rx_pfc_ena_frames_pri3; + /* + * Total number of received PFC frames with PFC enabled + * bit for Pri 4 + */ + uint64_t rx_pfc_ena_frames_pri4; + /* + * Total number of received PFC frames with PFC enabled + * bit for Pri 5 + */ + uint64_t rx_pfc_ena_frames_pri5; + /* + * Total number of received PFC frames with PFC enabled + * bit for Pri 6 + */ + uint64_t rx_pfc_ena_frames_pri6; + /* + * Total number of received PFC frames with PFC enabled + * bit for Pri 7 + */ + uint64_t rx_pfc_ena_frames_pri7; + /* Total Number of frames received with SCH CRC error */ + uint64_t rx_sch_crc_err_frames; + /* Total Number of under-sized frames received */ + uint64_t rx_undrsz_frames; + /* Total Number of fragmented frames received */ + uint64_t rx_frag_frames; + /* Total number of RX EEE LPI Events */ + uint64_t rx_eee_lpi_events; + /* EEE LPI Duration Counter on RX */ + uint64_t rx_eee_lpi_duration; + /* + * Total number of physical type Link Level Flow Control + * (LLFC) messages received + */ + uint64_t rx_llfc_physical_msgs; + /* + * Total number of logical type Link Level Flow Control + * (LLFC) messages received + */ + uint64_t rx_llfc_logical_msgs; + /* + * Total number of logical type Link Level Flow Control + * (LLFC) messages received with CRC error + */ + uint64_t rx_llfc_msgs_with_crc_err; + /* Total number of HCFC messages received */ + uint64_t rx_hcfc_msgs; + /* Total number of HCFC messages received with CRC error */ + uint64_t rx_hcfc_msgs_with_crc_err; + /* Total number of received bytes */ + uint64_t rx_bytes; + /* Total number of bytes received in runt frames */ + uint64_t rx_runt_bytes; + /* Total number of runt frames received */ + uint64_t rx_runt_frames; + /* Total Rx Discards per Port reported by STATS block */ + uint64_t rx_stat_discard; + uint64_t rx_stat_err; +} __attribute__((packed)); + /******************** * hwrm_port_qstats * ********************/ @@ -11990,6 +13201,154 @@ struct hwrm_port_qstats_output { uint8_t valid; } __attribute__((packed)); +/* Port Tx Statistics extended Formats */ +/* tx_port_stats_ext (size:2048b/256B) */ +struct tx_port_stats_ext { + /* Total number of tx bytes count on cos queue 0 */ + uint64_t tx_bytes_cos0; + /* Total number of tx bytes count on cos queue 1 */ + uint64_t tx_bytes_cos1; + /* Total number of tx bytes count on cos queue 2 */ + uint64_t tx_bytes_cos2; + /* Total number of tx bytes count on cos queue 3 */ + uint64_t tx_bytes_cos3; + /* Total number of tx bytes count on cos queue 4 */ + uint64_t tx_bytes_cos4; + /* Total number of tx bytes count on cos queue 5 */ + uint64_t tx_bytes_cos5; + /* Total number of tx bytes count on cos queue 6 */ + uint64_t tx_bytes_cos6; + /* Total number of tx bytes count on cos queue 7 */ + uint64_t tx_bytes_cos7; + /* Total number of tx packets count on cos queue 0 */ + uint64_t tx_packets_cos0; + /* Total number of tx packets count on cos queue 1 */ + uint64_t tx_packets_cos1; + /* Total number of tx packets count on cos queue 2 */ + uint64_t tx_packets_cos2; + /* Total number of tx packets count on cos queue 3 */ + uint64_t tx_packets_cos3; + /* Total number of tx packets count on cos queue 4 */ + uint64_t tx_packets_cos4; + /* Total number of tx packets count on cos queue 5 */ + uint64_t tx_packets_cos5; + /* Total number of tx packets count on cos queue 6 */ + uint64_t tx_packets_cos6; + /* Total number of tx packets count on cos queue 7 */ + uint64_t tx_packets_cos7; + /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 0 */ + uint64_t pfc_pri0_tx_duration_us; + /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 0 */ + uint64_t pfc_pri0_tx_transitions; + /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 1 */ + uint64_t pfc_pri1_tx_duration_us; + /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 1 */ + uint64_t pfc_pri1_tx_transitions; + /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 2 */ + uint64_t pfc_pri2_tx_duration_us; + /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 2 */ + uint64_t pfc_pri2_tx_transitions; + /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 3 */ + uint64_t pfc_pri3_tx_duration_us; + /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 3 */ + uint64_t pfc_pri3_tx_transitions; + /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 4 */ + uint64_t pfc_pri4_tx_duration_us; + /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 4 */ + uint64_t pfc_pri4_tx_transitions; + /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 5 */ + uint64_t pfc_pri5_tx_duration_us; + /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 5 */ + uint64_t pfc_pri5_tx_transitions; + /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 6 */ + uint64_t pfc_pri6_tx_duration_us; + /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 6 */ + uint64_t pfc_pri6_tx_transitions; + /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 7 */ + uint64_t pfc_pri7_tx_duration_us; + /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 7 */ + uint64_t pfc_pri7_tx_transitions; +} __attribute__((packed)); + +/* Port Rx Statistics extended Formats */ +/* rx_port_stats_ext (size:2368b/296B) */ +struct rx_port_stats_ext { + /* Number of times link state changed to down */ + uint64_t link_down_events; + /* Number of times the idle rings with pause bit are found */ + uint64_t continuous_pause_events; + /* Number of times the active rings pause bit resumed back */ + uint64_t resume_pause_events; + /* Number of times, the ROCE cos queue PFC is disabled to avoid pause flood/burst */ + uint64_t continuous_roce_pause_events; + /* Number of times, the ROCE cos queue PFC is enabled back */ + uint64_t resume_roce_pause_events; + /* Total number of rx bytes count on cos queue 0 */ + uint64_t rx_bytes_cos0; + /* Total number of rx bytes count on cos queue 1 */ + uint64_t rx_bytes_cos1; + /* Total number of rx bytes count on cos queue 2 */ + uint64_t rx_bytes_cos2; + /* Total number of rx bytes count on cos queue 3 */ + uint64_t rx_bytes_cos3; + /* Total number of rx bytes count on cos queue 4 */ + uint64_t rx_bytes_cos4; + /* Total number of rx bytes count on cos queue 5 */ + uint64_t rx_bytes_cos5; + /* Total number of rx bytes count on cos queue 6 */ + uint64_t rx_bytes_cos6; + /* Total number of rx bytes count on cos queue 7 */ + uint64_t rx_bytes_cos7; + /* Total number of rx packets count on cos queue 0 */ + uint64_t rx_packets_cos0; + /* Total number of rx packets count on cos queue 1 */ + uint64_t rx_packets_cos1; + /* Total number of rx packets count on cos queue 2 */ + uint64_t rx_packets_cos2; + /* Total number of rx packets count on cos queue 3 */ + uint64_t rx_packets_cos3; + /* Total number of rx packets count on cos queue 4 */ + uint64_t rx_packets_cos4; + /* Total number of rx packets count on cos queue 5 */ + uint64_t rx_packets_cos5; + /* Total number of rx packets count on cos queue 6 */ + uint64_t rx_packets_cos6; + /* Total number of rx packets count on cos queue 7 */ + uint64_t rx_packets_cos7; + /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 0 */ + uint64_t pfc_pri0_rx_duration_us; + /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 0 */ + uint64_t pfc_pri0_rx_transitions; + /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 1 */ + uint64_t pfc_pri1_rx_duration_us; + /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 1 */ + uint64_t pfc_pri1_rx_transitions; + /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 2 */ + uint64_t pfc_pri2_rx_duration_us; + /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 2 */ + uint64_t pfc_pri2_rx_transitions; + /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 3 */ + uint64_t pfc_pri3_rx_duration_us; + /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 3 */ + uint64_t pfc_pri3_rx_transitions; + /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 4 */ + uint64_t pfc_pri4_rx_duration_us; + /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 4 */ + uint64_t pfc_pri4_rx_transitions; + /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 5 */ + uint64_t pfc_pri5_rx_duration_us; + /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 5 */ + uint64_t pfc_pri5_rx_transitions; + /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 6 */ + uint64_t pfc_pri6_rx_duration_us; + /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 6 */ + uint64_t pfc_pri6_rx_transitions; + /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 7 */ + uint64_t pfc_pri7_rx_duration_us; + /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 7 */ + uint64_t pfc_pri7_rx_transitions; +} __attribute__((packed)); + /************************ * hwrm_port_qstats_ext * ************************/ @@ -12063,7 +13422,15 @@ struct hwrm_port_qstats_ext_output { uint16_t tx_stat_size; /* The size of RX port statistics block in bytes. */ uint16_t rx_stat_size; - uint8_t unused_0[3]; + /* Total number of active cos queues available. */ + uint16_t total_active_cos_queues; + uint8_t flags; + /* + * If set to 1, then this field indicates that clear + * roce specific counters is supported. + */ + #define HWRM_PORT_QSTATS_EXT_OUTPUT_FLAGS_CLEAR_ROCE_COUNTERS_SUPPORTED \ + UINT32_C(0x1) /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -12187,68 +13554,22 @@ struct hwrm_port_clr_stats_input { uint64_t resp_addr; /* Port ID of port that is being queried. */ uint16_t port_id; - uint8_t unused_0[6]; -} __attribute__((packed)); - -/* hwrm_port_clr_stats_output (size:128b/16B) */ -struct hwrm_port_clr_stats_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint8_t unused_0[7]; - /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. - */ - uint8_t valid; -} __attribute__((packed)); - -/**************************** - * hwrm_port_lpbk_clr_stats * - ****************************/ - - -/* hwrm_port_lpbk_clr_stats_input (size:128b/16B) */ -struct hwrm_port_lpbk_clr_stats_input { - /* The HWRM command request type. */ - uint16_t req_type; - /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. - */ - uint16_t cmpl_ring; - /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. - */ - uint16_t seq_id; - /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFE - Reserved for internal processors - * * 0xFFFF - HWRM - */ - uint16_t target_id; + uint8_t flags; /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * If set to 1, then this field indicates clear the following RoCE + * specific counters. + * RoCE associated TX/RX cos counters + * CNP associated TX/RX cos counters + * RoCE/CNP specific TX/RX flow counters + * Firmware will determine the RoCE/CNP cos queue based on qos profile. + * This flag is honored only when RoCE is enabled on that port. */ - uint64_t resp_addr; + #define HWRM_PORT_CLR_STATS_INPUT_FLAGS_ROCE_COUNTERS UINT32_C(0x1) + uint8_t unused_0[5]; } __attribute__((packed)); -/* hwrm_port_lpbk_clr_stats_output (size:128b/16B) */ -struct hwrm_port_lpbk_clr_stats_output { +/* hwrm_port_clr_stats_output (size:128b/16B) */ +struct hwrm_port_clr_stats_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -12268,83 +13589,6 @@ struct hwrm_port_lpbk_clr_stats_output { uint8_t valid; } __attribute__((packed)); -/********************** - * hwrm_port_ts_query * - **********************/ - - -/* hwrm_port_ts_query_input (size:192b/24B) */ -struct hwrm_port_ts_query_input { - /* The HWRM command request type. */ - uint16_t req_type; - /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. - */ - uint16_t cmpl_ring; - /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. - */ - uint16_t seq_id; - /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFE - Reserved for internal processors - * * 0xFFFF - HWRM - */ - uint16_t target_id; - /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. - */ - uint64_t resp_addr; - uint32_t flags; - /* - * Enumeration denoting the RX, TX type of the resource. - * This enumeration is used for resources that are similar for both - * TX and RX paths of the chip. - */ - #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH UINT32_C(0x1) - /* tx path */ - #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX UINT32_C(0x0) - /* rx path */ - #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX UINT32_C(0x1) - #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_LAST \ - HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX - /* Port ID of port that is being queried. */ - uint16_t port_id; - uint8_t unused_0[2]; -} __attribute__((packed)); - -/* hwrm_port_ts_query_output (size:192b/24B) */ -struct hwrm_port_ts_query_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - /* Timestamp value of PTP message captured. */ - uint64_t ptp_msg_ts; - /* Sequence ID of the PTP message captured. */ - uint16_t ptp_msg_seqid; - uint8_t unused_0[5]; - /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. - */ - uint8_t valid; -} __attribute__((packed)); - /*********************** * hwrm_port_phy_qcaps * ***********************/ @@ -12593,172 +13837,6 @@ struct hwrm_port_phy_qcaps_output { #define HWRM_PORT_PHY_QCAPS_OUTPUT_VALID_SFT 24 } __attribute__((packed)); -/*************************** - * hwrm_port_phy_i2c_write * - ***************************/ - - -/* hwrm_port_phy_i2c_write_input (size:832b/104B) */ -struct hwrm_port_phy_i2c_write_input { - /* The HWRM command request type. */ - uint16_t req_type; - /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. - */ - uint16_t cmpl_ring; - /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. - */ - uint16_t seq_id; - /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFE - Reserved for internal processors - * * 0xFFFF - HWRM - */ - uint16_t target_id; - /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. - */ - uint64_t resp_addr; - uint32_t flags; - uint32_t enables; - /* - * This bit must be '1' for the page_offset field to be - * configured. - */ - #define HWRM_PORT_PHY_I2C_WRITE_INPUT_ENABLES_PAGE_OFFSET \ - UINT32_C(0x1) - /* Port ID of port. */ - uint16_t port_id; - /* 8-bit I2C slave address. */ - uint8_t i2c_slave_addr; - uint8_t unused_0; - /* The page number that is being accessed over I2C. */ - uint16_t page_number; - /* Offset within the page that is being accessed over I2C. */ - uint16_t page_offset; - /* - * Length of data to write, in bytes starting at the offset - * specified above. If the offset is not specified, then - * the data shall be written from the beginning of the page. - */ - uint8_t data_length; - uint8_t unused_1[7]; - /* Up to 64B of data. */ - uint32_t data[16]; -} __attribute__((packed)); - -/* hwrm_port_phy_i2c_write_output (size:128b/16B) */ -struct hwrm_port_phy_i2c_write_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint8_t unused_0[7]; - /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. - */ - uint8_t valid; -} __attribute__((packed)); - -/************************** - * hwrm_port_phy_i2c_read * - **************************/ - - -/* hwrm_port_phy_i2c_read_input (size:320b/40B) */ -struct hwrm_port_phy_i2c_read_input { - /* The HWRM command request type. */ - uint16_t req_type; - /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. - */ - uint16_t cmpl_ring; - /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. - */ - uint16_t seq_id; - /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFE - Reserved for internal processors - * * 0xFFFF - HWRM - */ - uint16_t target_id; - /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. - */ - uint64_t resp_addr; - uint32_t flags; - uint32_t enables; - /* - * This bit must be '1' for the page_offset field to be - * configured. - */ - #define HWRM_PORT_PHY_I2C_READ_INPUT_ENABLES_PAGE_OFFSET \ - UINT32_C(0x1) - /* Port ID of port. */ - uint16_t port_id; - /* 8-bit I2C slave address. */ - uint8_t i2c_slave_addr; - uint8_t unused_0; - /* The page number that is being accessed over I2C. */ - uint16_t page_number; - /* Offset within the page that is being accessed over I2C. */ - uint16_t page_offset; - /* - * Length of data to read, in bytes starting at the offset - * specified above. If the offset is not specified, then - * the data shall be read from the beginning of the page. - */ - uint8_t data_length; - uint8_t unused_1[7]; -} __attribute__((packed)); - -/* hwrm_port_phy_i2c_read_output (size:640b/80B) */ -struct hwrm_port_phy_i2c_read_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - /* Up to 64B of data. */ - uint32_t data[16]; - uint8_t unused_0[7]; - /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. - */ - uint8_t valid; -} __attribute__((packed)); - /********************* * hwrm_port_led_cfg * *********************/ @@ -17127,247 +18205,6 @@ struct hwrm_queue_cos2bw_cfg_output { uint8_t valid; } __attribute__((packed)); -/************************* - * hwrm_queue_dscp_qcaps * - *************************/ - - -/* hwrm_queue_dscp_qcaps_input (size:192b/24B) */ -struct hwrm_queue_dscp_qcaps_input { - /* The HWRM command request type. */ - uint16_t req_type; - /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. - */ - uint16_t cmpl_ring; - /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. - */ - uint16_t seq_id; - /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFE - Reserved for internal processors - * * 0xFFFF - HWRM - */ - uint16_t target_id; - /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. - */ - uint64_t resp_addr; - /* - * Port ID of port for which the table is being configured. - * The HWRM needs to check whether this function is allowed - * to configure pri2cos mapping on this port. - */ - uint8_t port_id; - uint8_t unused_0[7]; -} __attribute__((packed)); - -/* hwrm_queue_dscp_qcaps_output (size:128b/16B) */ -struct hwrm_queue_dscp_qcaps_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - /* The number of bits provided by the hardware for the DSCP value. */ - uint8_t num_dscp_bits; - uint8_t unused_0; - /* Max number of DSCP-MASK-PRI entries supported. */ - uint16_t max_entries; - uint8_t unused_1[3]; - /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. - */ - uint8_t valid; -} __attribute__((packed)); - -/**************************** - * hwrm_queue_dscp2pri_qcfg * - ****************************/ - - -/* hwrm_queue_dscp2pri_qcfg_input (size:256b/32B) */ -struct hwrm_queue_dscp2pri_qcfg_input { - /* The HWRM command request type. */ - uint16_t req_type; - /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. - */ - uint16_t cmpl_ring; - /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. - */ - uint16_t seq_id; - /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFE - Reserved for internal processors - * * 0xFFFF - HWRM - */ - uint16_t target_id; - /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. - */ - uint64_t resp_addr; - /* - * This is the host address where the 24-bits DSCP-MASK-PRI - * tuple(s) will be copied to. - */ - uint64_t dest_data_addr; - /* - * Port ID of port for which the table is being configured. - * The HWRM needs to check whether this function is allowed - * to configure pri2cos mapping on this port. - */ - uint8_t port_id; - uint8_t unused_0; - /* Size of the buffer pointed to by dest_data_addr. */ - uint16_t dest_data_buffer_size; - uint8_t unused_1[4]; -} __attribute__((packed)); - -/* hwrm_queue_dscp2pri_qcfg_output (size:128b/16B) */ -struct hwrm_queue_dscp2pri_qcfg_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - /* - * A count of the number of DSCP-MASK-PRI tuple(s) pointed to - * by the dest_data_addr. - */ - uint16_t entry_cnt; - /* - * This is the default PRI which un-initialized DSCP values are - * mapped to. - */ - uint8_t default_pri; - uint8_t unused_0[4]; - /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. - */ - uint8_t valid; -} __attribute__((packed)); - -/*************************** - * hwrm_queue_dscp2pri_cfg * - ***************************/ - - -/* hwrm_queue_dscp2pri_cfg_input (size:320b/40B) */ -struct hwrm_queue_dscp2pri_cfg_input { - /* The HWRM command request type. */ - uint16_t req_type; - /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. - */ - uint16_t cmpl_ring; - /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. - */ - uint16_t seq_id; - /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFE - Reserved for internal processors - * * 0xFFFF - HWRM - */ - uint16_t target_id; - /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. - */ - uint64_t resp_addr; - /* - * This is the host address where the 24-bits DSCP-MASK-PRI tuple - * will be copied from. - */ - uint64_t src_data_addr; - uint32_t flags; - /* use_hw_default_pri is 1 b */ - #define HWRM_QUEUE_DSCP2PRI_CFG_INPUT_FLAGS_USE_HW_DEFAULT_PRI \ - UINT32_C(0x1) - uint32_t enables; - /* - * This bit must be '1' for the default_pri field to be - * configured. - */ - #define HWRM_QUEUE_DSCP2PRI_CFG_INPUT_ENABLES_DEFAULT_PRI \ - UINT32_C(0x1) - /* - * Port ID of port for which the table is being configured. - * The HWRM needs to check whether this function is allowed - * to configure pri2cos mapping on this port. - */ - uint8_t port_id; - /* - * This is the default PRI which un-initialized DSCP values will be - * mapped to. - */ - uint8_t default_pri; - /* - * A count of the number of DSCP-MASK-PRI tuple(s) in the data pointed - * to by src_data_addr. - */ - uint16_t entry_cnt; - uint8_t unused_0[4]; -} __attribute__((packed)); - -/* hwrm_queue_dscp2pri_cfg_output (size:128b/16B) */ -struct hwrm_queue_dscp2pri_cfg_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint8_t unused_0[7]; - /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. - */ - uint8_t valid; -} __attribute__((packed)); - /******************* * hwrm_vnic_alloc * *******************/ @@ -18182,177 +19019,6 @@ struct hwrm_vnic_tpa_cfg_output { uint8_t valid; } __attribute__((packed)); -/********************** - * hwrm_vnic_tpa_qcfg * - **********************/ - - -/* hwrm_vnic_tpa_qcfg_input (size:192b/24B) */ -struct hwrm_vnic_tpa_qcfg_input { - /* The HWRM command request type. */ - uint16_t req_type; - /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. - */ - uint16_t cmpl_ring; - /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. - */ - uint16_t seq_id; - /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFE - Reserved for internal processors - * * 0xFFFF - HWRM - */ - uint16_t target_id; - /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. - */ - uint64_t resp_addr; - /* Logical vnic ID */ - uint16_t vnic_id; - uint8_t unused_0[6]; -} __attribute__((packed)); - -/* hwrm_vnic_tpa_qcfg_output (size:256b/32B) */ -struct hwrm_vnic_tpa_qcfg_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint32_t flags; - /* - * When this bit is '1', the VNIC is configured to - * perform transparent packet aggregation (TPA) of - * non-tunneled TCP packets. - */ - #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_TPA \ - UINT32_C(0x1) - /* - * When this bit is '1', the VNIC is configured to - * perform transparent packet aggregation (TPA) of - * tunneled TCP packets. - */ - #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_ENCAP_TPA \ - UINT32_C(0x2) - /* - * When this bit is '1', the VNIC is configured to - * perform transparent packet aggregation (TPA) according - * to Windows Receive Segment Coalescing (RSC) rules. - */ - #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_RSC_WND_UPDATE \ - UINT32_C(0x4) - /* - * When this bit is '1', the VNIC is configured to - * perform transparent packet aggregation (TPA) according - * to Linux Generic Receive Offload (GRO) rules. - */ - #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_GRO \ - UINT32_C(0x8) - /* - * When this bit is '1', the VNIC is configured to - * perform transparent packet aggregation (TPA) for TCP - * packets with IP ECN set to non-zero. - */ - #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_AGG_WITH_ECN \ - UINT32_C(0x10) - /* - * When this bit is '1', the VNIC is configured to - * perform transparent packet aggregation (TPA) for - * GRE tunneled TCP packets only if all packets have the - * same GRE sequence. - */ - #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ \ - UINT32_C(0x20) - /* - * When this bit is '1' and the GRO mode is enabled, - * the VNIC is configured to - * perform transparent packet aggregation (TPA) for - * TCP/IPv4 packets with consecutively increasing IPIDs. - * In other words, the last packet that is being - * aggregated to an already existing aggregation context - * shall have IPID 1 more than the IPID of the last packet - * that was aggregated in that aggregation context. - */ - #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_GRO_IPID_CHECK \ - UINT32_C(0x40) - /* - * When this bit is '1' and the GRO mode is enabled, - * the VNIC is configured to - * perform transparent packet aggregation (TPA) for - * TCP packets with the same TTL (IPv4) or Hop limit (IPv6) - * value. - */ - #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_GRO_TTL_CHECK \ - UINT32_C(0x80) - /* - * This is the maximum number of TCP segments that can - * be aggregated (unit is Log2). Max value is 31. - */ - uint16_t max_agg_segs; - /* 1 segment */ - #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_1 UINT32_C(0x0) - /* 2 segments */ - #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_2 UINT32_C(0x1) - /* 4 segments */ - #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_4 UINT32_C(0x2) - /* 8 segments */ - #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_8 UINT32_C(0x3) - /* Any segment size larger than this is not valid */ - #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_MAX UINT32_C(0x1f) - #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_LAST \ - HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_MAX - /* - * This is the maximum number of aggregations this VNIC is - * allowed (unit is Log2). Max value is 7 - */ - uint16_t max_aggs; - /* 1 aggregation */ - #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_1 UINT32_C(0x0) - /* 2 aggregations */ - #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_2 UINT32_C(0x1) - /* 4 aggregations */ - #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_4 UINT32_C(0x2) - /* 8 aggregations */ - #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_8 UINT32_C(0x3) - /* 16 aggregations */ - #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_16 UINT32_C(0x4) - /* Any aggregation size larger than this is not valid */ - #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_MAX UINT32_C(0x7) - #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_LAST \ - HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_MAX - /* - * This is the maximum amount of time allowed for - * an aggregation context to complete after it was initiated. - */ - uint32_t max_agg_timer; - /* - * This is the minimum amount of payload length required to - * start an aggregation context. - */ - uint32_t min_agg_len; - uint8_t unused_0[7]; - /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. - */ - uint8_t valid; -} __attribute__((packed)); - /********************* * hwrm_vnic_rss_cfg * *********************/ @@ -19060,7 +19726,7 @@ struct hwrm_vnic_rss_cos_lb_ctx_free_output { *******************/ -/* hwrm_ring_alloc_input (size:640b/80B) */ +/* hwrm_ring_alloc_input (size:704b/88B) */ struct hwrm_ring_alloc_input { /* The HWRM command request type. */ uint16_t req_type; @@ -19142,7 +19808,18 @@ struct hwrm_ring_alloc_input { #define HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ UINT32_C(0x5) #define HWRM_RING_ALLOC_INPUT_RING_TYPE_LAST \ HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ - uint8_t unused_0[3]; + uint8_t unused_0; + /* Ring allocation flags. */ + uint16_t flags; + /* + * For Rx rings, the incoming packet data can be placed at either + * a 0B or 2B offset from the start of the Rx packet buffer. When + * '1', the received packet will be padded with 2B of zeros at the + * front of the packet. Note that this flag is only used for + * Rx rings and is ignored for all other rings included Rx + * Aggregation rings. + */ + #define HWRM_RING_ALLOC_INPUT_FLAGS_RX_SOP_PAD UINT32_C(0x1) /* * This value is a pointer to the page table for the * Ring. @@ -19347,6 +20024,13 @@ struct hwrm_ring_alloc_input { #define HWRM_RING_ALLOC_INPUT_INT_MODE_LAST \ HWRM_RING_ALLOC_INPUT_INT_MODE_POLL uint8_t unused_4[3]; + /* + * The cq_handle is specified when allocating a completion ring. For + * devices that support NQs, this cq_handle will be included in the + * NQE to specify which CQ should be read to retrieve the completion + * record. + */ + uint64_t cq_handle; } __attribute__((packed)); /* hwrm_ring_alloc_output (size:128b/16B) */ @@ -19454,6 +20138,228 @@ struct hwrm_ring_free_output { uint8_t valid; } __attribute__((packed)); +/******************* + * hwrm_ring_reset * + *******************/ + + +/* hwrm_ring_reset_input (size:192b/24B) */ +struct hwrm_ring_reset_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFE - Reserved for internal processors + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Ring Type. */ + uint8_t ring_type; + /* L2 Completion Ring (CR) */ + #define HWRM_RING_RESET_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0) + /* TX Ring (TR) */ + #define HWRM_RING_RESET_INPUT_RING_TYPE_TX UINT32_C(0x1) + /* RX Ring (RR) */ + #define HWRM_RING_RESET_INPUT_RING_TYPE_RX UINT32_C(0x2) + /* RoCE Notification Completion Ring (ROCE_CR) */ + #define HWRM_RING_RESET_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3) + #define HWRM_RING_RESET_INPUT_RING_TYPE_LAST \ + HWRM_RING_RESET_INPUT_RING_TYPE_ROCE_CMPL + uint8_t unused_0; + /* Physical number of the ring. */ + uint16_t ring_id; + uint8_t unused_1[4]; +} __attribute__((packed)); + +/* hwrm_ring_reset_output (size:128b/16B) */ +struct hwrm_ring_reset_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __attribute__((packed)); + +/************************** + * hwrm_ring_aggint_qcaps * + **************************/ + + +/* hwrm_ring_aggint_qcaps_input (size:128b/16B) */ +struct hwrm_ring_aggint_qcaps_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFE - Reserved for internal processors + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; +} __attribute__((packed)); + +/* hwrm_ring_aggint_qcaps_output (size:384b/48B) */ +struct hwrm_ring_aggint_qcaps_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint32_t cmpl_params; + /* + * When this bit is set to '1', int_lat_tmr_min can be configured + * on completion rings. + */ + #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_INT_LAT_TMR_MIN \ + UINT32_C(0x1) + /* + * When this bit is set to '1', int_lat_tmr_max can be configured + * on completion rings. + */ + #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_INT_LAT_TMR_MAX \ + UINT32_C(0x2) + /* + * When this bit is set to '1', timer_reset can be enabled + * on completion rings. + */ + #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_TIMER_RESET \ + UINT32_C(0x4) + /* + * When this bit is set to '1', ring_idle can be enabled + * on completion rings. + */ + #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_RING_IDLE \ + UINT32_C(0x8) + /* + * When this bit is set to '1', num_cmpl_dma_aggr can be configured + * on completion rings. + */ + #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_DMA_AGGR \ + UINT32_C(0x10) + /* + * When this bit is set to '1', num_cmpl_dma_aggr_during_int can be configured + * on completion rings. + */ + #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT \ + UINT32_C(0x20) + /* + * When this bit is set to '1', cmpl_aggr_dma_tmr can be configured + * on completion rings. + */ + #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_CMPL_AGGR_DMA_TMR \ + UINT32_C(0x40) + /* + * When this bit is set to '1', cmpl_aggr_dma_tmr_during_int can be configured + * on completion rings. + */ + #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT \ + UINT32_C(0x80) + /* + * When this bit is set to '1', num_cmpl_aggr_int can be configured + * on completion rings. + */ + #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_AGGR_INT \ + UINT32_C(0x100) + uint32_t nq_params; + /* + * When this bit is set to '1', int_lat_tmr_min can be configured + * on notification queues. + */ + #define HWRM_RING_AGGINT_QCAPS_OUTPUT_NQ_PARAMS_INT_LAT_TMR_MIN \ + UINT32_C(0x1) + /* Minimum value for num_cmpl_dma_aggr */ + uint16_t num_cmpl_dma_aggr_min; + /* Maximum value for num_cmpl_dma_aggr */ + uint16_t num_cmpl_dma_aggr_max; + /* Minimum value for num_cmpl_dma_aggr_during_int */ + uint16_t num_cmpl_dma_aggr_during_int_min; + /* Maximum value for num_cmpl_dma_aggr_during_int */ + uint16_t num_cmpl_dma_aggr_during_int_max; + /* Minimum value for cmpl_aggr_dma_tmr */ + uint16_t cmpl_aggr_dma_tmr_min; + /* Maximum value for cmpl_aggr_dma_tmr */ + uint16_t cmpl_aggr_dma_tmr_max; + /* Minimum value for cmpl_aggr_dma_tmr_during_int */ + uint16_t cmpl_aggr_dma_tmr_during_int_min; + /* Maximum value for cmpl_aggr_dma_tmr_during_int */ + uint16_t cmpl_aggr_dma_tmr_during_int_max; + /* Minimum value for int_lat_tmr_min */ + uint16_t int_lat_tmr_min_min; + /* Maximum value for int_lat_tmr_min */ + uint16_t int_lat_tmr_min_max; + /* Minimum value for int_lat_tmr_max */ + uint16_t int_lat_tmr_max_min; + /* Maximum value for int_lat_tmr_max */ + uint16_t int_lat_tmr_max_max; + /* Minimum value for num_cmpl_aggr_int */ + uint16_t num_cmpl_aggr_int_min; + /* Maximum value for num_cmpl_aggr_int */ + uint16_t num_cmpl_aggr_int_max; + /* The units for timer parameters, in nanoseconds. */ + uint16_t timer_units; + uint8_t unused_0[1]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __attribute__((packed)); + /************************************** * hwrm_ring_cmpl_ring_qaggint_params * **************************************/ @@ -19716,79 +20622,6 @@ struct hwrm_ring_cmpl_ring_cfg_aggint_params_output { uint8_t valid; } __attribute__((packed)); -/******************* - * hwrm_ring_reset * - *******************/ - - -/* hwrm_ring_reset_input (size:192b/24B) */ -struct hwrm_ring_reset_input { - /* The HWRM command request type. */ - uint16_t req_type; - /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. - */ - uint16_t cmpl_ring; - /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. - */ - uint16_t seq_id; - /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFE - Reserved for internal processors - * * 0xFFFF - HWRM - */ - uint16_t target_id; - /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. - */ - uint64_t resp_addr; - /* Ring Type. */ - uint8_t ring_type; - /* L2 Completion Ring (CR) */ - #define HWRM_RING_RESET_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0) - /* TX Ring (TR) */ - #define HWRM_RING_RESET_INPUT_RING_TYPE_TX UINT32_C(0x1) - /* RX Ring (RR) */ - #define HWRM_RING_RESET_INPUT_RING_TYPE_RX UINT32_C(0x2) - /* RoCE Notification Completion Ring (ROCE_CR) */ - #define HWRM_RING_RESET_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3) - #define HWRM_RING_RESET_INPUT_RING_TYPE_LAST \ - HWRM_RING_RESET_INPUT_RING_TYPE_ROCE_CMPL - uint8_t unused_0; - /* Physical number of the ring. */ - uint16_t ring_id; - uint8_t unused_1[4]; -} __attribute__((packed)); - -/* hwrm_ring_reset_output (size:128b/16B) */ -struct hwrm_ring_reset_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint8_t unused_0[7]; - /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. - */ - uint8_t valid; -} __attribute__((packed)); - /*********************** * hwrm_ring_grp_alloc * ***********************/ @@ -20000,6 +20833,24 @@ struct hwrm_cfa_l2_filter_alloc_input { */ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST \ UINT32_C(0x8) + /* + * Enumeration denoting NO_ROCE_L2 to support old drivers. + * New driver L2 for only L2 traffic, ROCE for roce and l2 traffic + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_MASK \ + UINT32_C(0x30) + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_SFT 4 + /* To support old drivers */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_NO_ROCE_L2 \ + (UINT32_C(0x0) << 4) + /* Only L2 traffic */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_L2 \ + (UINT32_C(0x1) << 4) + /* Roce & L2 traffic */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_ROCE \ + (UINT32_C(0x2) << 4) + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_LAST \ + HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_ROCE uint32_t enables; /* * This bit must be '1' for the l2_addr field to be @@ -20419,18 +21270,40 @@ struct hwrm_cfa_l2_filter_cfg_input { * This enumeration is used for resources that are similar for both * TX and RX paths of the chip. */ - #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH UINT32_C(0x1) + #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH \ + UINT32_C(0x1) /* tx path */ - #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0) + #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_TX \ + UINT32_C(0x0) /* rx path */ - #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1) + #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX \ + UINT32_C(0x1) #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_LAST \ HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX /* * Setting of this flag indicates drop action. If this flag is not set, * then it should be considered accept action. */ - #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_DROP UINT32_C(0x2) + #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_DROP \ + UINT32_C(0x2) + /* + * Enumeration denoting NO_ROCE_L2 to support old drivers. + * New driver L2 for only L2 traffic, ROCE for roce and l2 traffic + */ + #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_MASK \ + UINT32_C(0xc) + #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_SFT 2 + /* To support old drivers */ + #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_NO_ROCE_L2 \ + (UINT32_C(0x0) << 2) + /* Only L2 traffic */ + #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_L2 \ + (UINT32_C(0x1) << 2) + /* Roce & L2 traffic */ + #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_ROCE \ + (UINT32_C(0x2) << 2) + #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_LAST \ + HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_ROCE uint32_t enables; /* * This bit must be '1' for the dst_id field to be @@ -21532,7 +22405,7 @@ struct hwrm_vxlan_ipv6_hdr { uint32_t dest_ip_addr[4]; } __attribute__((packed)); -/* hwrm_cfa_encap_data_vxlan (size:576b/72B) */ +/* hwrm_cfa_encap_data_vxlan (size:640b/80B) */ struct hwrm_cfa_encap_data_vxlan { /* Source MAC address. */ uint8_t src_mac_addr[6]; @@ -21568,6 +22441,13 @@ struct hwrm_cfa_encap_data_vxlan { uint16_t dst_port; /* VXLAN Network Identifier. */ uint32_t vni; + /* 3 bytes VXLAN header reserve fields from 1st dword of the VXLAN header. */ + uint8_t hdr_rsvd0[3]; + /* 1 byte VXLAN header reserve field from 2nd dword of the VXLAN header. */ + uint8_t hdr_rsvd1; + /* VXLAN header flags field. */ + uint8_t hdr_flags; + uint8_t unused[3]; } __attribute__((packed)); /******************************* @@ -21634,8 +22514,11 @@ struct hwrm_cfa_encap_record_alloc_input { /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE \ UINT32_C(0x8) + /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ + #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_V4 \ + UINT32_C(0x9) #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_LAST \ - HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE + HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_V4 uint8_t unused_0[3]; /* This value is encap data used for the given encap type. */ uint32_t encap_data[20]; @@ -22703,922 +23586,6 @@ struct hwrm_cfa_em_flow_free_output { uint8_t valid; } __attribute__((packed)); -/************************ - * hwrm_cfa_em_flow_cfg * - ************************/ - - -/* hwrm_cfa_em_flow_cfg_input (size:384b/48B) */ -struct hwrm_cfa_em_flow_cfg_input { - /* The HWRM command request type. */ - uint16_t req_type; - /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. - */ - uint16_t cmpl_ring; - /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. - */ - uint16_t seq_id; - /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFE - Reserved for internal processors - * * 0xFFFF - HWRM - */ - uint16_t target_id; - /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. - */ - uint64_t resp_addr; - uint32_t enables; - /* - * This bit must be '1' for the new_dst_id field to be - * configured. - */ - #define HWRM_CFA_EM_FLOW_CFG_INPUT_ENABLES_NEW_DST_ID \ - UINT32_C(0x1) - /* - * This bit must be '1' for the new_mirror_vnic_id field to be - * configured. - */ - #define HWRM_CFA_EM_FLOW_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID \ - UINT32_C(0x2) - /* - * This bit must be '1' for the new_meter_instance_id field to be - * configured. - */ - #define HWRM_CFA_EM_FLOW_CFG_INPUT_ENABLES_NEW_METER_INSTANCE_ID \ - UINT32_C(0x4) - uint8_t unused_0[4]; - /* This value is an opaque id into CFA data structures. */ - uint64_t em_filter_id; - /* - * If set, this value shall represent the new - * Logical VNIC ID of the destination VNIC for the RX - * path and network port id of the destination port for - * the TX path. - */ - uint32_t new_dst_id; - /* - * New Logical VNIC ID of the VNIC where traffic is - * mirrored. - */ - uint32_t new_mirror_vnic_id; - /* - * New meter to attach to the flow. Specifying the - * invalid instance ID is used to remove any existing - * meter from the flow. - */ - uint16_t new_meter_instance_id; - /* - * A value of 0xfff is considered invalid and implies the - * instance is not configured. - */ - #define HWRM_CFA_EM_FLOW_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID \ - UINT32_C(0xffff) - #define HWRM_CFA_EM_FLOW_CFG_INPUT_NEW_METER_INSTANCE_ID_LAST \ - HWRM_CFA_EM_FLOW_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID - uint8_t unused_1[6]; -} __attribute__((packed)); - -/* hwrm_cfa_em_flow_cfg_output (size:128b/16B) */ -struct hwrm_cfa_em_flow_cfg_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint8_t unused_0[7]; - /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. - */ - uint8_t valid; -} __attribute__((packed)); - -/******************************** - * hwrm_cfa_meter_profile_alloc * - ********************************/ - - -/* hwrm_cfa_meter_profile_alloc_input (size:320b/40B) */ -struct hwrm_cfa_meter_profile_alloc_input { - /* The HWRM command request type. */ - uint16_t req_type; - /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. - */ - uint16_t cmpl_ring; - /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. - */ - uint16_t seq_id; - /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFE - Reserved for internal processors - * * 0xFFFF - HWRM - */ - uint16_t target_id; - /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. - */ - uint64_t resp_addr; - uint8_t flags; - /* - * Enumeration denoting the RX, TX type of the resource. - * This enumeration is used for resources that are similar for both - * TX and RX paths of the chip. - */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1) - /* tx path */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_TX \ - UINT32_C(0x0) - /* rx path */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX \ - UINT32_C(0x1) - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_LAST \ - HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX - /* The meter algorithm type. */ - uint8_t meter_type; - /* RFC 2697 (srTCM) */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2697 \ - UINT32_C(0x0) - /* RFC 2698 (trTCM) */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2698 \ - UINT32_C(0x1) - /* RFC 4115 (trTCM) */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115 \ - UINT32_C(0x2) - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_LAST \ - HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115 - /* - * This field is reserved for the future use. - * It shall be set to 0. - */ - uint16_t reserved1; - /* - * This field is reserved for the future use. - * It shall be set to 0. - */ - uint32_t reserved2; - /* A meter rate specified in bytes-per-second. */ - uint32_t commit_rate; - /* The bandwidth value. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_SFT \ - 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_LAST \ - HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT \ - 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \ - HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID - /* A meter burst size specified in bytes. */ - uint32_t commit_burst; - /* The bandwidth value. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_SFT \ - 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_LAST \ - HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT \ - 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \ - HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID - /* A meter rate specified in bytes-per-second. */ - uint32_t excess_peak_rate; - /* The bandwidth value. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT \ - 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_LAST \ - HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT \ - 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \ - HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID - /* A meter burst size specified in bytes. */ - uint32_t excess_peak_burst; - /* The bandwidth value. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT \ - 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_LAST \ - HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT \ - 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST \ - HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID -} __attribute__((packed)); - -/* hwrm_cfa_meter_profile_alloc_output (size:128b/16B) */ -struct hwrm_cfa_meter_profile_alloc_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - /* This value identifies a meter profile in CFA. */ - uint16_t meter_profile_id; - /* - * A value of 0xfff is considered invalid and implies the - * profile is not configured. - */ - #define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID \ - UINT32_C(0xffff) - #define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_LAST \ - HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID - uint8_t unused_0[5]; - /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. - */ - uint8_t valid; -} __attribute__((packed)); - -/******************************* - * hwrm_cfa_meter_profile_free * - *******************************/ - - -/* hwrm_cfa_meter_profile_free_input (size:192b/24B) */ -struct hwrm_cfa_meter_profile_free_input { - /* The HWRM command request type. */ - uint16_t req_type; - /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. - */ - uint16_t cmpl_ring; - /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. - */ - uint16_t seq_id; - /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFE - Reserved for internal processors - * * 0xFFFF - HWRM - */ - uint16_t target_id; - /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. - */ - uint64_t resp_addr; - uint8_t flags; - /* - * Enumeration denoting the RX, TX type of the resource. - * This enumeration is used for resources that are similar for both - * TX and RX paths of the chip. - */ - #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1) - /* tx path */ - #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_TX \ - UINT32_C(0x0) - /* rx path */ - #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX \ - UINT32_C(0x1) - #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_LAST \ - HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX - uint8_t unused_0; - /* This value identifies a meter profile in CFA. */ - uint16_t meter_profile_id; - /* - * A value of 0xfff is considered invalid and implies the - * profile is not configured. - */ - #define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID \ - UINT32_C(0xffff) - #define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_LAST \ - HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID - uint8_t unused_1[4]; -} __attribute__((packed)); - -/* hwrm_cfa_meter_profile_free_output (size:128b/16B) */ -struct hwrm_cfa_meter_profile_free_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint8_t unused_0[7]; - /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. - */ - uint8_t valid; -} __attribute__((packed)); - -/****************************** - * hwrm_cfa_meter_profile_cfg * - ******************************/ - - -/* hwrm_cfa_meter_profile_cfg_input (size:320b/40B) */ -struct hwrm_cfa_meter_profile_cfg_input { - /* The HWRM command request type. */ - uint16_t req_type; - /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. - */ - uint16_t cmpl_ring; - /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. - */ - uint16_t seq_id; - /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFE - Reserved for internal processors - * * 0xFFFF - HWRM - */ - uint16_t target_id; - /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. - */ - uint64_t resp_addr; - uint8_t flags; - /* - * Enumeration denoting the RX, TX type of the resource. - * This enumeration is used for resources that are similar for both - * TX and RX paths of the chip. - */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH UINT32_C(0x1) - /* tx path */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0) - /* rx path */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_LAST \ - HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX - /* The meter algorithm type. */ - uint8_t meter_type; - /* RFC 2697 (srTCM) */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2697 \ - UINT32_C(0x0) - /* RFC 2698 (trTCM) */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2698 \ - UINT32_C(0x1) - /* RFC 4115 (trTCM) */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115 \ - UINT32_C(0x2) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_LAST \ - HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115 - /* This value identifies a meter profile in CFA. */ - uint16_t meter_profile_id; - /* - * A value of 0xfff is considered invalid and implies the - * profile is not configured. - */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID \ - UINT32_C(0xffff) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_LAST \ - HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID - /* - * This field is reserved for the future use. - * It shall be set to 0. - */ - uint32_t reserved; - /* A meter rate specified in bytes-per-second. */ - uint32_t commit_rate; - /* The bandwidth value. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_SFT \ - 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_LAST \ - HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT \ - 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \ - HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID - /* A meter burst size specified in bytes. */ - uint32_t commit_burst; - /* The bandwidth value. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_SFT \ - 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_LAST \ - HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT \ - 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \ - HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID - /* A meter rate specified in bytes-per-second. */ - uint32_t excess_peak_rate; - /* The bandwidth value. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT \ - 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_LAST \ - HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT \ - 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \ - HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID - /* A meter burst size specified in bytes. */ - uint32_t excess_peak_burst; - /* The bandwidth value. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT \ - 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_LAST \ - HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT \ - 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST \ - HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID -} __attribute__((packed)); - -/* hwrm_cfa_meter_profile_cfg_output (size:128b/16B) */ -struct hwrm_cfa_meter_profile_cfg_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint8_t unused_0[7]; - /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. - */ - uint8_t valid; -} __attribute__((packed)); - -/********************************* - * hwrm_cfa_meter_instance_alloc * - *********************************/ - - -/* hwrm_cfa_meter_instance_alloc_input (size:192b/24B) */ -struct hwrm_cfa_meter_instance_alloc_input { - /* The HWRM command request type. */ - uint16_t req_type; - /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. - */ - uint16_t cmpl_ring; - /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. - */ - uint16_t seq_id; - /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFE - Reserved for internal processors - * * 0xFFFF - HWRM - */ - uint16_t target_id; - /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. - */ - uint64_t resp_addr; - uint8_t flags; - /* - * Enumeration denoting the RX, TX type of the resource. - * This enumeration is used for resources that are similar for both - * TX and RX paths of the chip. - */ - #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH \ - UINT32_C(0x1) - /* tx path */ - #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_TX \ - UINT32_C(0x0) - /* rx path */ - #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX \ - UINT32_C(0x1) - #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_LAST \ - HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX - uint8_t unused_0; - /* This value identifies a meter profile in CFA. */ - uint16_t meter_profile_id; - /* - * A value of 0xfff is considered invalid and implies the - * profile is not configured. - */ - #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID \ - UINT32_C(0xffff) - #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_LAST \ - HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID - uint8_t unused_1[4]; -} __attribute__((packed)); - -/* hwrm_cfa_meter_instance_alloc_output (size:128b/16B) */ -struct hwrm_cfa_meter_instance_alloc_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - /* This value identifies a meter instance in CFA. */ - uint16_t meter_instance_id; - /* - * A value of 0xfff is considered invalid and implies the - * instance is not configured. - */ - #define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID \ - UINT32_C(0xffff) - #define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_LAST \ - HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID - uint8_t unused_0[5]; - /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. - */ - uint8_t valid; -} __attribute__((packed)); - -/******************************** - * hwrm_cfa_meter_instance_free * - ********************************/ - - -/* hwrm_cfa_meter_instance_free_input (size:192b/24B) */ -struct hwrm_cfa_meter_instance_free_input { - /* The HWRM command request type. */ - uint16_t req_type; - /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. - */ - uint16_t cmpl_ring; - /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. - */ - uint16_t seq_id; - /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFE - Reserved for internal processors - * * 0xFFFF - HWRM - */ - uint16_t target_id; - /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. - */ - uint64_t resp_addr; - uint8_t flags; - /* - * Enumeration denoting the RX, TX type of the resource. - * This enumeration is used for resources that are similar for both - * TX and RX paths of the chip. - */ - #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1) - /* tx path */ - #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_TX \ - UINT32_C(0x0) - /* rx path */ - #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX \ - UINT32_C(0x1) - #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_LAST \ - HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX - uint8_t unused_0; - /* This value identifies a meter instance in CFA. */ - uint16_t meter_instance_id; - /* - * A value of 0xfff is considered invalid and implies the - * instance is not configured. - */ - #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID \ - UINT32_C(0xffff) - #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_LAST \ - HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID - uint8_t unused_1[4]; -} __attribute__((packed)); - -/* hwrm_cfa_meter_instance_free_output (size:128b/16B) */ -struct hwrm_cfa_meter_instance_free_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint8_t unused_0[7]; - /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. - */ - uint8_t valid; -} __attribute__((packed)); - /******************************* * hwrm_cfa_decap_filter_alloc * *******************************/ @@ -24030,10 +23997,12 @@ struct hwrm_cfa_flow_alloc_input { uint64_t resp_addr; uint16_t flags; /* tunnel is 1 b */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_TUNNEL UINT32_C(0x1) + #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_TUNNEL \ + UINT32_C(0x1) /* num_vlan is 2 b */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_MASK UINT32_C(0x6) - #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_SFT 1 + #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_MASK \ + UINT32_C(0x6) + #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_SFT 1 /* no tags */ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_NONE \ (UINT32_C(0x0) << 1) @@ -24046,8 +24015,9 @@ struct hwrm_cfa_flow_alloc_input { #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_LAST \ HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO /* Enumeration denoting the Flow Type. */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_MASK UINT32_C(0x38) - #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_SFT 3 + #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_MASK \ + UINT32_C(0x38) + #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_SFT 3 /* L2 flow */ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_L2 \ (UINT32_C(0x0) << 3) @@ -24060,6 +24030,29 @@ struct hwrm_cfa_flow_alloc_input { #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_LAST \ HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6 /* + * when set to 1, indicates TX flow offload for function specified in src_fid and + * the dst_fid should be set to invalid value. To indicate a VM to VM flow, both + * of the path_tx and path_rx flags need to be set. For virtio vSwitch offload + * case, the src_fid and dst_fid is set to the same fid value. For the SRIOV + * vSwitch offload case, the src_fid and dst_fid must be set to the same VF FID + * belong to the children VFs of the same PF to indicate VM to VM flow. + */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_TX \ + UINT32_C(0x40) + /* + * when set to 1, indicates RX flow offload for function specified in dst_fid and + * the src_fid should be set to invalid value. + */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_RX \ + UINT32_C(0x80) + /* + * Set to 1 to indicate matching of VXLAN VNI from the custom vxlan header is + * required and the VXLAN VNI value is stored in the first 24 bits of the dmac field. + * This flag is only valid when the flow direction is RX. + */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_MATCH_VXLAN_IP_VNI \ + UINT32_C(0x100) + /* * Tx Flow: vf fid. * Rx Flow: pf fid. */ @@ -24104,6 +24097,14 @@ struct hwrm_cfa_flow_alloc_input { #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TTL_DECREMENT \ UINT32_C(0x200) /* + * If set to 1 and flow direction is TX, it indicates decap of L2 header + * and encap of tunnel header. If set to 1 and flow direction is RX, it + * indicates decap of tunnel header and encap L2 header. The type of tunnel + * is specified in the tunnel_type field. + */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL_IP \ + UINT32_C(0x400) + /* * Tx Flow: pf or vf fid. * Rx Flow: vf fid. */ @@ -24171,10 +24172,35 @@ struct hwrm_cfa_flow_alloc_input { uint16_t l2_rewrite_smac[3]; /* The value of ip protocol. */ uint8_t ip_proto; - uint8_t unused_0; + /* Tunnel Type. */ + uint8_t tunnel_type; + /* Non-tunnel */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL UINT32_C(0x0) + /* Virtual eXtensible Local Area Network (VXLAN) */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1) + /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE UINT32_C(0x2) + /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE UINT32_C(0x3) + /* IP in IP */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP UINT32_C(0x4) + /* Generic Network Virtualization Encapsulation (Geneve) */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5) + /* Multi-Protocol Lable Switching (MPLS) */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS UINT32_C(0x6) + /* Stateless Transport Tunnel (STT) */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT UINT32_C(0x7) + /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE UINT32_C(0x8) + /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 UINT32_C(0x9) + /* Any tunneled traffic */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL UINT32_C(0xff) + #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST \ + HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL } __attribute__((packed)); -/* hwrm_cfa_flow_alloc_output (size:128b/16B) */ +/* hwrm_cfa_flow_alloc_output (size:256b/32B) */ struct hwrm_cfa_flow_alloc_output { /* The specific error status for the command. */ uint16_t error_code; @@ -24186,7 +24212,18 @@ struct hwrm_cfa_flow_alloc_output { uint16_t resp_len; /* Flow record index. */ uint16_t flow_handle; - uint8_t unused_0[5]; + uint8_t unused_0[2]; + /* + * This is the ID of the flow associated with this + * filter. + * This value shall be used to match and associate the + * flow identifier returned in completion records. + * A value of 0xFFFFFFFF shall indicate no flow id. + */ + uint32_t flow_id; + /* This value identifies a set of CFA data structures used for a flow. */ + uint64_t ext_flow_handle; + uint8_t unused_1[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -24202,7 +24239,7 @@ struct hwrm_cfa_flow_alloc_output { **********************/ -/* hwrm_cfa_flow_free_input (size:192b/24B) */ +/* hwrm_cfa_flow_free_input (size:256b/32B) */ struct hwrm_cfa_flow_free_input { /* The HWRM command request type. */ uint16_t req_type; @@ -24234,6 +24271,8 @@ struct hwrm_cfa_flow_free_input { /* Flow record index. */ uint16_t flow_handle; uint8_t unused_0[6]; + /* This value identifies a set of CFA data structures used for a flow. */ + uint64_t ext_flow_handle; } __attribute__((packed)); /* hwrm_cfa_flow_free_output (size:256b/32B) */ @@ -24261,98 +24300,6 @@ struct hwrm_cfa_flow_free_output { uint8_t valid; } __attribute__((packed)); -/********************** - * hwrm_cfa_flow_info * - **********************/ - - -/* hwrm_cfa_flow_info_input (size:192b/24B) */ -struct hwrm_cfa_flow_info_input { - /* The HWRM command request type. */ - uint16_t req_type; - /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. - */ - uint16_t cmpl_ring; - /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. - */ - uint16_t seq_id; - /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFE - Reserved for internal processors - * * 0xFFFF - HWRM - */ - uint16_t target_id; - /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. - */ - uint64_t resp_addr; - /* Flow record index. */ - uint16_t flow_handle; - /* Max flow handle */ - #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_MASK \ - UINT32_C(0xfff) - #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_SFT 0 - /* CNP flow handle */ - #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_CNP_CNT \ - UINT32_C(0x1000) - /* Direction rx = 1 */ - #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_DIR_RX \ - UINT32_C(0x8000) - uint8_t unused_0[6]; -} __attribute__((packed)); - -/* hwrm_cfa_flow_info_output (size:448b/56B) */ -struct hwrm_cfa_flow_info_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - /* flags is 8 b */ - uint8_t flags; - /* profile is 8 b */ - uint8_t profile; - /* src_fid is 16 b */ - uint16_t src_fid; - /* dst_fid is 16 b */ - uint16_t dst_fid; - /* l2_ctxt_id is 16 b */ - uint16_t l2_ctxt_id; - /* em_info is 64 b */ - uint64_t em_info; - /* tcam_info is 64 b */ - uint64_t tcam_info; - /* vfp_tcam_info is 64 b */ - uint64_t vfp_tcam_info; - /* ar_id is 16 b */ - uint16_t ar_id; - /* flow_handle is 16 b */ - uint16_t flow_handle; - /* tunnel_handle is 32 b */ - uint32_t tunnel_handle; - uint8_t unused_0[7]; - /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. - */ - uint8_t valid; -} __attribute__((packed)); - /*********************** * hwrm_cfa_flow_flush * ***********************/ @@ -24417,7 +24364,7 @@ struct hwrm_cfa_flow_flush_output { ***********************/ -/* hwrm_cfa_flow_stats_input (size:320b/40B) */ +/* hwrm_cfa_flow_stats_input (size:640b/80B) */ struct hwrm_cfa_flow_stats_input { /* The HWRM command request type. */ uint16_t req_type; @@ -24469,6 +24416,26 @@ struct hwrm_cfa_flow_stats_input { /* Flow handle. */ uint16_t flow_handle_9; uint8_t unused_0[2]; + /* Flow ID of a flow. */ + uint32_t flow_id_0; + /* Flow ID of a flow. */ + uint32_t flow_id_1; + /* Flow ID of a flow. */ + uint32_t flow_id_2; + /* Flow ID of a flow. */ + uint32_t flow_id_3; + /* Flow ID of a flow. */ + uint32_t flow_id_4; + /* Flow ID of a flow. */ + uint32_t flow_id_5; + /* Flow ID of a flow. */ + uint32_t flow_id_6; + /* Flow ID of a flow. */ + uint32_t flow_id_7; + /* Flow ID of a flow. */ + uint32_t flow_id_8; + /* Flow ID of a flow. */ + uint32_t flow_id_9; } __attribute__((packed)); /* hwrm_cfa_flow_stats_output (size:1408b/176B) */ @@ -24532,421 +24499,6 @@ struct hwrm_cfa_flow_stats_output { uint8_t valid; } __attribute__((packed)); -/************************** - * hwrm_cfa_vf_pair_alloc * - **************************/ - - -/* hwrm_cfa_vf_pair_alloc_input (size:448b/56B) */ -struct hwrm_cfa_vf_pair_alloc_input { - /* The HWRM command request type. */ - uint16_t req_type; - /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. - */ - uint16_t cmpl_ring; - /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. - */ - uint16_t seq_id; - /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFE - Reserved for internal processors - * * 0xFFFF - HWRM - */ - uint16_t target_id; - /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. - */ - uint64_t resp_addr; - /* Logical VF number (range: 0 -> MAX_VFS -1). */ - uint16_t vf_a_id; - /* Logical VF number (range: 0 -> MAX_VFS -1). */ - uint16_t vf_b_id; - uint8_t unused_0[4]; - /* VF Pair name (32 byte string). */ - char pair_name[32]; -} __attribute__((packed)); - -/* hwrm_cfa_vf_pair_alloc_output (size:128b/16B) */ -struct hwrm_cfa_vf_pair_alloc_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint8_t unused_0[7]; - /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. - */ - uint8_t valid; -} __attribute__((packed)); - -/************************* - * hwrm_cfa_vf_pair_free * - *************************/ - - -/* hwrm_cfa_vf_pair_free_input (size:384b/48B) */ -struct hwrm_cfa_vf_pair_free_input { - /* The HWRM command request type. */ - uint16_t req_type; - /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. - */ - uint16_t cmpl_ring; - /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. - */ - uint16_t seq_id; - /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFE - Reserved for internal processors - * * 0xFFFF - HWRM - */ - uint16_t target_id; - /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. - */ - uint64_t resp_addr; - /* VF Pair name (32 byte string). */ - char pair_name[32]; -} __attribute__((packed)); - -/* hwrm_cfa_vf_pair_free_output (size:128b/16B) */ -struct hwrm_cfa_vf_pair_free_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint8_t unused_0[7]; - /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. - */ - uint8_t valid; -} __attribute__((packed)); - -/************************* - * hwrm_cfa_vf_pair_info * - *************************/ - - -/* hwrm_cfa_vf_pair_info_input (size:448b/56B) */ -struct hwrm_cfa_vf_pair_info_input { - /* The HWRM command request type. */ - uint16_t req_type; - /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. - */ - uint16_t cmpl_ring; - /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. - */ - uint16_t seq_id; - /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFE - Reserved for internal processors - * * 0xFFFF - HWRM - */ - uint16_t target_id; - /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. - */ - uint64_t resp_addr; - uint32_t flags; - /* If this flag is set, lookup by name else lookup by index. */ - #define HWRM_CFA_VF_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE UINT32_C(0x1) - /* vf pair table index. */ - uint16_t vf_pair_index; - uint8_t unused_0[2]; - /* VF Pair name (32 byte string). */ - char vf_pair_name[32]; -} __attribute__((packed)); - -/* hwrm_cfa_vf_pair_info_output (size:512b/64B) */ -struct hwrm_cfa_vf_pair_info_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - /* vf pair table index. */ - uint16_t next_vf_pair_index; - /* vf pair member a's vf_fid. */ - uint16_t vf_a_fid; - /* vf pair member a's Linux logical VF number. */ - uint16_t vf_a_index; - /* vf pair member b's vf_fid. */ - uint16_t vf_b_fid; - /* vf pair member a's Linux logical VF number. */ - uint16_t vf_b_index; - /* vf pair state. */ - uint8_t pair_state; - /* Pair has been allocated */ - #define HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_ALLOCATED UINT32_C(0x1) - /* Both pair members are active */ - #define HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE UINT32_C(0x2) - #define HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_LAST \ - HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE - uint8_t unused_0[5]; - /* VF Pair name (32 byte string). */ - char pair_name[32]; - uint8_t unused_1[7]; - /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. - */ - uint8_t valid; -} __attribute__((packed)); - -/*********************** - * hwrm_cfa_pair_alloc * - ***********************/ - - -/* hwrm_cfa_pair_alloc_input (size:576b/72B) */ -struct hwrm_cfa_pair_alloc_input { - /* The HWRM command request type. */ - uint16_t req_type; - /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. - */ - uint16_t cmpl_ring; - /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. - */ - uint16_t seq_id; - /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFE - Reserved for internal processors - * * 0xFFFF - HWRM - */ - uint16_t target_id; - /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. - */ - uint64_t resp_addr; - /* Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair, 5-rep2fn_mod). */ - uint8_t pair_mode; - /* Pair between VF on local host with PF or VF on specified host. */ - #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_VF2FN UINT32_C(0x0) - /* Pair between REP on local host with PF or VF on specified host. */ - #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN UINT32_C(0x1) - /* Pair between REP on local host with REP on specified host. */ - #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2REP UINT32_C(0x2) - /* Pair for the proxy interface. */ - #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_PROXY UINT32_C(0x3) - /* Pair for the PF interface. */ - #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_PFPAIR UINT32_C(0x4) - /* Modify exiting rep2fn pair and move pair to new PF. */ - #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_MOD UINT32_C(0x5) - /* Modify exiting rep2fn pairs paired with same PF and move pairs to new PF. */ - #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_MODALL UINT32_C(0x6) - #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_LAST \ - HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_MODALL - uint8_t unused_0; - /* Logical VF number (range: 0 -> MAX_VFS -1). */ - uint16_t vf_a_id; - /* Logical Host (0xff-local host). */ - uint8_t host_b_id; - /* Logical PF (0xff-PF for command channel). */ - uint8_t pf_b_id; - /* Logical VF number (range: 0 -> MAX_VFS -1). */ - uint16_t vf_b_id; - /* Loopback port (0xff-internal loopback), valid for mode-3. */ - uint8_t port_id; - /* Priority used for encap of loopback packets valid for mode-3. */ - uint8_t pri; - /* New PF for rep2fn modify, valid for mode 5. */ - uint16_t new_pf_fid; - uint32_t enables; - /* - * This bit must be '1' for the q_ab field to be - * configured. - */ - #define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_AB_VALID UINT32_C(0x1) - /* - * This bit must be '1' for the q_ba field to be - * configured. - */ - #define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_BA_VALID UINT32_C(0x2) - /* - * This bit must be '1' for the fc_ab field to be - * configured. - */ - #define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_AB_VALID UINT32_C(0x4) - /* - * This bit must be '1' for the fc_ba field to be - * configured. - */ - #define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_BA_VALID UINT32_C(0x8) - /* VF Pair name (32 byte string). */ - char pair_name[32]; - /* - * The q_ab value specifies the logical index of the TX/RX CoS - * queue to be assigned for traffic in the A to B direction of - * the interface pair. The default value is 0. - */ - uint8_t q_ab; - /* - * The q_ba value specifies the logical index of the TX/RX CoS - * queue to be assigned for traffic in the B to A direction of - * the interface pair. The default value is 1. - */ - uint8_t q_ba; - /* - * Specifies whether RX ring flow control is disabled (0) or enabled - * (1) in the A to B direction. The default value is 0, meaning that - * packets will be dropped when the B-side RX rings are full. - */ - uint8_t fc_ab; - /* - * Specifies whether RX ring flow control is disabled (0) or enabled - * (1) in the B to A direction. The default value is 1, meaning that - * the RX CoS queue will be flow controlled when the A-side RX rings - * are full. - */ - uint8_t fc_ba; - uint8_t unused_1[4]; -} __attribute__((packed)); - -/* hwrm_cfa_pair_alloc_output (size:192b/24B) */ -struct hwrm_cfa_pair_alloc_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - /* Only valid for modes 1 and 2. */ - uint16_t rx_cfa_code_a; - /* Only valid for modes 1 and 2. */ - uint16_t tx_cfa_action_a; - /* Only valid for mode 2. */ - uint16_t rx_cfa_code_b; - /* Only valid for mode 2. */ - uint16_t tx_cfa_action_b; - uint8_t unused_0[7]; - /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. - */ - uint8_t valid; -} __attribute__((packed)); - -/********************** - * hwrm_cfa_pair_free * - **********************/ - - -/* hwrm_cfa_pair_free_input (size:384b/48B) */ -struct hwrm_cfa_pair_free_input { - /* The HWRM command request type. */ - uint16_t req_type; - /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. - */ - uint16_t cmpl_ring; - /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. - */ - uint16_t seq_id; - /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFE - Reserved for internal processors - * * 0xFFFF - HWRM - */ - uint16_t target_id; - /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. - */ - uint64_t resp_addr; - /* VF Pair name (32 byte string). */ - char pair_name[32]; -} __attribute__((packed)); - -/* hwrm_cfa_pair_free_output (size:128b/16B) */ -struct hwrm_cfa_pair_free_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint8_t unused_0[7]; - /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. - */ - uint8_t valid; -} __attribute__((packed)); - /********************** * hwrm_cfa_pair_info * **********************/ @@ -25067,13 +24619,13 @@ struct hwrm_cfa_pair_info_output { uint8_t valid; } __attribute__((packed)); -/********************** - * hwrm_cfa_vfr_alloc * - **********************/ +/*************************************** + * hwrm_cfa_redirect_query_tunnel_type * + ***************************************/ -/* hwrm_cfa_vfr_alloc_input (size:448b/56B) */ -struct hwrm_cfa_vfr_alloc_input { +/* hwrm_cfa_redirect_query_tunnel_type_input (size:192b/24B) */ +struct hwrm_cfa_redirect_query_tunnel_type_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -25101,20 +24653,13 @@ struct hwrm_cfa_vfr_alloc_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Logical VF number (range: 0 -> MAX_VFS -1). */ - uint16_t vf_id; - /* - * This field is reserved for the future use. - * It shall be set to 0. - */ - uint16_t reserved; - uint8_t unused_0[4]; - /* VF Representor name (32 byte string). */ - char vfr_name[32]; + /* The source function id. */ + uint16_t src_fid; + uint8_t unused_0[6]; } __attribute__((packed)); -/* hwrm_cfa_vfr_alloc_output (size:128b/16B) */ -struct hwrm_cfa_vfr_alloc_output { +/* hwrm_cfa_redirect_query_tunnel_type_output (size:128b/16B) */ +struct hwrm_cfa_redirect_query_tunnel_type_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -25123,10 +24668,44 @@ struct hwrm_cfa_vfr_alloc_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Rx CFA code. */ - uint16_t rx_cfa_code; - /* Tx CFA action. */ - uint16_t tx_cfa_action; + /* Tunnel Mask. */ + uint32_t tunnel_mask; + /* Non-tunnel */ + #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NONTUNNEL \ + UINT32_C(0x1) + /* Virtual eXtensible Local Area Network (VXLAN) */ + #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN \ + UINT32_C(0x2) + /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ + #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NVGRE \ + UINT32_C(0x4) + /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ + #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2GRE \ + UINT32_C(0x8) + /* IP in IP */ + #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPIP \ + UINT32_C(0x10) + /* Generic Network Virtualization Encapsulation (Geneve) */ + #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_GENEVE \ + UINT32_C(0x20) + /* Multi-Protocol Lable Switching (MPLS) */ + #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_MPLS \ + UINT32_C(0x40) + /* Stateless Transport Tunnel (STT) */ + #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_STT \ + UINT32_C(0x80) + /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ + #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE \ + UINT32_C(0x100) + /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ + #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_V4 \ + UINT32_C(0x200) + /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ + #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE_V1 \ + UINT32_C(0x400) + /* Any tunneled traffic */ + #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_ANYTUNNEL \ + UINT32_C(0x800) uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output @@ -25138,65 +24717,6 @@ struct hwrm_cfa_vfr_alloc_output { uint8_t valid; } __attribute__((packed)); -/********************* - * hwrm_cfa_vfr_free * - *********************/ - - -/* hwrm_cfa_vfr_free_input (size:384b/48B) */ -struct hwrm_cfa_vfr_free_input { - /* The HWRM command request type. */ - uint16_t req_type; - /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. - */ - uint16_t cmpl_ring; - /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. - */ - uint16_t seq_id; - /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFE - Reserved for internal processors - * * 0xFFFF - HWRM - */ - uint16_t target_id; - /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. - */ - uint64_t resp_addr; - /* VF Representor name (32 byte string). */ - char vfr_name[32]; -} __attribute__((packed)); - -/* hwrm_cfa_vfr_free_output (size:128b/16B) */ -struct hwrm_cfa_vfr_free_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint8_t unused_0[7]; - /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. - */ - uint8_t valid; -} __attribute__((packed)); - /****************************** * hwrm_tunnel_dst_port_query * ******************************/ @@ -25460,6 +24980,7 @@ struct hwrm_tunnel_dst_port_free_output { uint8_t valid; } __attribute__((packed)); +/* Periodic statistics context DMA to host. */ /* ctx_hw_stats (size:1280b/160B) */ struct ctx_hw_stats { /* Number of received unicast packets */ @@ -25882,377 +25403,6 @@ struct hwrm_pcie_qstats_output { uint8_t valid; } __attribute__((packed)); -/* Port Tx Statistics Formats */ -/* tx_port_stats (size:3264b/408B) */ -struct tx_port_stats { - /* Total Number of 64 Bytes frames transmitted */ - uint64_t tx_64b_frames; - /* Total Number of 65-127 Bytes frames transmitted */ - uint64_t tx_65b_127b_frames; - /* Total Number of 128-255 Bytes frames transmitted */ - uint64_t tx_128b_255b_frames; - /* Total Number of 256-511 Bytes frames transmitted */ - uint64_t tx_256b_511b_frames; - /* Total Number of 512-1023 Bytes frames transmitted */ - uint64_t tx_512b_1023b_frames; - /* Total Number of 1024-1518 Bytes frames transmitted */ - uint64_t tx_1024b_1518_frames; - /* - * Total Number of each good VLAN (exludes FCS errors) - * frame transmitted which is 1519 to 1522 bytes in length - * inclusive (excluding framing bits but including FCS bytes). - */ - uint64_t tx_good_vlan_frames; - /* Total Number of 1519-2047 Bytes frames transmitted */ - uint64_t tx_1519b_2047_frames; - /* Total Number of 2048-4095 Bytes frames transmitted */ - uint64_t tx_2048b_4095b_frames; - /* Total Number of 4096-9216 Bytes frames transmitted */ - uint64_t tx_4096b_9216b_frames; - /* Total Number of 9217-16383 Bytes frames transmitted */ - uint64_t tx_9217b_16383b_frames; - /* Total Number of good frames transmitted */ - uint64_t tx_good_frames; - /* Total Number of frames transmitted */ - uint64_t tx_total_frames; - /* Total number of unicast frames transmitted */ - uint64_t tx_ucast_frames; - /* Total number of multicast frames transmitted */ - uint64_t tx_mcast_frames; - /* Total number of broadcast frames transmitted */ - uint64_t tx_bcast_frames; - /* Total number of PAUSE control frames transmitted */ - uint64_t tx_pause_frames; - /* - * Total number of PFC/per-priority PAUSE - * control frames transmitted - */ - uint64_t tx_pfc_frames; - /* Total number of jabber frames transmitted */ - uint64_t tx_jabber_frames; - /* Total number of frames transmitted with FCS error */ - uint64_t tx_fcs_err_frames; - /* Total number of control frames transmitted */ - uint64_t tx_control_frames; - /* Total number of over-sized frames transmitted */ - uint64_t tx_oversz_frames; - /* Total number of frames with single deferral */ - uint64_t tx_single_dfrl_frames; - /* Total number of frames with multiple deferrals */ - uint64_t tx_multi_dfrl_frames; - /* Total number of frames with single collision */ - uint64_t tx_single_coll_frames; - /* Total number of frames with multiple collisions */ - uint64_t tx_multi_coll_frames; - /* Total number of frames with late collisions */ - uint64_t tx_late_coll_frames; - /* Total number of frames with excessive collisions */ - uint64_t tx_excessive_coll_frames; - /* Total number of fragmented frames transmitted */ - uint64_t tx_frag_frames; - /* Total number of transmit errors */ - uint64_t tx_err; - /* Total number of single VLAN tagged frames transmitted */ - uint64_t tx_tagged_frames; - /* Total number of double VLAN tagged frames transmitted */ - uint64_t tx_dbl_tagged_frames; - /* Total number of runt frames transmitted */ - uint64_t tx_runt_frames; - /* Total number of TX FIFO under runs */ - uint64_t tx_fifo_underruns; - /* - * Total number of PFC frames with PFC enabled bit for - * Pri 0 transmitted - */ - uint64_t tx_pfc_ena_frames_pri0; - /* - * Total number of PFC frames with PFC enabled bit for - * Pri 1 transmitted - */ - uint64_t tx_pfc_ena_frames_pri1; - /* - * Total number of PFC frames with PFC enabled bit for - * Pri 2 transmitted - */ - uint64_t tx_pfc_ena_frames_pri2; - /* - * Total number of PFC frames with PFC enabled bit for - * Pri 3 transmitted - */ - uint64_t tx_pfc_ena_frames_pri3; - /* - * Total number of PFC frames with PFC enabled bit for - * Pri 4 transmitted - */ - uint64_t tx_pfc_ena_frames_pri4; - /* - * Total number of PFC frames with PFC enabled bit for - * Pri 5 transmitted - */ - uint64_t tx_pfc_ena_frames_pri5; - /* - * Total number of PFC frames with PFC enabled bit for - * Pri 6 transmitted - */ - uint64_t tx_pfc_ena_frames_pri6; - /* - * Total number of PFC frames with PFC enabled bit for - * Pri 7 transmitted - */ - uint64_t tx_pfc_ena_frames_pri7; - /* Total number of EEE LPI Events on TX */ - uint64_t tx_eee_lpi_events; - /* EEE LPI Duration Counter on TX */ - uint64_t tx_eee_lpi_duration; - /* - * Total number of Link Level Flow Control (LLFC) messages - * transmitted - */ - uint64_t tx_llfc_logical_msgs; - /* Total number of HCFC messages transmitted */ - uint64_t tx_hcfc_msgs; - /* Total number of TX collisions */ - uint64_t tx_total_collisions; - /* Total number of transmitted bytes */ - uint64_t tx_bytes; - /* Total number of end-to-end HOL frames */ - uint64_t tx_xthol_frames; - /* Total Tx Drops per Port reported by STATS block */ - uint64_t tx_stat_discard; - /* Total Tx Error Drops per Port reported by STATS block */ - uint64_t tx_stat_error; -} __attribute__((packed)); - -/* Port Rx Statistics Formats */ -/* rx_port_stats (size:4224b/528B) */ -struct rx_port_stats { - /* Total Number of 64 Bytes frames received */ - uint64_t rx_64b_frames; - /* Total Number of 65-127 Bytes frames received */ - uint64_t rx_65b_127b_frames; - /* Total Number of 128-255 Bytes frames received */ - uint64_t rx_128b_255b_frames; - /* Total Number of 256-511 Bytes frames received */ - uint64_t rx_256b_511b_frames; - /* Total Number of 512-1023 Bytes frames received */ - uint64_t rx_512b_1023b_frames; - /* Total Number of 1024-1518 Bytes frames received */ - uint64_t rx_1024b_1518_frames; - /* - * Total Number of each good VLAN (exludes FCS errors) - * frame received which is 1519 to 1522 bytes in length - * inclusive (excluding framing bits but including FCS bytes). - */ - uint64_t rx_good_vlan_frames; - /* Total Number of 1519-2047 Bytes frames received */ - uint64_t rx_1519b_2047b_frames; - /* Total Number of 2048-4095 Bytes frames received */ - uint64_t rx_2048b_4095b_frames; - /* Total Number of 4096-9216 Bytes frames received */ - uint64_t rx_4096b_9216b_frames; - /* Total Number of 9217-16383 Bytes frames received */ - uint64_t rx_9217b_16383b_frames; - /* Total number of frames received */ - uint64_t rx_total_frames; - /* Total number of unicast frames received */ - uint64_t rx_ucast_frames; - /* Total number of multicast frames received */ - uint64_t rx_mcast_frames; - /* Total number of broadcast frames received */ - uint64_t rx_bcast_frames; - /* Total number of received frames with FCS error */ - uint64_t rx_fcs_err_frames; - /* Total number of control frames received */ - uint64_t rx_ctrl_frames; - /* Total number of PAUSE frames received */ - uint64_t rx_pause_frames; - /* Total number of PFC frames received */ - uint64_t rx_pfc_frames; - /* - * Total number of frames received with an unsupported - * opcode - */ - uint64_t rx_unsupported_opcode_frames; - /* - * Total number of frames received with an unsupported - * DA for pause and PFC - */ - uint64_t rx_unsupported_da_pausepfc_frames; - /* Total number of frames received with an unsupported SA */ - uint64_t rx_wrong_sa_frames; - /* Total number of received packets with alignment error */ - uint64_t rx_align_err_frames; - /* Total number of received frames with out-of-range length */ - uint64_t rx_oor_len_frames; - /* Total number of received frames with error termination */ - uint64_t rx_code_err_frames; - /* - * Total number of received frames with a false carrier is - * detected during idle, as defined by RX_ER samples active - * and RXD is 0xE. The event is reported along with the - * statistics generated on the next received frame. Only - * one false carrier condition can be detected and logged - * between frames. - * - * Carrier event, valid for 10M/100M speed modes only. - */ - uint64_t rx_false_carrier_frames; - /* Total number of over-sized frames received */ - uint64_t rx_ovrsz_frames; - /* Total number of jabber packets received */ - uint64_t rx_jbr_frames; - /* Total number of received frames with MTU error */ - uint64_t rx_mtu_err_frames; - /* Total number of received frames with CRC match */ - uint64_t rx_match_crc_frames; - /* Total number of frames received promiscuously */ - uint64_t rx_promiscuous_frames; - /* - * Total number of received frames with one or two VLAN - * tags - */ - uint64_t rx_tagged_frames; - /* Total number of received frames with two VLAN tags */ - uint64_t rx_double_tagged_frames; - /* Total number of truncated frames received */ - uint64_t rx_trunc_frames; - /* Total number of good frames (without errors) received */ - uint64_t rx_good_frames; - /* - * Total number of received PFC frames with transition from - * XON to XOFF on Pri 0 - */ - uint64_t rx_pfc_xon2xoff_frames_pri0; - /* - * Total number of received PFC frames with transition from - * XON to XOFF on Pri 1 - */ - uint64_t rx_pfc_xon2xoff_frames_pri1; - /* - * Total number of received PFC frames with transition from - * XON to XOFF on Pri 2 - */ - uint64_t rx_pfc_xon2xoff_frames_pri2; - /* - * Total number of received PFC frames with transition from - * XON to XOFF on Pri 3 - */ - uint64_t rx_pfc_xon2xoff_frames_pri3; - /* - * Total number of received PFC frames with transition from - * XON to XOFF on Pri 4 - */ - uint64_t rx_pfc_xon2xoff_frames_pri4; - /* - * Total number of received PFC frames with transition from - * XON to XOFF on Pri 5 - */ - uint64_t rx_pfc_xon2xoff_frames_pri5; - /* - * Total number of received PFC frames with transition from - * XON to XOFF on Pri 6 - */ - uint64_t rx_pfc_xon2xoff_frames_pri6; - /* - * Total number of received PFC frames with transition from - * XON to XOFF on Pri 7 - */ - uint64_t rx_pfc_xon2xoff_frames_pri7; - /* - * Total number of received PFC frames with PFC enabled - * bit for Pri 0 - */ - uint64_t rx_pfc_ena_frames_pri0; - /* - * Total number of received PFC frames with PFC enabled - * bit for Pri 1 - */ - uint64_t rx_pfc_ena_frames_pri1; - /* - * Total number of received PFC frames with PFC enabled - * bit for Pri 2 - */ - uint64_t rx_pfc_ena_frames_pri2; - /* - * Total number of received PFC frames with PFC enabled - * bit for Pri 3 - */ - uint64_t rx_pfc_ena_frames_pri3; - /* - * Total number of received PFC frames with PFC enabled - * bit for Pri 4 - */ - uint64_t rx_pfc_ena_frames_pri4; - /* - * Total number of received PFC frames with PFC enabled - * bit for Pri 5 - */ - uint64_t rx_pfc_ena_frames_pri5; - /* - * Total number of received PFC frames with PFC enabled - * bit for Pri 6 - */ - uint64_t rx_pfc_ena_frames_pri6; - /* - * Total number of received PFC frames with PFC enabled - * bit for Pri 7 - */ - uint64_t rx_pfc_ena_frames_pri7; - /* Total Number of frames received with SCH CRC error */ - uint64_t rx_sch_crc_err_frames; - /* Total Number of under-sized frames received */ - uint64_t rx_undrsz_frames; - /* Total Number of fragmented frames received */ - uint64_t rx_frag_frames; - /* Total number of RX EEE LPI Events */ - uint64_t rx_eee_lpi_events; - /* EEE LPI Duration Counter on RX */ - uint64_t rx_eee_lpi_duration; - /* - * Total number of physical type Link Level Flow Control - * (LLFC) messages received - */ - uint64_t rx_llfc_physical_msgs; - /* - * Total number of logical type Link Level Flow Control - * (LLFC) messages received - */ - uint64_t rx_llfc_logical_msgs; - /* - * Total number of logical type Link Level Flow Control - * (LLFC) messages received with CRC error - */ - uint64_t rx_llfc_msgs_with_crc_err; - /* Total number of HCFC messages received */ - uint64_t rx_hcfc_msgs; - /* Total number of HCFC messages received with CRC error */ - uint64_t rx_hcfc_msgs_with_crc_err; - /* Total number of received bytes */ - uint64_t rx_bytes; - /* Total number of bytes received in runt frames */ - uint64_t rx_runt_bytes; - /* Total number of runt frames received */ - uint64_t rx_runt_frames; - /* Total Rx Discards per Port reported by STATS block */ - uint64_t rx_stat_discard; - uint64_t rx_stat_err; -} __attribute__((packed)); - -/* Port Rx Statistics extended Formats */ -/* rx_port_stats_ext (size:320b/40B) */ -struct rx_port_stats_ext { - /* Number of times link state changed to down */ - uint64_t link_down_events; - /* Number of times the idle rings with pause bit are found */ - uint64_t continuous_pause_events; - /* Number of times the active rings pause bit resumed back */ - uint64_t resume_pause_events; - /* Number of times, the ROCE cos queue PFC is disabled to avoid pause flood/burst */ - uint64_t continuous_roce_pause_events; - /* Number of times, the ROCE cos queue PFC is enabled back */ - uint64_t resume_roce_pause_events; -} __attribute__((packed)); - /* PCIe Statistics Formats */ /* pcie_ctx_hw_stats (size:768b/96B) */ struct pcie_ctx_hw_stats { @@ -28109,103 +27259,4 @@ struct hwrm_nvm_validate_option_cmd_err { uint8_t unused_0[7]; } __attribute__((packed)); -/***************************** - * hwrm_nvm_factory_defaults * - *****************************/ - - -/* hwrm_nvm_factory_defaults_input (size:192b/24B) */ -struct hwrm_nvm_factory_defaults_input { - /* The HWRM command request type. */ - uint16_t req_type; - /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. - */ - uint16_t cmpl_ring; - /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. - */ - uint16_t seq_id; - /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFE - Reserved for internal processors - * * 0xFFFF - HWRM - */ - uint16_t target_id; - /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. - */ - uint64_t resp_addr; - /* mode is 8 b */ - uint8_t mode; - /* If set to 1, it will trigger restoration of factory default settings */ - #define HWRM_NVM_FACTORY_DEFAULTS_INPUT_MODE_RESTORE UINT32_C(0x0) - /* If set to 1, it will trigger creation of factory default settings */ - #define HWRM_NVM_FACTORY_DEFAULTS_INPUT_MODE_CREATE UINT32_C(0x1) - #define HWRM_NVM_FACTORY_DEFAULTS_INPUT_MODE_LAST \ - HWRM_NVM_FACTORY_DEFAULTS_INPUT_MODE_CREATE - uint8_t unused_0[7]; -} __attribute__((packed)); - -/* hwrm_nvm_factory_defaults_output (size:128b/16B) */ -struct hwrm_nvm_factory_defaults_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint8_t result; - /* factory defaults created successfully. */ - #define HWRM_NVM_FACTORY_DEFAULTS_OUTPUT_RESULT_CREATE_OK \ - UINT32_C(0x0) - /* factory defaults restored successfully. */ - #define HWRM_NVM_FACTORY_DEFAULTS_OUTPUT_RESULT_RESTORE_OK \ - UINT32_C(0x1) - /* factory defaults already created. */ - #define HWRM_NVM_FACTORY_DEFAULTS_OUTPUT_RESULT_CREATE_ALREADY \ - UINT32_C(0x2) - #define HWRM_NVM_FACTORY_DEFAULTS_OUTPUT_RESULT_LAST \ - HWRM_NVM_FACTORY_DEFAULTS_OUTPUT_RESULT_CREATE_ALREADY - uint8_t unused_0[6]; - /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. - */ - uint8_t valid; -} __attribute__((packed)); - -/* hwrm_nvm_factory_defaults_cmd_err (size:64b/8B) */ -struct hwrm_nvm_factory_defaults_cmd_err { - /* - * command specific error codes that goes to - * the cmd_err field in Common HWRM Error Response. - */ - uint8_t code; - /* Unknown error */ - #define HWRM_NVM_FACTORY_DEFAULTS_CMD_ERR_CODE_UNKNOWN \ - UINT32_C(0x0) - /* valid configuration not present to create defaults */ - #define HWRM_NVM_FACTORY_DEFAULTS_CMD_ERR_CODE_NO_VALID_CFG \ - UINT32_C(0x1) - /* No saved configuration present to restore, restore failed */ - #define HWRM_NVM_FACTORY_DEFAULTS_CMD_ERR_CODE_NO_SAVED_CFG \ - UINT32_C(0x2) - #define HWRM_NVM_FACTORY_DEFAULTS_CMD_ERR_CODE_LAST \ - HWRM_NVM_FACTORY_DEFAULTS_CMD_ERR_CODE_NO_SAVED_CFG - uint8_t unused_0[7]; -} __attribute__((packed)); - #endif /* _HSI_STRUCT_DEF_DPDK_H_ */ |