diff options
Diffstat (limited to 'drivers/net/nfp')
37 files changed, 8528 insertions, 1370 deletions
diff --git a/drivers/net/nfp/Makefile b/drivers/net/nfp/Makefile index aa3b68a4..ab4e0a7d 100644 --- a/drivers/net/nfp/Makefile +++ b/drivers/net/nfp/Makefile @@ -20,11 +20,24 @@ EXPORT_MAP := rte_pmd_nfp_version.map LIBABIVER := 1 +VPATH += $(SRCDIR)/nfpcore + +SRCS-$(CONFIG_RTE_LIBRTE_NFP_PMD) += nfp_cppcore.c +SRCS-$(CONFIG_RTE_LIBRTE_NFP_PMD) += nfp_cpp_pcie_ops.c +SRCS-$(CONFIG_RTE_LIBRTE_NFP_PMD) += nfp_mutex.c +SRCS-$(CONFIG_RTE_LIBRTE_NFP_PMD) += nfp_resource.c +SRCS-$(CONFIG_RTE_LIBRTE_NFP_PMD) += nfp_crc.c +SRCS-$(CONFIG_RTE_LIBRTE_NFP_PMD) += nfp_mip.c +SRCS-$(CONFIG_RTE_LIBRTE_NFP_PMD) += nfp_nffw.c +SRCS-$(CONFIG_RTE_LIBRTE_NFP_PMD) += nfp_hwinfo.c +SRCS-$(CONFIG_RTE_LIBRTE_NFP_PMD) += nfp_rtsym.c +SRCS-$(CONFIG_RTE_LIBRTE_NFP_PMD) += nfp_nsp.c +SRCS-$(CONFIG_RTE_LIBRTE_NFP_PMD) += nfp_nsp_cmds.c +SRCS-$(CONFIG_RTE_LIBRTE_NFP_PMD) += nfp_nsp_eth.c + # # all source are stored in SRCS-y # SRCS-$(CONFIG_RTE_LIBRTE_NFP_PMD) += nfp_net.c -SRCS-$(CONFIG_RTE_LIBRTE_NFP_PMD) += nfp_nfpu.c -SRCS-$(CONFIG_RTE_LIBRTE_NFP_PMD) += nfp_nspu.c include $(RTE_SDK)/mk/rte.lib.mk diff --git a/drivers/net/nfp/meson.build b/drivers/net/nfp/meson.build new file mode 100644 index 00000000..3ba37e27 --- /dev/null +++ b/drivers/net/nfp/meson.build @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2018 Intel Corporation + +sources = files('nfpcore/nfp_cpp_pcie_ops.c', + 'nfpcore/nfp_nsp.c', + 'nfpcore/nfp_cppcore.c', + 'nfpcore/nfp_resource.c', + 'nfpcore/nfp_mip.c', + 'nfpcore/nfp_nffw.c', + 'nfpcore/nfp_rtsym.c', + 'nfpcore/nfp_nsp_cmds.c', + 'nfpcore/nfp_crc.c', + 'nfpcore/nfp_mutex.c', + 'nfpcore/nfp_nsp_eth.c', + 'nfpcore/nfp_hwinfo.c', + 'nfp_net.c') diff --git a/drivers/net/nfp/nfp_net.c b/drivers/net/nfp/nfp_net.c index e5bfde62..6e5e305f 100644 --- a/drivers/net/nfp/nfp_net.c +++ b/drivers/net/nfp/nfp_net.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014, 2015 Netronome Systems, Inc. + * Copyright (c) 2014-2018 Netronome Systems, Inc. * All rights reserved. * * Small portions derived from code Copyright(c) 2010-2015 Intel Corporation. @@ -55,7 +55,13 @@ #include <rte_alarm.h> #include <rte_spinlock.h> -#include "nfp_nfpu.h" +#include "nfpcore/nfp_cpp.h" +#include "nfpcore/nfp_nffw.h" +#include "nfpcore/nfp_hwinfo.h" +#include "nfpcore/nfp_mip.h" +#include "nfpcore/nfp_rtsym.h" +#include "nfpcore/nfp_nsp.h" + #include "nfp_net_pmd.h" #include "nfp_net_logs.h" #include "nfp_net_ctrl.h" @@ -103,13 +109,11 @@ static int nfp_net_rss_reta_write(struct rte_eth_dev *dev, uint16_t reta_size); static int nfp_net_rss_hash_write(struct rte_eth_dev *dev, struct rte_eth_rss_conf *rss_conf); +static int nfp_set_mac_addr(struct rte_eth_dev *dev, + struct ether_addr *mac_addr); -/* - * The offset of the queue controller queues in the PCIe Target. These - * happen to be at the same offset on the NFP6000 and the NFP3200 so - * we use a single macro here. - */ -#define NFP_PCIE_QUEUE(_q) (0x800 * ((_q) & 0xff)) +/* The offset of the queue controller queues in the PCIe Target */ +#define NFP_PCIE_QUEUE(_q) (0x80000 + (NFP_QCP_QUEUE_ADDR_SZ * ((_q) & 0xff))) /* Maximum value which can be added to a queue with one transaction */ #define NFP_QCP_MAX_ADD 0x7f @@ -213,57 +217,6 @@ nn_cfg_writeq(struct nfp_net_hw *hw, int off, uint64_t val) nn_writeq(rte_cpu_to_le_64(val), hw->ctrl_bar + off); } -/* - * Atomically reads link status information from global structure rte_eth_dev. - * - * @param dev - * - Pointer to the structure rte_eth_dev to read from. - * - Pointer to the buffer to be saved with the link status. - * - * @return - * - On success, zero. - * - On failure, negative value. - */ -static inline int -nfp_net_dev_atomic_read_link_status(struct rte_eth_dev *dev, - struct rte_eth_link *link) -{ - struct rte_eth_link *dst = link; - struct rte_eth_link *src = &dev->data->dev_link; - - if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst, - *(uint64_t *)src) == 0) - return -1; - - return 0; -} - -/* - * Atomically writes the link status information into global - * structure rte_eth_dev. - * - * @param dev - * - Pointer to the structure rte_eth_dev to read from. - * - Pointer to the buffer to be saved with the link status. - * - * @return - * - On success, zero. - * - On failure, negative value. - */ -static inline int -nfp_net_dev_atomic_write_link_status(struct rte_eth_dev *dev, - struct rte_eth_link *link) -{ - struct rte_eth_link *dst = &dev->data->dev_link; - struct rte_eth_link *src = link; - - if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst, - *(uint64_t *)src) == 0) - return -1; - - return 0; -} - static void nfp_net_rx_queue_release_mbufs(struct nfp_net_rxq *rxq) { @@ -310,7 +263,7 @@ nfp_net_tx_queue_release_mbufs(struct nfp_net_txq *txq) for (i = 0; i < txq->tx_count; i++) { if (txq->txbufs[i].mbuf) { - rte_pktmbuf_free(txq->txbufs[i].mbuf); + rte_pktmbuf_free_seg(txq->txbufs[i].mbuf); txq->txbufs[i].mbuf = NULL; } } @@ -343,7 +296,7 @@ __nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t update) uint32_t new; struct timespec wait; - PMD_DRV_LOG(DEBUG, "Writing to the configuration queue (%p)...\n", + PMD_DRV_LOG(DEBUG, "Writing to the configuration queue (%p)...", hw->qcp_cfg); if (hw->qcp_cfg == NULL) @@ -354,7 +307,7 @@ __nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t update) wait.tv_sec = 0; wait.tv_nsec = 1000000; - PMD_DRV_LOG(DEBUG, "Polling for update ack...\n"); + PMD_DRV_LOG(DEBUG, "Polling for update ack..."); /* Poll update field, waiting for NFP to ack the config */ for (cnt = 0; ; cnt++) { @@ -372,7 +325,7 @@ __nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t update) } nanosleep(&wait, 0); /* waiting for a 1ms */ } - PMD_DRV_LOG(DEBUG, "Ack DONE\n"); + PMD_DRV_LOG(DEBUG, "Ack DONE"); return 0; } @@ -390,7 +343,7 @@ nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t ctrl, uint32_t update) { uint32_t err; - PMD_DRV_LOG(DEBUG, "nfp_net_reconfig: ctrl=%08x update=%08x\n", + PMD_DRV_LOG(DEBUG, "nfp_net_reconfig: ctrl=%08x update=%08x", ctrl, update); rte_spinlock_lock(&hw->reconfig_lock); @@ -427,8 +380,6 @@ nfp_net_configure(struct rte_eth_dev *dev) struct rte_eth_conf *dev_conf; struct rte_eth_rxmode *rxmode; struct rte_eth_txmode *txmode; - uint32_t new_ctrl = 0; - uint32_t update = 0; struct nfp_net_hw *hw; hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private); @@ -454,96 +405,17 @@ nfp_net_configure(struct rte_eth_dev *dev) } /* Checking RX mode */ - if (rxmode->mq_mode & ETH_MQ_RX_RSS) { - if (hw->cap & NFP_NET_CFG_CTRL_RSS) { - update = NFP_NET_CFG_UPDATE_RSS; - new_ctrl = NFP_NET_CFG_CTRL_RSS; - } else { - PMD_INIT_LOG(INFO, "RSS not supported"); - return -EINVAL; - } - } - - if (rxmode->split_hdr_size) { - PMD_INIT_LOG(INFO, "rxmode does not support split header"); - return -EINVAL; - } - - if (rxmode->hw_ip_checksum) { - if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM) { - new_ctrl |= NFP_NET_CFG_CTRL_RXCSUM; - } else { - PMD_INIT_LOG(INFO, "RXCSUM not supported"); - return -EINVAL; - } - } - - if (rxmode->hw_vlan_filter) { - PMD_INIT_LOG(INFO, "VLAN filter not supported"); - return -EINVAL; - } - - if (rxmode->hw_vlan_strip) { - if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN) { - new_ctrl |= NFP_NET_CFG_CTRL_RXVLAN; - } else { - PMD_INIT_LOG(INFO, "hw vlan strip not supported"); - return -EINVAL; - } - } - - if (rxmode->hw_vlan_extend) { - PMD_INIT_LOG(INFO, "VLAN extended not supported"); - return -EINVAL; - } - - if (rxmode->jumbo_frame) - hw->mtu = rxmode->max_rx_pkt_len; - - if (!rxmode->hw_strip_crc) - PMD_INIT_LOG(INFO, "HW does strip CRC and it is not configurable"); - - if (rxmode->enable_scatter) { - PMD_INIT_LOG(INFO, "Scatter not supported"); + if (rxmode->mq_mode & ETH_MQ_RX_RSS && + !(hw->cap & NFP_NET_CFG_CTRL_RSS)) { + PMD_INIT_LOG(INFO, "RSS not supported"); return -EINVAL; } - /* If next capabilities are supported, configure them by default */ - - /* VLAN insertion */ - if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN) - new_ctrl |= NFP_NET_CFG_CTRL_TXVLAN; - - /* L2 broadcast */ - if (hw->cap & NFP_NET_CFG_CTRL_L2BC) - new_ctrl |= NFP_NET_CFG_CTRL_L2BC; - - /* L2 multicast */ - if (hw->cap & NFP_NET_CFG_CTRL_L2MC) - new_ctrl |= NFP_NET_CFG_CTRL_L2MC; - - /* TX checksum offload */ - if (hw->cap & NFP_NET_CFG_CTRL_TXCSUM) - new_ctrl |= NFP_NET_CFG_CTRL_TXCSUM; - - /* LSO offload */ - if (hw->cap & NFP_NET_CFG_CTRL_LSO) - new_ctrl |= NFP_NET_CFG_CTRL_LSO; - - /* RX gather */ - if (hw->cap & NFP_NET_CFG_CTRL_GATHER) - new_ctrl |= NFP_NET_CFG_CTRL_GATHER; - - if (!new_ctrl) - return 0; - - update |= NFP_NET_CFG_UPDATE_GEN; - - nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl); - if (nfp_net_reconfig(hw, new_ctrl, update) < 0) - return -EIO; - - hw->ctrl = new_ctrl; + /* KEEP_CRC offload flag is not supported by PMD + * can remove the below block when DEV_RX_OFFLOAD_CRC_STRIP removed + */ + if (rte_eth_dev_must_keep_crc(rxmode->offloads)) + PMD_INIT_LOG(INFO, "HW does strip CRC. No configurable!"); return 0; } @@ -625,47 +497,29 @@ nfp_net_cfg_queue_setup(struct nfp_net_hw *hw) #define ETH_ADDR_LEN 6 static void -nfp_eth_copy_mac_reverse(uint8_t *dst, const uint8_t *src) +nfp_eth_copy_mac(uint8_t *dst, const uint8_t *src) { int i; for (i = 0; i < ETH_ADDR_LEN; i++) - dst[ETH_ADDR_LEN - i - 1] = src[i]; + dst[i] = src[i]; } static int nfp_net_pf_read_mac(struct nfp_net_hw *hw, int port) { - union eth_table_entry *entry; - int idx, i; - - idx = port; - entry = hw->eth_table; - - /* Reading NFP ethernet table obtained before */ - for (i = 0; i < NSP_ETH_MAX_COUNT; i++) { - if (!(entry->port & NSP_ETH_PORT_LANES_MASK)) { - /* port not in use */ - entry++; - continue; - } - if (idx == 0) - break; - idx--; - entry++; - } - - if (i == NSP_ETH_MAX_COUNT) - return -EINVAL; + struct nfp_eth_table *nfp_eth_table; + nfp_eth_table = nfp_eth_read_ports(hw->cpp); /* * hw points to port0 private data. We need hw now pointing to * right port. */ hw += port; - nfp_eth_copy_mac_reverse((uint8_t *)&hw->mac_addr, - (uint8_t *)&entry->mac_addr); + nfp_eth_copy_mac((uint8_t *)&hw->mac_addr, + (uint8_t *)&nfp_eth_table->ports[port].mac_addr); + free(nfp_eth_table); return 0; } @@ -675,7 +529,7 @@ nfp_net_vf_read_mac(struct nfp_net_hw *hw) uint32_t tmp; tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR)); - memcpy(&hw->mac_addr[0], &tmp, sizeof(struct ether_addr)); + memcpy(&hw->mac_addr[0], &tmp, 4); tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR + 4)); memcpy(&hw->mac_addr[4], &tmp, 2); @@ -695,6 +549,37 @@ nfp_net_write_mac(struct nfp_net_hw *hw, uint8_t *mac) hw->ctrl_bar + NFP_NET_CFG_MACADDR + 6); } +int +nfp_set_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr) +{ + struct nfp_net_hw *hw; + uint32_t update, ctrl; + + hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private); + if ((hw->ctrl & NFP_NET_CFG_CTRL_ENABLE) && + !(hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR)) { + PMD_INIT_LOG(INFO, "MAC address unable to change when" + " port enabled"); + return -EBUSY; + } + + if ((hw->ctrl & NFP_NET_CFG_CTRL_ENABLE) && + !(hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR)) + return -EBUSY; + + /* Writing new MAC to the specific port BAR address */ + nfp_net_write_mac(hw, (uint8_t *)mac_addr); + + /* Signal the NIC about the change */ + update = NFP_NET_CFG_UPDATE_MACADDR; + ctrl = hw->ctrl | NFP_NET_CFG_CTRL_LIVE_ADDR; + if (nfp_net_reconfig(hw, ctrl, update) < 0) { + PMD_INIT_LOG(INFO, "MAC address update failed"); + return -EIO; + } + return 0; +} + static int nfp_configure_rx_interrupt(struct rte_eth_dev *dev, struct rte_intr_handle *intr_handle) @@ -729,7 +614,7 @@ nfp_configure_rx_interrupt(struct rte_eth_dev *dev, */ nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(i), i + 1); intr_handle->intr_vec[i] = i + 1; - PMD_INIT_LOG(DEBUG, "intr_vec[%d]= %d\n", i, + PMD_INIT_LOG(DEBUG, "intr_vec[%d]= %d", i, intr_handle->intr_vec[i]); } } @@ -739,15 +624,75 @@ nfp_configure_rx_interrupt(struct rte_eth_dev *dev, return 0; } +static uint32_t +nfp_check_offloads(struct rte_eth_dev *dev) +{ + struct nfp_net_hw *hw; + struct rte_eth_conf *dev_conf; + struct rte_eth_rxmode *rxmode; + struct rte_eth_txmode *txmode; + uint32_t ctrl = 0; + + hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private); + + dev_conf = &dev->data->dev_conf; + rxmode = &dev_conf->rxmode; + txmode = &dev_conf->txmode; + + if (rxmode->offloads & DEV_RX_OFFLOAD_IPV4_CKSUM) { + if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM) + ctrl |= NFP_NET_CFG_CTRL_RXCSUM; + } + + if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) { + if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN) + ctrl |= NFP_NET_CFG_CTRL_RXVLAN; + } + + if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) + hw->mtu = rxmode->max_rx_pkt_len; + + if (txmode->offloads & DEV_TX_OFFLOAD_VLAN_INSERT) + ctrl |= NFP_NET_CFG_CTRL_TXVLAN; + + /* L2 broadcast */ + if (hw->cap & NFP_NET_CFG_CTRL_L2BC) + ctrl |= NFP_NET_CFG_CTRL_L2BC; + + /* L2 multicast */ + if (hw->cap & NFP_NET_CFG_CTRL_L2MC) + ctrl |= NFP_NET_CFG_CTRL_L2MC; + + /* TX checksum offload */ + if (txmode->offloads & DEV_TX_OFFLOAD_IPV4_CKSUM || + txmode->offloads & DEV_TX_OFFLOAD_UDP_CKSUM || + txmode->offloads & DEV_TX_OFFLOAD_TCP_CKSUM) + ctrl |= NFP_NET_CFG_CTRL_TXCSUM; + + /* LSO offload */ + if (txmode->offloads & DEV_TX_OFFLOAD_TCP_TSO) { + if (hw->cap & NFP_NET_CFG_CTRL_LSO) + ctrl |= NFP_NET_CFG_CTRL_LSO; + else + ctrl |= NFP_NET_CFG_CTRL_LSO2; + } + + /* RX gather */ + if (txmode->offloads & DEV_TX_OFFLOAD_MULTI_SEGS) + ctrl |= NFP_NET_CFG_CTRL_GATHER; + + return ctrl; +} + static int nfp_net_start(struct rte_eth_dev *dev) { struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; - struct rte_eth_conf *dev_conf; - struct rte_eth_rxmode *rxmode; uint32_t new_ctrl, update = 0; struct nfp_net_hw *hw; + struct rte_eth_conf *dev_conf; + struct rte_eth_rxmode *rxmode; uint32_t intr_vector; int ret; @@ -758,9 +703,6 @@ nfp_net_start(struct rte_eth_dev *dev) /* Disabling queues just in case... */ nfp_net_disable_queues(dev); - /* Writing configuration parameters in the device */ - nfp_net_params_setup(hw); - /* Enabling the required queues in the device */ nfp_net_enable_queues(dev); @@ -795,21 +737,22 @@ nfp_net_start(struct rte_eth_dev *dev) rte_intr_enable(intr_handle); + new_ctrl = nfp_check_offloads(dev); + + /* Writing configuration parameters in the device */ + nfp_net_params_setup(hw); + dev_conf = &dev->data->dev_conf; rxmode = &dev_conf->rxmode; - /* Checking RX mode */ if (rxmode->mq_mode & ETH_MQ_RX_RSS) { - if (hw->cap & NFP_NET_CFG_CTRL_RSS) { - if (!nfp_net_rss_config_default(dev)) - update |= NFP_NET_CFG_UPDATE_RSS; - } else { - PMD_INIT_LOG(INFO, "RSS not supported"); - return -EINVAL; - } + nfp_net_rss_config_default(dev); + update |= NFP_NET_CFG_UPDATE_RSS; + new_ctrl |= NFP_NET_CFG_CTRL_RSS; } + /* Enable device */ - new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_ENABLE; + new_ctrl |= NFP_NET_CFG_CTRL_ENABLE; update |= NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING; @@ -831,7 +774,7 @@ nfp_net_start(struct rte_eth_dev *dev) if (hw->is_pf) /* Configure the physical port up */ - nfp_nsp_eth_config(hw->nspu_desc, hw->pf_port_idx, 1); + nfp_eth_set_configured(hw->cpp, hw->pf_port_idx, 1); hw->ctrl = new_ctrl; @@ -882,7 +825,7 @@ nfp_net_stop(struct rte_eth_dev *dev) if (hw->is_pf) /* Configure the physical port down */ - nfp_nsp_eth_config(hw->nspu_desc, hw->pf_port_idx, 0); + nfp_eth_set_configured(hw->cpp, hw->pf_port_idx, 0); } /* Reset and stop device. The device can not be restarted. */ @@ -936,7 +879,7 @@ nfp_net_promisc_enable(struct rte_eth_dev *dev) uint32_t new_ctrl, update = 0; struct nfp_net_hw *hw; - PMD_DRV_LOG(DEBUG, "Promiscuous mode enable\n"); + PMD_DRV_LOG(DEBUG, "Promiscuous mode enable"); hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private); @@ -946,7 +889,7 @@ nfp_net_promisc_enable(struct rte_eth_dev *dev) } if (hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) { - PMD_DRV_LOG(INFO, "Promiscuous mode already enabled\n"); + PMD_DRV_LOG(INFO, "Promiscuous mode already enabled"); return; } @@ -972,7 +915,7 @@ nfp_net_promisc_disable(struct rte_eth_dev *dev) hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private); if ((hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) == 0) { - PMD_DRV_LOG(INFO, "Promiscuous mode already disabled\n"); + PMD_DRV_LOG(INFO, "Promiscuous mode already disabled"); return; } @@ -999,8 +942,9 @@ static int nfp_net_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete) { struct nfp_net_hw *hw; - struct rte_eth_link link, old; + struct rte_eth_link link; uint32_t nn_link_status; + int ret; static const uint32_t ls_to_ethtool[] = { [NFP_NET_CFG_STS_LINK_RATE_UNSUPPORTED] = ETH_SPEED_NUM_NONE, @@ -1013,13 +957,10 @@ nfp_net_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete) [NFP_NET_CFG_STS_LINK_RATE_100G] = ETH_SPEED_NUM_100G, }; - PMD_DRV_LOG(DEBUG, "Link update\n"); + PMD_DRV_LOG(DEBUG, "Link update"); hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private); - memset(&old, 0, sizeof(old)); - nfp_net_dev_atomic_read_link_status(dev, &old); - nn_link_status = nn_cfg_readl(hw, NFP_NET_CFG_STS); memset(&link, 0, sizeof(struct rte_eth_link)); @@ -1037,16 +978,14 @@ nfp_net_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete) else link.link_speed = ls_to_ethtool[nn_link_status]; - if (old.link_status != link.link_status) { - nfp_net_dev_atomic_write_link_status(dev, &link); + ret = rte_eth_linkstatus_set(dev, &link); + if (ret == 0) { if (link.link_status) - PMD_DRV_LOG(INFO, "NIC Link is Up\n"); + PMD_DRV_LOG(INFO, "NIC Link is Up"); else - PMD_DRV_LOG(INFO, "NIC Link is Down\n"); - return 0; + PMD_DRV_LOG(INFO, "NIC Link is Down"); } - - return -1; + return ret; } static int @@ -1214,7 +1153,6 @@ nfp_net_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private); - dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev); dev_info->max_rx_queues = (uint16_t)hw->max_rx_queues; dev_info->max_tx_queues = (uint16_t)hw->max_tx_queues; dev_info->min_rx_bufsize = ETHER_MIN_MTU; @@ -1230,6 +1168,9 @@ nfp_net_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) DEV_RX_OFFLOAD_UDP_CKSUM | DEV_RX_OFFLOAD_TCP_CKSUM; + dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_JUMBO_FRAME | + DEV_RX_OFFLOAD_KEEP_CRC; + if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN) dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT; @@ -1238,6 +1179,12 @@ nfp_net_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) DEV_TX_OFFLOAD_UDP_CKSUM | DEV_TX_OFFLOAD_TCP_CKSUM; + if (hw->cap & NFP_NET_CFG_CTRL_LSO_ANY) + dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_TCP_TSO; + + if (hw->cap & NFP_NET_CFG_CTRL_GATHER) + dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MULTI_SEGS; + dev_info->default_rxconf = (struct rte_eth_rxconf) { .rx_thresh = { .pthresh = DEFAULT_RX_PTHRESH, @@ -1256,8 +1203,6 @@ nfp_net_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) }, .tx_free_thresh = DEFAULT_TX_FREE_THRESH, .tx_rs_thresh = DEFAULT_TX_RSBIT_THRESH, - .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS | - ETH_TXQ_FLAGS_NOOFFLOADS, }; dev_info->flow_type_rss_offloads = ETH_RSS_NONFRAG_IPV4_TCP | @@ -1268,12 +1213,9 @@ nfp_net_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) dev_info->reta_size = NFP_NET_CFG_RSS_ITBL_SZ; dev_info->hash_key_size = NFP_NET_CFG_RSS_KEY_SZ; - dev_info->speed_capa = ETH_SPEED_NUM_1G | ETH_LINK_SPEED_10G | - ETH_SPEED_NUM_25G | ETH_SPEED_NUM_40G | - ETH_SPEED_NUM_50G | ETH_LINK_SPEED_100G; - - if (hw->cap & NFP_NET_CFG_CTRL_LSO) - dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_TCP_TSO; + dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G | + ETH_LINK_SPEED_25G | ETH_LINK_SPEED_40G | + ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G; } static const uint32_t * @@ -1376,18 +1318,17 @@ nfp_net_dev_link_status_print(struct rte_eth_dev *dev) struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); struct rte_eth_link link; - memset(&link, 0, sizeof(link)); - nfp_net_dev_atomic_read_link_status(dev, &link); + rte_eth_linkstatus_get(dev, &link); if (link.link_status) - RTE_LOG(INFO, PMD, "Port %d: Link Up - speed %u Mbps - %s\n", - dev->data->port_id, link.link_speed, - link.link_duplex == ETH_LINK_FULL_DUPLEX - ? "full-duplex" : "half-duplex"); + PMD_DRV_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s", + dev->data->port_id, link.link_speed, + link.link_duplex == ETH_LINK_FULL_DUPLEX + ? "full-duplex" : "half-duplex"); else - RTE_LOG(INFO, PMD, " Port %d: Link Down\n", - dev->data->port_id); + PMD_DRV_LOG(INFO, " Port %d: Link Down", + dev->data->port_id); - RTE_LOG(INFO, PMD, "PCI Address: %04d:%02d:%02d:%d\n", + PMD_DRV_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d", pci_dev->addr.domain, pci_dev->addr.bus, pci_dev->addr.devid, pci_dev->addr.function); } @@ -1428,11 +1369,9 @@ nfp_net_dev_interrupt_handler(void *param) struct rte_eth_link link; struct rte_eth_dev *dev = (struct rte_eth_dev *)param; - PMD_DRV_LOG(DEBUG, "We got a LSC interrupt!!!\n"); + PMD_DRV_LOG(DEBUG, "We got a LSC interrupt!!!"); - /* get the link status */ - memset(&link, 0, sizeof(link)); - nfp_net_dev_atomic_read_link_status(dev, &link); + rte_eth_linkstatus_get(dev, &link); nfp_net_link_update(dev, 0); @@ -1449,7 +1388,7 @@ nfp_net_dev_interrupt_handler(void *param) if (rte_eal_alarm_set(timeout * 1000, nfp_net_dev_interrupt_delayed_handler, (void *)dev) < 0) { - RTE_LOG(ERR, PMD, "Error setting alarm"); + PMD_INIT_LOG(ERR, "Error setting alarm"); /* Unmasking */ nfp_net_irq_unmask(dev); } @@ -1500,9 +1439,9 @@ nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) /* switch to jumbo mode if needed */ if ((uint32_t)mtu > ETHER_MAX_LEN) - dev->data->dev_conf.rxmode.jumbo_frame = 1; + dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_JUMBO_FRAME; else - dev->data->dev_conf.rxmode.jumbo_frame = 0; + dev->data->dev_conf.rxmode.offloads &= ~DEV_RX_OFFLOAD_JUMBO_FRAME; /* update max frame size */ dev->data->dev_conf.rxmode.max_rx_pkt_len = (uint32_t)mtu; @@ -1534,7 +1473,7 @@ nfp_net_rx_queue_setup(struct rte_eth_dev *dev, if (((nb_desc * sizeof(struct nfp_net_rx_desc)) % 128) != 0 || (nb_desc > NFP_NET_MAX_RX_DESC) || (nb_desc < NFP_NET_MIN_RX_DESC)) { - RTE_LOG(ERR, PMD, "Wrong nb_desc value\n"); + PMD_DRV_LOG(ERR, "Wrong nb_desc value"); return -EINVAL; } @@ -1572,8 +1511,6 @@ nfp_net_rx_queue_setup(struct rte_eth_dev *dev, rxq->rx_count = nb_desc; rxq->port_id = dev->data->port_id; rxq->rx_free_thresh = rx_conf->rx_free_thresh; - rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ? 0 - : ETHER_CRC_LEN); rxq->drop_en = rx_conf->rx_drop_en; /* @@ -1587,7 +1524,7 @@ nfp_net_rx_queue_setup(struct rte_eth_dev *dev, socket_id); if (tz == NULL) { - RTE_LOG(ERR, PMD, "Error allocatig rx dma\n"); + PMD_DRV_LOG(ERR, "Error allocatig rx dma"); nfp_net_rx_queue_release(rxq); return -ENOMEM; } @@ -1605,7 +1542,7 @@ nfp_net_rx_queue_setup(struct rte_eth_dev *dev, return -ENOMEM; } - PMD_RX_LOG(DEBUG, "rxbufs=%p hw_ring=%p dma_addr=0x%" PRIx64 "\n", + PMD_RX_LOG(DEBUG, "rxbufs=%p hw_ring=%p dma_addr=0x%" PRIx64, rxq->rxbufs, rxq->rxds, (unsigned long int)rxq->dma); nfp_net_reset_rx_queue(rxq); @@ -1630,7 +1567,7 @@ nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq) uint64_t dma_addr; unsigned i; - PMD_RX_LOG(DEBUG, "nfp_net_rx_fill_freelist for %u descriptors\n", + PMD_RX_LOG(DEBUG, "nfp_net_rx_fill_freelist for %u descriptors", rxq->rx_count); for (i = 0; i < rxq->rx_count; i++) { @@ -1638,7 +1575,7 @@ nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq) struct rte_mbuf *mbuf = rte_pktmbuf_alloc(rxq->mem_pool); if (mbuf == NULL) { - RTE_LOG(ERR, PMD, "RX mbuf alloc failed queue_id=%u\n", + PMD_DRV_LOG(ERR, "RX mbuf alloc failed queue_id=%u", (unsigned)rxq->qidx); return -ENOMEM; } @@ -1650,14 +1587,14 @@ nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq) rxd->fld.dma_addr_hi = (dma_addr >> 32) & 0xff; rxd->fld.dma_addr_lo = dma_addr & 0xffffffff; rxe[i].mbuf = mbuf; - PMD_RX_LOG(DEBUG, "[%d]: %" PRIx64 "\n", i, dma_addr); + PMD_RX_LOG(DEBUG, "[%d]: %" PRIx64, i, dma_addr); } /* Make sure all writes are flushed before telling the hardware */ rte_wmb(); /* Not advertising the whole ring as the firmware gets confused if so */ - PMD_RX_LOG(DEBUG, "Increment FL write pointer in %u\n", + PMD_RX_LOG(DEBUG, "Increment FL write pointer in %u", rxq->rx_count - 1); nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, rxq->rx_count - 1); @@ -1683,7 +1620,7 @@ nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, if (((nb_desc * sizeof(struct nfp_net_tx_desc)) % 128) != 0 || (nb_desc > NFP_NET_MAX_TX_DESC) || (nb_desc < NFP_NET_MIN_TX_DESC)) { - RTE_LOG(ERR, PMD, "Wrong nb_desc value\n"); + PMD_DRV_LOG(ERR, "Wrong nb_desc value"); return -EINVAL; } @@ -1692,10 +1629,10 @@ nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, DEFAULT_TX_FREE_THRESH); if (tx_free_thresh > (nb_desc)) { - RTE_LOG(ERR, PMD, + PMD_DRV_LOG(ERR, "tx_free_thresh must be less than the number of TX " "descriptors. (tx_free_thresh=%u port=%d " - "queue=%d)\n", (unsigned int)tx_free_thresh, + "queue=%d)", (unsigned int)tx_free_thresh, dev->data->port_id, (int)queue_idx); return -(EINVAL); } @@ -1705,7 +1642,7 @@ nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, * calling nfp_net_stop */ if (dev->data->tx_queues[queue_idx]) { - PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d\n", + PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d", queue_idx); nfp_net_tx_queue_release(dev->data->tx_queues[queue_idx]); dev->data->tx_queues[queue_idx] = NULL; @@ -1715,7 +1652,7 @@ nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nfp_net_txq), RTE_CACHE_LINE_SIZE, socket_id); if (txq == NULL) { - RTE_LOG(ERR, PMD, "Error allocating tx dma\n"); + PMD_DRV_LOG(ERR, "Error allocating tx dma"); return -ENOMEM; } @@ -1729,7 +1666,7 @@ nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, NFP_NET_MAX_TX_DESC, NFP_MEMZONE_ALIGN, socket_id); if (tz == NULL) { - RTE_LOG(ERR, PMD, "Error allocating tx dma\n"); + PMD_DRV_LOG(ERR, "Error allocating tx dma"); nfp_net_tx_queue_release(txq); return -ENOMEM; } @@ -1746,7 +1683,6 @@ nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, txq->qcp_q = hw->tx_bar + NFP_QCP_QUEUE_OFF(txq->tx_qcidx); txq->port_id = dev->data->port_id; - txq->txq_flags = tx_conf->txq_flags; /* Saving physical and virtual addresses for the TX ring */ txq->dma = (uint64_t)tz->iova; @@ -1760,7 +1696,7 @@ nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, nfp_net_tx_queue_release(txq); return -ENOMEM; } - PMD_TX_LOG(DEBUG, "txbufs=%p hw_ring=%p dma_addr=0x%" PRIx64 "\n", + PMD_TX_LOG(DEBUG, "txbufs=%p hw_ring=%p dma_addr=0x%" PRIx64, txq->txbufs, txq->txds, (unsigned long int)txq->dma); nfp_net_reset_tx_queue(txq); @@ -1786,7 +1722,7 @@ nfp_net_tx_tso(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd, uint64_t ol_flags; struct nfp_net_hw *hw = txq->hw; - if (!(hw->cap & NFP_NET_CFG_CTRL_LSO)) + if (!(hw->cap & NFP_NET_CFG_CTRL_LSO_ANY)) goto clean_txd; ol_flags = mb->ol_flags; @@ -1794,15 +1730,19 @@ nfp_net_tx_tso(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd, if (!(ol_flags & PKT_TX_TCP_SEG)) goto clean_txd; - txd->l4_offset = mb->l2_len + mb->l3_len + mb->l4_len; - txd->lso = rte_cpu_to_le_16(mb->tso_segsz); + txd->l3_offset = mb->l2_len; + txd->l4_offset = mb->l2_len + mb->l3_len; + txd->lso_hdrlen = mb->l2_len + mb->l3_len + mb->l4_len; + txd->mss = rte_cpu_to_le_16(mb->tso_segsz); txd->flags = PCIE_DESC_TX_LSO; return; clean_txd: txd->flags = 0; + txd->l3_offset = 0; txd->l4_offset = 0; - txd->lso = 0; + txd->lso_hdrlen = 0; + txd->mss = 0; } /* nfp_net_tx_cksum - Set TX CSUM offload flags in TX descriptor */ @@ -1888,14 +1828,10 @@ nfp_net_set_hash(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd, if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS)) return; - if (NFD_CFG_MAJOR_VERSION_of(hw->ver) <= 3) { - if (!(rxd->rxd.flags & PCIE_DESC_RX_RSS)) - return; - - hash = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_OFFSET); - hash_type = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_TYPE_OFFSET); - - } else if (NFP_DESC_META_LEN(rxd)) { + /* this is true for new firmwares */ + if (likely(((hw->cap & NFP_NET_CFG_CTRL_RSS2) || + (NFD_CFG_MAJOR_VERSION_of(hw->ver) == 4)) && + NFP_DESC_META_LEN(rxd))) { /* * new metadata api: * <---- 32 bit -----> @@ -1928,7 +1864,11 @@ nfp_net_set_hash(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd, return; } } else { - return; + if (!(rxd->rxd.flags & PCIE_DESC_RX_RSS)) + return; + + hash = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_OFFSET); + hash_type = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_TYPE_OFFSET); } mbuf->hash.rss = hash; @@ -2019,16 +1959,16 @@ nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) break; } + rxds = &rxq->rxds[rxq->rd_p]; + if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0) + break; + /* * Memory barrier to ensure that we won't do other * reads before the DD bit. */ rte_rmb(); - rxds = &rxq->rxds[rxq->rd_p]; - if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0) - break; - /* * We got a packet. Let's alloc a new mbuff for refilling the * free descriptor ring as soon as possible @@ -2051,7 +1991,7 @@ nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) mb = rxb->mbuf; rxb->mbuf = new_mb; - PMD_RX_LOG(DEBUG, "Packet len: %u, mbuf_size: %u\n", + PMD_RX_LOG(DEBUG, "Packet len: %u, mbuf_size: %u", rxds->rxd.data_len, rxq->mbuf_size); /* Size of this segment */ @@ -2089,6 +2029,8 @@ nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) mb->nb_segs = 1; mb->next = NULL; + mb->port = rxq->port_id; + /* Checking the RSS flag */ nfp_net_set_hash(rxq, rxds, mb); @@ -2120,7 +2062,7 @@ nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) if (nb_hold == 0) return nb_hold; - PMD_RX_LOG(DEBUG, "RX port_id=%u queue_id=%u, %d packets received\n", + PMD_RX_LOG(DEBUG, "RX port_id=%u queue_id=%u, %d packets received", rxq->port_id, (unsigned int)rxq->qidx, nb_hold); nb_hold += rxq->nb_rx_hold; @@ -2131,7 +2073,7 @@ nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) */ rte_wmb(); if (nb_hold > rxq->rx_free_thresh) { - PMD_RX_LOG(DEBUG, "port=%u queue=%u nb_hold=%u avail=%u\n", + PMD_RX_LOG(DEBUG, "port=%u queue=%u nb_hold=%u avail=%u", rxq->port_id, (unsigned int)rxq->qidx, (unsigned)nb_hold, (unsigned)avail); nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, nb_hold); @@ -2155,14 +2097,14 @@ nfp_net_tx_free_bufs(struct nfp_net_txq *txq) int todo; PMD_TX_LOG(DEBUG, "queue %u. Check for descriptor with a complete" - " status\n", txq->qidx); + " status", txq->qidx); /* Work out how many packets have been sent */ qcp_rd_p = nfp_qcp_read(txq->qcp_q, NFP_QCP_READ_PTR); if (qcp_rd_p == txq->rd_p) { PMD_TX_LOG(DEBUG, "queue %u: It seems harrier is not sending " - "packets (%u, %u)\n", txq->qidx, + "packets (%u, %u)", txq->qidx, qcp_rd_p, txq->rd_p); return 0; } @@ -2172,7 +2114,7 @@ nfp_net_tx_free_bufs(struct nfp_net_txq *txq) else todo = qcp_rd_p + txq->tx_count - txq->rd_p; - PMD_TX_LOG(DEBUG, "qcp_rd_p %u, txq->rd_p: %u, qcp->rd_p: %u\n", + PMD_TX_LOG(DEBUG, "qcp_rd_p %u, txq->rd_p: %u, qcp->rd_p: %u", qcp_rd_p, txq->rd_p, txq->rd_p); if (todo == 0) @@ -2226,7 +2168,7 @@ nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts) hw = txq->hw; txds = &txq->txds[txq->wr_p]; - PMD_TX_LOG(DEBUG, "working for queue %u at pos %d and %u packets\n", + PMD_TX_LOG(DEBUG, "working for queue %u at pos %d and %u packets", txq->qidx, txq->wr_p, nb_pkts); if ((nfp_free_tx_desc(txq) < nb_pkts) || (nfp_net_txq_full(txq))) @@ -2240,7 +2182,7 @@ nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts) i = 0; issued_descs = 0; - PMD_TX_LOG(DEBUG, "queue: %u. Sending %u packets\n", + PMD_TX_LOG(DEBUG, "queue: %u. Sending %u packets", txq->qidx, nb_pkts); /* Sending packets */ while ((i < nb_pkts) && free_descs) { @@ -2299,7 +2241,7 @@ nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts) dma_size = pkt->data_len; dma_addr = rte_mbuf_data_iova(pkt); PMD_TX_LOG(DEBUG, "Working with mbuf at dma address:" - "%" PRIx64 "\n", dma_addr); + "%" PRIx64 "", dma_addr); /* Filling descriptors fields */ txds->dma_len = dma_size; @@ -2314,11 +2256,15 @@ nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts) txq->wr_p = 0; pkt_size -= dma_size; - if (!pkt_size) - /* End of packet */ - txds->offset_eop |= PCIE_DESC_TX_EOP; + + /* + * Making the EOP, packets with just one segment + * the priority + */ + if (likely(!pkt_size)) + txds->offset_eop = PCIE_DESC_TX_EOP; else - txds->offset_eop &= PCIE_DESC_TX_OFFSET_MASK; + txds->offset_eop = 0; pkt = pkt->next; /* Referencing next free TX descriptor */ @@ -2349,7 +2295,7 @@ nfp_net_vlan_offload_set(struct rte_eth_dev *dev, int mask) if ((mask & ETH_VLAN_FILTER_OFFLOAD) || (mask & ETH_VLAN_EXTEND_OFFLOAD)) - RTE_LOG(INFO, PMD, "No support for ETH_VLAN_FILTER_OFFLOAD or" + PMD_DRV_LOG(INFO, "No support for ETH_VLAN_FILTER_OFFLOAD or" " ETH_VLAN_EXTEND_OFFLOAD"); /* Enable vlan strip if it is not configured yet */ @@ -2386,9 +2332,9 @@ nfp_net_rss_reta_write(struct rte_eth_dev *dev, NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private); if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) { - RTE_LOG(ERR, PMD, "The size of hash lookup table configured " + PMD_DRV_LOG(ERR, "The size of hash lookup table configured " "(%d) doesn't match the number hardware can supported " - "(%d)\n", reta_size, NFP_NET_CFG_RSS_ITBL_SZ); + "(%d)", reta_size, NFP_NET_CFG_RSS_ITBL_SZ); return -EINVAL; } @@ -2467,9 +2413,9 @@ nfp_net_reta_query(struct rte_eth_dev *dev, return -EINVAL; if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) { - RTE_LOG(ERR, PMD, "The size of hash lookup table configured " + PMD_DRV_LOG(ERR, "The size of hash lookup table configured " "(%d) doesn't match the number hardware can supported " - "(%d)\n", reta_size, NFP_NET_CFG_RSS_ITBL_SZ); + "(%d)", reta_size, NFP_NET_CFG_RSS_ITBL_SZ); return -EINVAL; } @@ -2555,14 +2501,14 @@ nfp_net_rss_hash_update(struct rte_eth_dev *dev, /* Checking if RSS is enabled */ if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS)) { if (rss_hf != 0) { /* Enable RSS? */ - RTE_LOG(ERR, PMD, "RSS unsupported\n"); + PMD_DRV_LOG(ERR, "RSS unsupported"); return -EINVAL; } return 0; /* Nothing to do */ } if (rss_conf->rss_key_len > NFP_NET_CFG_RSS_KEY_SZ) { - RTE_LOG(ERR, PMD, "hash key too long\n"); + PMD_DRV_LOG(ERR, "hash key too long"); return -EINVAL; } @@ -2634,7 +2580,7 @@ nfp_net_rss_config_default(struct rte_eth_dev *dev) uint16_t queue; int i, j, ret; - RTE_LOG(INFO, PMD, "setting default RSS conf for %u queues\n", + PMD_DRV_LOG(INFO, "setting default RSS conf for %u queues", rx_queues); nfp_reta_conf[0].mask = ~0x0; @@ -2654,7 +2600,7 @@ nfp_net_rss_config_default(struct rte_eth_dev *dev) dev_conf = &dev->data->dev_conf; if (!dev_conf) { - RTE_LOG(INFO, PMD, "wrong rss conf"); + PMD_DRV_LOG(INFO, "wrong rss conf"); return -EINVAL; } rss_conf = dev_conf->rx_adv_conf.rss_conf; @@ -2679,6 +2625,7 @@ static const struct eth_dev_ops nfp_net_eth_dev_ops = { .dev_infos_get = nfp_net_infos_get, .dev_supported_ptypes_get = nfp_net_supported_ptypes_get, .mtu_set = nfp_net_dev_mtu_set, + .mac_addr_set = nfp_set_mac_addr, .vlan_offload_set = nfp_net_vlan_offload_set, .reta_update = nfp_net_reta_update, .reta_query = nfp_net_reta_query, @@ -2734,10 +2681,8 @@ nfp_net_init(struct rte_eth_dev *eth_dev) uint64_t tx_bar_off = 0, rx_bar_off = 0; uint32_t start_q; int stride = 4; - - nspu_desc_t *nspu_desc = NULL; - uint64_t bar_offset; int port = 0; + int err; PMD_INIT_FUNC_TRACE(); @@ -2747,18 +2692,17 @@ nfp_net_init(struct rte_eth_dev *eth_dev) (pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC)) { port = get_pf_port_number(eth_dev->data->name); if (port < 0 || port > 7) { - RTE_LOG(ERR, PMD, "Port value is wrong\n"); + PMD_DRV_LOG(ERR, "Port value is wrong"); return -ENODEV; } - PMD_INIT_LOG(DEBUG, "Working with PF port value %d\n", port); + PMD_INIT_LOG(DEBUG, "Working with PF port value %d", port); /* This points to port 0 private data */ hwport0 = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); /* This points to the specific port private data */ hw = &hwport0[port]; - hw->pf_port_idx = port; } else { hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); hwport0 = 0; @@ -2786,26 +2730,21 @@ nfp_net_init(struct rte_eth_dev *eth_dev) hw->ctrl_bar = (uint8_t *)pci_dev->mem_resource[0].addr; if (hw->ctrl_bar == NULL) { - RTE_LOG(ERR, PMD, - "hw->ctrl_bar is NULL. BAR0 not configured\n"); + PMD_DRV_LOG(ERR, + "hw->ctrl_bar is NULL. BAR0 not configured"); return -ENODEV; } if (hw->is_pf && port == 0) { - nspu_desc = hw->nspu_desc; - - if (nfp_nsp_map_ctrl_bar(nspu_desc, &bar_offset) != 0) { - /* - * A firmware should be there after PF probe so this - * should not happen. - */ - RTE_LOG(ERR, PMD, "PF BAR symbol resolution failed\n"); - return -ENODEV; + hw->ctrl_bar = nfp_rtsym_map(hw->sym_tbl, "_pf0_net_bar0", + hw->total_ports * 32768, + &hw->ctrl_area); + if (!hw->ctrl_bar) { + printf("nfp_rtsym_map fails for _pf0_net_ctrl_bar"); + return -EIO; } - /* vNIC PF control BAR is a subset of PF PCI device BAR */ - hw->ctrl_bar += bar_offset; - PMD_INIT_LOG(DEBUG, "ctrl bar: %p\n", hw->ctrl_bar); + PMD_INIT_LOG(DEBUG, "ctrl bar: %p", hw->ctrl_bar); } if (port > 0) { @@ -2817,7 +2756,7 @@ nfp_net_init(struct rte_eth_dev *eth_dev) (port * NFP_PF_CSR_SLICE_SIZE); } - PMD_INIT_LOG(DEBUG, "ctrl bar: %p\n", hw->ctrl_bar); + PMD_INIT_LOG(DEBUG, "ctrl bar: %p", hw->ctrl_bar); hw->max_rx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_RXRINGS); hw->max_tx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_TXRINGS); @@ -2828,31 +2767,34 @@ nfp_net_init(struct rte_eth_dev *eth_dev) case PCI_DEVICE_ID_NFP6000_PF_NIC: case PCI_DEVICE_ID_NFP6000_VF_NIC: start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_TXQ); - tx_bar_off = NFP_PCIE_QUEUE(start_q); + tx_bar_off = start_q * NFP_QCP_QUEUE_ADDR_SZ; start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_RXQ); - rx_bar_off = NFP_PCIE_QUEUE(start_q); + rx_bar_off = start_q * NFP_QCP_QUEUE_ADDR_SZ; break; default: - RTE_LOG(ERR, PMD, "nfp_net: no device ID matching\n"); - return -ENODEV; + PMD_DRV_LOG(ERR, "nfp_net: no device ID matching"); + err = -ENODEV; + goto dev_err_ctrl_map; } - PMD_INIT_LOG(DEBUG, "tx_bar_off: 0x%" PRIx64 "\n", tx_bar_off); - PMD_INIT_LOG(DEBUG, "rx_bar_off: 0x%" PRIx64 "\n", rx_bar_off); + PMD_INIT_LOG(DEBUG, "tx_bar_off: 0x%" PRIx64 "", tx_bar_off); + PMD_INIT_LOG(DEBUG, "rx_bar_off: 0x%" PRIx64 "", rx_bar_off); if (hw->is_pf && port == 0) { /* configure access to tx/rx vNIC BARs */ - nfp_nsp_map_queues_bar(nspu_desc, &bar_offset); - PMD_INIT_LOG(DEBUG, "tx/rx bar_offset: %" PRIx64 "\n", - bar_offset); - hwport0->hw_queues = (uint8_t *)pci_dev->mem_resource[0].addr; - - /* vNIC PF tx/rx BARs are a subset of PF PCI device */ - hwport0->hw_queues += bar_offset; + hwport0->hw_queues = nfp_cpp_map_area(hw->cpp, 0, 0, + NFP_PCIE_QUEUE(0), + NFP_QCP_QUEUE_AREA_SZ, + &hw->hwqueues_area); + + if (!hwport0->hw_queues) { + printf("nfp_rtsym_map fails for net.qc"); + err = -EIO; + goto dev_err_ctrl_map; + } - /* Lets seize the chance to read eth table from hw */ - if (nfp_nsp_eth_read_table(nspu_desc, &hw->eth_table)) - return -ENODEV; + PMD_INIT_LOG(DEBUG, "tx/rx bar address: 0x%p", + hwport0->hw_queues); } if (hw->is_pf) { @@ -2877,14 +2819,20 @@ nfp_net_init(struct rte_eth_dev *eth_dev) hw->max_mtu = nn_cfg_readl(hw, NFP_NET_CFG_MAX_MTU); hw->mtu = ETHER_MTU; + /* VLAN insertion is incompatible with LSOv2 */ + if (hw->cap & NFP_NET_CFG_CTRL_LSO2) + hw->cap &= ~NFP_NET_CFG_CTRL_TXVLAN; + if (NFD_CFG_MAJOR_VERSION_of(hw->ver) < 2) hw->rx_offset = NFP_NET_RX_OFFSET; else hw->rx_offset = nn_cfg_readl(hw, NFP_NET_CFG_RX_OFFSET_ADDR); - PMD_INIT_LOG(INFO, "VER: %#x, Maximum supported MTU: %d", - hw->ver, hw->max_mtu); - PMD_INIT_LOG(INFO, "CAP: %#x, %s%s%s%s%s%s%s%s%s%s%s", hw->cap, + PMD_INIT_LOG(INFO, "VER: %u.%u, Maximum supported MTU: %d", + NFD_CFG_MAJOR_VERSION_of(hw->ver), + NFD_CFG_MINOR_VERSION_of(hw->ver), hw->max_mtu); + + PMD_INIT_LOG(INFO, "CAP: %#x, %s%s%s%s%s%s%s%s%s%s%s%s%s%s", hw->cap, hw->cap & NFP_NET_CFG_CTRL_PROMISC ? "PROMISC " : "", hw->cap & NFP_NET_CFG_CTRL_L2BC ? "L2BCFILT " : "", hw->cap & NFP_NET_CFG_CTRL_L2MC ? "L2MCFILT " : "", @@ -2894,8 +2842,11 @@ nfp_net_init(struct rte_eth_dev *eth_dev) hw->cap & NFP_NET_CFG_CTRL_TXVLAN ? "TXVLAN " : "", hw->cap & NFP_NET_CFG_CTRL_SCATTER ? "SCATTER " : "", hw->cap & NFP_NET_CFG_CTRL_GATHER ? "GATHER " : "", + hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR ? "LIVE_ADDR " : "", hw->cap & NFP_NET_CFG_CTRL_LSO ? "TSO " : "", - hw->cap & NFP_NET_CFG_CTRL_RSS ? "RSS " : ""); + hw->cap & NFP_NET_CFG_CTRL_LSO2 ? "TSOv2 " : "", + hw->cap & NFP_NET_CFG_CTRL_RSS ? "RSS " : "", + hw->cap & NFP_NET_CFG_CTRL_RSS2 ? "RSSv2 " : ""); hw->ctrl = 0; @@ -2912,7 +2863,8 @@ nfp_net_init(struct rte_eth_dev *eth_dev) eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", ETHER_ADDR_LEN, 0); if (eth_dev->data->mac_addrs == NULL) { PMD_INIT_LOG(ERR, "Failed to space for MAC address"); - return -ENOMEM; + err = -ENOMEM; + goto dev_err_queues_map; } if (hw->is_pf) { @@ -2923,6 +2875,8 @@ nfp_net_init(struct rte_eth_dev *eth_dev) } if (!is_valid_assigned_ether_addr((struct ether_addr *)&hw->mac_addr)) { + PMD_INIT_LOG(INFO, "Using random mac address for port %d", + port); /* Using random mac addresses for VFs */ eth_random_addr(&hw->mac_addr[0]); nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr); @@ -2951,11 +2905,19 @@ nfp_net_init(struct rte_eth_dev *eth_dev) nfp_net_stats_reset(eth_dev); return 0; + +dev_err_queues_map: + nfp_cpp_area_free(hw->hwqueues_area); +dev_err_ctrl_map: + nfp_cpp_area_free(hw->ctrl_area); + + return err; } static int nfp_pf_create_dev(struct rte_pci_device *dev, int port, int ports, - nfpu_desc_t *nfpu_desc, void **priv) + struct nfp_cpp *cpp, struct nfp_hwinfo *hwinfo, + int phys_port, struct nfp_rtsym_table *sym_tbl, void **priv) { struct rte_eth_dev *eth_dev; struct nfp_net_hw *hw; @@ -2993,12 +2955,16 @@ nfp_pf_create_dev(struct rte_pci_device *dev, int port, int ports, * Then dev_private is adjusted per port. */ hw = (struct nfp_net_hw *)(eth_dev->data->dev_private) + port; - hw->nspu_desc = nfpu_desc->nspu; - hw->nfpu_desc = nfpu_desc; + hw->cpp = cpp; + hw->hwinfo = hwinfo; + hw->sym_tbl = sym_tbl; + hw->pf_port_idx = phys_port; hw->is_pf = 1; if (ports > 1) hw->pf_multiport_enabled = 1; + hw->total_ports = ports; + eth_dev->device = &dev->device; rte_eth_copy_pci_info(eth_dev, dev); @@ -3006,82 +2972,228 @@ nfp_pf_create_dev(struct rte_pci_device *dev, int port, int ports, if (ret) rte_eth_dev_release_port(eth_dev); + else + rte_eth_dev_probing_finish(eth_dev); rte_free(port_name); return ret; } +#define DEFAULT_FW_PATH "/lib/firmware/netronome" + +static int +nfp_fw_upload(struct rte_pci_device *dev, struct nfp_nsp *nsp, char *card) +{ + struct nfp_cpp *cpp = nsp->cpp; + int fw_f; + char *fw_buf; + char fw_name[125]; + char serial[40]; + struct stat file_stat; + off_t fsize, bytes; + + /* Looking for firmware file in order of priority */ + + /* First try to find a firmware image specific for this device */ + sprintf(serial, "serial-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x", + cpp->serial[0], cpp->serial[1], cpp->serial[2], cpp->serial[3], + cpp->serial[4], cpp->serial[5], cpp->interface >> 8, + cpp->interface & 0xff); + + sprintf(fw_name, "%s/%s.nffw", DEFAULT_FW_PATH, serial); + + PMD_DRV_LOG(DEBUG, "Trying with fw file: %s", fw_name); + fw_f = open(fw_name, O_RDONLY); + if (fw_f > 0) + goto read_fw; + + /* Then try the PCI name */ + sprintf(fw_name, "%s/pci-%s.nffw", DEFAULT_FW_PATH, dev->device.name); + + PMD_DRV_LOG(DEBUG, "Trying with fw file: %s", fw_name); + fw_f = open(fw_name, O_RDONLY); + if (fw_f > 0) + goto read_fw; + + /* Finally try the card type and media */ + sprintf(fw_name, "%s/%s", DEFAULT_FW_PATH, card); + PMD_DRV_LOG(DEBUG, "Trying with fw file: %s", fw_name); + fw_f = open(fw_name, O_RDONLY); + if (fw_f < 0) { + PMD_DRV_LOG(INFO, "Firmware file %s not found.", fw_name); + return -ENOENT; + } + +read_fw: + if (fstat(fw_f, &file_stat) < 0) { + PMD_DRV_LOG(INFO, "Firmware file %s size is unknown", fw_name); + close(fw_f); + return -ENOENT; + } + + fsize = file_stat.st_size; + PMD_DRV_LOG(INFO, "Firmware file found at %s with size: %" PRIu64 "", + fw_name, (uint64_t)fsize); + + fw_buf = malloc((size_t)fsize); + if (!fw_buf) { + PMD_DRV_LOG(INFO, "malloc failed for fw buffer"); + close(fw_f); + return -ENOMEM; + } + memset(fw_buf, 0, fsize); + + bytes = read(fw_f, fw_buf, fsize); + if (bytes != fsize) { + PMD_DRV_LOG(INFO, "Reading fw to buffer failed." + "Just %" PRIu64 " of %" PRIu64 " bytes read", + (uint64_t)bytes, (uint64_t)fsize); + free(fw_buf); + close(fw_f); + return -EIO; + } + + PMD_DRV_LOG(INFO, "Uploading the firmware ..."); + nfp_nsp_load_fw(nsp, fw_buf, bytes); + PMD_DRV_LOG(INFO, "Done"); + + free(fw_buf); + close(fw_f); + + return 0; +} + +static int +nfp_fw_setup(struct rte_pci_device *dev, struct nfp_cpp *cpp, + struct nfp_eth_table *nfp_eth_table, struct nfp_hwinfo *hwinfo) +{ + struct nfp_nsp *nsp; + const char *nfp_fw_model; + char card_desc[100]; + int err = 0; + + nfp_fw_model = nfp_hwinfo_lookup(hwinfo, "assembly.partno"); + + if (nfp_fw_model) { + PMD_DRV_LOG(INFO, "firmware model found: %s", nfp_fw_model); + } else { + PMD_DRV_LOG(ERR, "firmware model NOT found"); + return -EIO; + } + + if (nfp_eth_table->count == 0 || nfp_eth_table->count > 8) { + PMD_DRV_LOG(ERR, "NFP ethernet table reports wrong ports: %u", + nfp_eth_table->count); + return -EIO; + } + + PMD_DRV_LOG(INFO, "NFP ethernet port table reports %u ports", + nfp_eth_table->count); + + PMD_DRV_LOG(INFO, "Port speed: %u", nfp_eth_table->ports[0].speed); + + sprintf(card_desc, "nic_%s_%dx%d.nffw", nfp_fw_model, + nfp_eth_table->count, nfp_eth_table->ports[0].speed / 1000); + + nsp = nfp_nsp_open(cpp); + if (!nsp) { + PMD_DRV_LOG(ERR, "NFP error when obtaining NSP handle"); + return -EIO; + } + + nfp_nsp_device_soft_reset(nsp); + err = nfp_fw_upload(dev, nsp, card_desc); + + nfp_nsp_close(nsp); + return err; +} + static int nfp_pf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, struct rte_pci_device *dev) { - nfpu_desc_t *nfpu_desc; - nspu_desc_t *nspu_desc; - uint64_t offset_symbol; - uint8_t *bar_offset; - int major, minor; + struct nfp_cpp *cpp; + struct nfp_hwinfo *hwinfo; + struct nfp_rtsym_table *sym_tbl; + struct nfp_eth_table *nfp_eth_table = NULL; int total_ports; void *priv = 0; int ret = -ENODEV; + int err; int i; if (!dev) return ret; - nfpu_desc = rte_malloc("nfp nfpu", sizeof(nfpu_desc_t), 0); - if (!nfpu_desc) - return -ENOMEM; + /* + * When device bound to UIO, the device could be used, by mistake, + * by two DPDK apps, and the UIO driver does not avoid it. This + * could lead to a serious problem when configuring the NFP CPP + * interface. Here we avoid this telling to the CPP init code to + * use a lock file if UIO is being used. + */ + if (dev->kdrv == RTE_KDRV_VFIO) + cpp = nfp_cpp_from_device_name(dev, 0); + else + cpp = nfp_cpp_from_device_name(dev, 1); - if (nfpu_open(dev, nfpu_desc, 0) < 0) { - RTE_LOG(ERR, PMD, - "nfpu_open failed\n"); - goto nfpu_error; + if (!cpp) { + PMD_DRV_LOG(ERR, "A CPP handle can not be obtained"); + ret = -EIO; + goto error; } - nspu_desc = nfpu_desc->nspu; + hwinfo = nfp_hwinfo_read(cpp); + if (!hwinfo) { + PMD_DRV_LOG(ERR, "Error reading hwinfo table"); + return -EIO; + } + nfp_eth_table = nfp_eth_read_ports(cpp); + if (!nfp_eth_table) { + PMD_DRV_LOG(ERR, "Error reading NFP ethernet table"); + return -EIO; + } - /* Check NSP ABI version */ - if (nfp_nsp_get_abi_version(nspu_desc, &major, &minor) < 0) { - RTE_LOG(INFO, PMD, "NFP NSP not present\n"); + if (nfp_fw_setup(dev, cpp, nfp_eth_table, hwinfo)) { + PMD_DRV_LOG(INFO, "Error when uploading firmware"); + ret = -EIO; goto error; } - PMD_INIT_LOG(INFO, "nspu ABI version: %d.%d\n", major, minor); - if ((major == 0) && (minor < 20)) { - RTE_LOG(INFO, PMD, "NFP NSP ABI version too old. Required 0.20 or higher\n"); + /* Now the symbol table should be there */ + sym_tbl = nfp_rtsym_table_read(cpp); + if (!sym_tbl) { + PMD_DRV_LOG(ERR, "Something is wrong with the firmware" + " symbol table"); + ret = -EIO; goto error; } - ret = nfp_nsp_fw_setup(nspu_desc, "nfd_cfg_pf0_num_ports", - &offset_symbol); - if (ret) + total_ports = nfp_rtsym_read_le(sym_tbl, "nfd_cfg_pf0_num_ports", &err); + if (total_ports != (int)nfp_eth_table->count) { + PMD_DRV_LOG(ERR, "Inconsistent number of ports"); + ret = -EIO; goto error; - - bar_offset = (uint8_t *)dev->mem_resource[0].addr; - bar_offset += offset_symbol; - total_ports = (uint32_t)*bar_offset; - PMD_INIT_LOG(INFO, "Total pf ports: %d\n", total_ports); + } + PMD_INIT_LOG(INFO, "Total pf ports: %d", total_ports); if (total_ports <= 0 || total_ports > 8) { - RTE_LOG(ERR, PMD, "nfd_cfg_pf0_num_ports symbol with wrong value"); + PMD_DRV_LOG(ERR, "nfd_cfg_pf0_num_ports symbol with wrong value"); ret = -ENODEV; goto error; } for (i = 0; i < total_ports; i++) { - ret = nfp_pf_create_dev(dev, i, total_ports, nfpu_desc, &priv); + ret = nfp_pf_create_dev(dev, i, total_ports, cpp, hwinfo, + nfp_eth_table->ports[i].index, + sym_tbl, &priv); if (ret) - goto error; + break; } - return 0; - error: - nfpu_close(nfpu_desc); -nfpu_error: - rte_free(nfpu_desc); - + free(nfp_eth_table); return ret; } @@ -3129,8 +3241,19 @@ static int eth_nfp_pci_remove(struct rte_pci_device *pci_dev) if ((pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC) || (pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC)) { port = get_pf_port_number(eth_dev->data->name); + /* + * hotplug is not possible with multiport PF although freeing + * data structures can be done for first port. + */ + if (port != 0) + return -ENOTSUP; hwport0 = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); hw = &hwport0[port]; + nfp_cpp_area_free(hw->ctrl_area); + nfp_cpp_area_free(hw->hwqueues_area); + free(hw->hwinfo); + free(hw->sym_tbl); + nfp_cpp_free(hw->cpp); } else { hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); } @@ -3161,9 +3284,7 @@ RTE_PMD_REGISTER_PCI_TABLE(net_nfp_vf, pci_id_nfp_vf_net_map); RTE_PMD_REGISTER_KMOD_DEP(net_nfp_pf, "* igb_uio | uio_pci_generic | vfio"); RTE_PMD_REGISTER_KMOD_DEP(net_nfp_vf, "* igb_uio | uio_pci_generic | vfio"); -RTE_INIT(nfp_init_log); -static void -nfp_init_log(void) +RTE_INIT(nfp_init_log) { nfp_logtype_init = rte_log_register("pmd.net.nfp.init"); if (nfp_logtype_init >= 0) diff --git a/drivers/net/nfp/nfp_net_ctrl.h b/drivers/net/nfp/nfp_net_ctrl.h index 1ebd99ca..21e17da1 100644 --- a/drivers/net/nfp/nfp_net_ctrl.h +++ b/drivers/net/nfp/nfp_net_ctrl.h @@ -120,6 +120,9 @@ #define NFP_NET_CFG_CTRL_VXLAN (0x1 << 24) /* Enable VXLAN */ #define NFP_NET_CFG_CTRL_NVGRE (0x1 << 25) /* Enable NVGRE */ #define NFP_NET_CFG_CTRL_MSIX_TX_OFF (0x1 << 26) /* Disable MSIX for TX */ +#define NFP_NET_CFG_CTRL_LSO2 (0x1 << 28) /* LSO/TSO (version 2) */ +#define NFP_NET_CFG_CTRL_RSS2 (0x1 << 29) /* RSS (version 2) */ +#define NFP_NET_CFG_CTRL_LIVE_ADDR (0x1 << 31) /* live MAC addr change */ #define NFP_NET_CFG_UPDATE 0x0004 #define NFP_NET_CFG_UPDATE_GEN (0x1 << 0) /* General update */ #define NFP_NET_CFG_UPDATE_RING (0x1 << 1) /* Ring config change */ @@ -131,6 +134,7 @@ #define NFP_NET_CFG_UPDATE_RESET (0x1 << 7) /* Update due to FLR */ #define NFP_NET_CFG_UPDATE_IRQMOD (0x1 << 8) /* IRQ mod change */ #define NFP_NET_CFG_UPDATE_VXLAN (0x1 << 9) /* VXLAN port change */ +#define NFP_NET_CFG_UPDATE_MACADDR (0x1 << 11) /* MAC address change */ #define NFP_NET_CFG_UPDATE_ERR (0x1 << 31) /* A error occurred */ #define NFP_NET_CFG_TXRS_ENABLE 0x0008 #define NFP_NET_CFG_RXRS_ENABLE 0x0010 @@ -140,6 +144,8 @@ #define NFP_NET_CFG_LSC 0x0020 #define NFP_NET_CFG_MACADDR 0x0024 +#define NFP_NET_CFG_CTRL_LSO_ANY (NFP_NET_CFG_CTRL_LSO | NFP_NET_CFG_CTRL_LSO2) + /* * Read-only words (0x0030 - 0x0050): * @NFP_NET_CFG_VERSION: Firmware version number diff --git a/drivers/net/nfp/nfp_net_eth.h b/drivers/net/nfp/nfp_net_eth.h deleted file mode 100644 index af57f03c..00000000 --- a/drivers/net/nfp/nfp_net_eth.h +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Copyright (c) 2017 Netronome Systems, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * vim:shiftwidth=8:noexpandtab - * - * @file dpdk/pmd/nfp_net_eth.h - * - * Netronome NFP_NET PDM driver - */ - -union eth_table_entry { - struct { - uint64_t port; - uint64_t state; - uint8_t mac_addr[6]; - uint8_t resv[2]; - uint64_t control; - }; - uint64_t raw[4]; -}; - -#ifndef BIT_ULL -#define BIT_ULL(a) (1ULL << (a)) -#endif - -#define NSP_ETH_NBI_PORT_COUNT 24 -#define NSP_ETH_MAX_COUNT (2 * NSP_ETH_NBI_PORT_COUNT) -#define NSP_ETH_TABLE_SIZE (NSP_ETH_MAX_COUNT * sizeof(union eth_table_entry)) - -#define NSP_ETH_PORT_LANES 0xf -#define NSP_ETH_PORT_INDEX 0xff00 -#define NSP_ETH_PORT_LABEL 0x3f000000000000 -#define NSP_ETH_PORT_PHYLABEL 0xfc0000000000000 - -#define NSP_ETH_PORT_LANES_MASK rte_cpu_to_le_64(NSP_ETH_PORT_LANES) - -#define NSP_ETH_STATE_CONFIGURED BIT_ULL(0) -#define NSP_ETH_STATE_ENABLED BIT_ULL(1) -#define NSP_ETH_STATE_TX_ENABLED BIT_ULL(2) -#define NSP_ETH_STATE_RX_ENABLED BIT_ULL(3) -#define NSP_ETH_STATE_RATE 0xf00 -#define NSP_ETH_STATE_INTERFACE 0xff000 -#define NSP_ETH_STATE_MEDIA 0x300000 -#define NSP_ETH_STATE_OVRD_CHNG BIT_ULL(22) -#define NSP_ETH_STATE_ANEG 0x3800000 - -#define NSP_ETH_CTRL_CONFIGURED BIT_ULL(0) -#define NSP_ETH_CTRL_ENABLED BIT_ULL(1) -#define NSP_ETH_CTRL_TX_ENABLED BIT_ULL(2) -#define NSP_ETH_CTRL_RX_ENABLED BIT_ULL(3) -#define NSP_ETH_CTRL_SET_RATE BIT_ULL(4) -#define NSP_ETH_CTRL_SET_LANES BIT_ULL(5) -#define NSP_ETH_CTRL_SET_ANEG BIT_ULL(6) diff --git a/drivers/net/nfp/nfp_net_logs.h b/drivers/net/nfp/nfp_net_logs.h index 3fe24e96..9952881c 100644 --- a/drivers/net/nfp/nfp_net_logs.h +++ b/drivers/net/nfp/nfp_net_logs.h @@ -36,19 +36,20 @@ extern int nfp_logtype_init; #define PMD_INIT_LOG(level, fmt, args...) \ - RTE_LOG(level, PMD, "%s(): " fmt "\n", __func__, ## args) + rte_log(RTE_LOG_ ## level, nfp_logtype_init, \ + "%s(): " fmt "\n", __func__, ## args) #define PMD_INIT_FUNC_TRACE() PMD_INIT_LOG(DEBUG, " >>") #ifdef RTE_LIBRTE_NFP_NET_DEBUG_RX #define PMD_RX_LOG(level, fmt, args...) \ - RTE_LOG(level, PMD, "%s() rx: " fmt, __func__, ## args) + RTE_LOG(level, PMD, "%s() rx: " fmt "\n", __func__, ## args) #else #define PMD_RX_LOG(level, fmt, args...) do { } while (0) #endif #ifdef RTE_LIBRTE_NFP_NET_DEBUG_TX #define PMD_TX_LOG(level, fmt, args...) \ - RTE_LOG(level, PMD, "%s() tx: " fmt, __func__, ## args) + RTE_LOG(level, PMD, "%s() tx: " fmt "\n", __func__, ## args) #define ASSERT(x) if (!(x)) rte_panic("NFP_NET: x") #else #define PMD_TX_LOG(level, fmt, args...) do { } while (0) @@ -58,6 +59,6 @@ extern int nfp_logtype_init; extern int nfp_logtype_driver; #define PMD_DRV_LOG(level, fmt, args...) \ rte_log(RTE_LOG_ ## level, nfp_logtype_driver, \ - "%s(): " fmt, __func__, ## args) + "%s(): " fmt "\n", __func__, ## args) #endif /* _NFP_NET_LOGS_H_ */ diff --git a/drivers/net/nfp/nfp_net_pmd.h b/drivers/net/nfp/nfp_net_pmd.h index 1ae0ea62..c1b044ee 100644 --- a/drivers/net/nfp/nfp_net_pmd.h +++ b/drivers/net/nfp/nfp_net_pmd.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014, 2015 Netronome Systems, Inc. + * Copyright (c) 2014-2018 Netronome Systems, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -63,6 +63,7 @@ struct nfp_net_adapter; #define NFP_NET_CRTL_BAR 0 #define NFP_NET_TX_BAR 2 #define NFP_NET_RX_BAR 2 +#define NFP_QCP_QUEUE_AREA_SZ 0x80000 /* Macros for accessing the Queue Controller Peripheral 'CSRs' */ #define NFP_QCP_QUEUE_OFF(_x) ((_x) * 0x800) @@ -184,18 +185,28 @@ static inline void nn_writeq(uint64_t val, volatile void *addr) struct nfp_net_tx_desc { union { struct { - uint8_t dma_addr_hi; /* High bits of host buf address */ + uint8_t dma_addr_hi; /* High bits of host buf address */ __le16 dma_len; /* Length to DMA for this desc */ - uint8_t offset_eop; /* Offset in buf where pkt starts + + uint8_t offset_eop; /* Offset in buf where pkt starts + * highest bit is eop flag. */ __le32 dma_addr_lo; /* Low 32bit of host buf addr */ - __le16 lso; /* MSS to be used for LSO */ - uint8_t l4_offset; /* LSO, where the L4 data starts */ - uint8_t flags; /* TX Flags, see @PCIE_DESC_TX_* */ - - __le16 vlan; /* VLAN tag to add if indicated */ + __le16 mss; /* MSS to be used for LSO */ + uint8_t lso_hdrlen; /* LSO, where the data starts */ + uint8_t flags; /* TX Flags, see @PCIE_DESC_TX_* */ + + union { + struct { + /* + * L3 and L4 header offsets required + * for TSOv2 + */ + uint8_t l3_offset; + uint8_t l4_offset; + }; + __le16 vlan; /* VLAN tag to add if indicated */ + }; __le16 data_len; /* Length of frame + meta data */ } __attribute__((__packed__)); __le32 vals[4]; @@ -247,15 +258,13 @@ struct nfp_net_txq { /* * At this point 48 bytes have been used for all the fields in the * TX critical path. We have room for 8 bytes and still all placed - * in a cache line. We are not using the threshold values below nor - * the txq_flags but if we need to, we can add the most used in the - * remaining bytes. + * in a cache line. We are not using the threshold values below but + * if we need to, we can add the most used in the remaining bytes. */ uint32_t tx_rs_thresh; /* not used by now. Future? */ uint32_t tx_pthresh; /* not used by now. Future? */ uint32_t tx_hthresh; /* not used by now. Future? */ uint32_t tx_wthresh; /* not used by now. Future? */ - uint32_t txq_flags; /* not used by now. Future? */ uint16_t port_id; int qidx; int tx_qcidx; @@ -430,20 +439,21 @@ struct nfp_net_hw { /* Records starting point for counters */ struct rte_eth_stats eth_stats_base; -#ifdef NFP_NET_LIBNFP struct nfp_cpp *cpp; struct nfp_cpp_area *ctrl_area; - struct nfp_cpp_area *tx_area; - struct nfp_cpp_area *rx_area; + struct nfp_cpp_area *hwqueues_area; struct nfp_cpp_area *msix_area; -#endif + uint8_t *hw_queues; uint8_t is_pf; uint8_t pf_port_idx; uint8_t pf_multiport_enabled; + uint8_t total_ports; + union eth_table_entry *eth_table; - nspu_desc_t *nspu_desc; - nfpu_desc_t *nfpu_desc; + + struct nfp_hwinfo *hwinfo; + struct nfp_rtsym_table *sym_tbl; }; struct nfp_net_adapter { diff --git a/drivers/net/nfp/nfp_nfpu.c b/drivers/net/nfp/nfp_nfpu.c deleted file mode 100644 index f11afef3..00000000 --- a/drivers/net/nfp/nfp_nfpu.c +++ /dev/null @@ -1,108 +0,0 @@ -#include <stdlib.h> -#include <stdio.h> -#include <string.h> -#include <unistd.h> -#include <errno.h> -#include <sys/file.h> -#include <sys/stat.h> -#include <fcntl.h> -#include <sys/types.h> - -#include <rte_bus_pci.h> -#include <rte_malloc.h> - -#include "nfp_nfpu.h" - -/* PF BAR and expansion BAR for the NSP interface */ -#define NFP_CFG_PCIE_BAR 0 -#define NFP_CFG_EXP_BAR 7 - -#define NFP_CFG_EXP_BAR_CFG_BASE 0x30000 - -/* There could be other NFP userspace tools using the NSP interface. - * Make sure there is no other process using it and locking the access for - * avoiding problems. - */ -static int -nspv_aquire_process_lock(nfpu_desc_t *desc) -{ - int rc; - struct flock lock; - char lockname[30]; - - memset(&lock, 0, sizeof(lock)); - - snprintf(lockname, sizeof(lockname), "/var/lock/nfp%d", desc->nfp); - - /* Using S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP | S_IROTH | S_IWOTH */ - desc->lock = open(lockname, O_RDWR | O_CREAT, 0666); - - if (desc->lock < 0) - return desc->lock; - - lock.l_type = F_WRLCK; - lock.l_whence = SEEK_SET; - rc = -1; - while (rc != 0) { - rc = fcntl(desc->lock, F_SETLK, &lock); - if (rc < 0) { - if ((errno != EAGAIN) && (errno != EACCES)) { - close(desc->lock); - return rc; - } - } - } - - return 0; -} - -int -nfpu_open(struct rte_pci_device *pci_dev, nfpu_desc_t *desc, int nfp) -{ - void *cfg_base, *mem_base; - size_t barsz; - int ret = 0; - int i = 0; - - desc->nfp = nfp; - - ret = nspv_aquire_process_lock(desc); - if (ret) - return -1; - - barsz = pci_dev->mem_resource[0].len; - - /* barsz in log2 */ - while (barsz >>= 1) - i++; - - barsz = i; - - /* Sanity check: we can assume any bar size less than 1MB an error */ - if (barsz < 20) - return -1; - - /* Getting address for NFP expansion BAR registers */ - cfg_base = pci_dev->mem_resource[0].addr; - cfg_base = (uint8_t *)cfg_base + NFP_CFG_EXP_BAR_CFG_BASE; - - /* Getting address for NFP NSP interface registers */ - mem_base = pci_dev->mem_resource[0].addr; - mem_base = (uint8_t *)mem_base + (NFP_CFG_EXP_BAR << (barsz - 3)); - - - desc->nspu = rte_malloc("nfp nspu", sizeof(nspu_desc_t), 0); - nfp_nspu_init(desc->nspu, desc->nfp, NFP_CFG_PCIE_BAR, barsz, - NFP_CFG_EXP_BAR, cfg_base, mem_base); - - return ret; -} - -int -nfpu_close(nfpu_desc_t *desc) -{ - rte_free(desc->nspu); - close(desc->lock); - unlink("/var/lock/nfp0"); - return 0; -} diff --git a/drivers/net/nfp/nfp_nfpu.h b/drivers/net/nfp/nfp_nfpu.h deleted file mode 100644 index e56fa099..00000000 --- a/drivers/net/nfp/nfp_nfpu.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright (c) 2017 Netronome Systems, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * vim:shiftwidth=8:noexpandtab - * - * @file dpdk/pmd/nfp_nfpu.h - * - * Netronome NFP_NET PDM driver - */ - -/* - * NFP User interface creates a window for talking with NFP NSP processor - */ - - -#include <rte_bus_pci.h> -#include "nfp_nspu.h" - -typedef struct { - int nfp; - int lock; - nspu_desc_t *nspu; -} nfpu_desc_t; - -int nfpu_open(struct rte_pci_device *pci_dev, nfpu_desc_t *desc, int nfp); -int nfpu_close(nfpu_desc_t *desc); diff --git a/drivers/net/nfp/nfp_nspu.c b/drivers/net/nfp/nfp_nspu.c deleted file mode 100644 index f9089832..00000000 --- a/drivers/net/nfp/nfp_nspu.c +++ /dev/null @@ -1,642 +0,0 @@ -#include <stdlib.h> -#include <stdio.h> -#include <string.h> -#include <unistd.h> -#include <sys/types.h> -#include <sys/file.h> -#include <sys/stat.h> -#include <fcntl.h> - -#include <rte_log.h> -#include <rte_byteorder.h> - -#include "nfp_nfpu.h" - -#define CFG_EXP_BAR_ADDR_SZ 1 -#define CFG_EXP_BAR_MAP_TYPE 1 - -#define EXP_BAR_TARGET_SHIFT 23 -#define EXP_BAR_LENGTH_SHIFT 27 /* 0=32, 1=64 bit increment */ -#define EXP_BAR_MAP_TYPE_SHIFT 29 /* Bulk BAR map */ - -/* NFP target for NSP access */ -#define NFP_NSP_TARGET 7 - -/* Expansion BARs for mapping PF vnic BARs */ -#define NFP_NET_PF_CFG_EXP_BAR 6 -#define NFP_NET_PF_HW_QUEUES_EXP_BAR 5 - -/* - * This is an NFP internal address used for configuring properly an NFP - * expansion BAR. - */ -#define MEM_CMD_BASE_ADDR 0x8100000000 - -/* NSP interface registers */ -#define NSP_BASE (MEM_CMD_BASE_ADDR + 0x22100) -#define NSP_STATUS 0x00 -#define NSP_COMMAND 0x08 -#define NSP_BUFFER 0x10 -#define NSP_DEFAULT_BUF 0x18 -#define NSP_DEFAULT_BUF_CFG 0x20 - -#define NSP_MAGIC 0xab10 -#define NSP_STATUS_MAGIC(x) (((x) >> 48) & 0xffff) -#define NSP_STATUS_MAJOR(x) (int)(((x) >> 44) & 0xf) -#define NSP_STATUS_MINOR(x) (int)(((x) >> 32) & 0xfff) - -/* NSP commands */ -#define NSP_CMD_RESET 1 -#define NSP_CMD_FW_LOAD 6 -#define NSP_CMD_READ_ETH_TABLE 7 -#define NSP_CMD_WRITE_ETH_TABLE 8 -#define NSP_CMD_GET_SYMBOL 14 - -#define NSP_BUFFER_CFG_SIZE_MASK (0xff) - -#define NSP_REG_ADDR(d, off, reg) ((uint8_t *)(d)->mem_base + (off) + (reg)) -#define NSP_REG_VAL(p) (*(uint64_t *)(p)) - -/* - * An NFP expansion BAR is configured for allowing access to a specific NFP - * target: - * - * IN: - * desc: struct with basic NSP addresses to work with - * expbar: NFP PF expansion BAR index to configure - * tgt: NFP target to configure access - * addr: NFP target address - * - * OUT: - * pcie_offset: NFP PCI BAR offset to work with - */ -static void -nfp_nspu_mem_bar_cfg(nspu_desc_t *desc, int expbar, int tgt, - uint64_t addr, uint64_t *pcie_offset) -{ - uint64_t x, y, barsz; - uint32_t *expbar_ptr; - - barsz = desc->barsz; - - /* - * NFP CPP address to configure. This comes from NFP 6000 - * datasheet document based on Bulk mapping. - */ - x = (addr >> (barsz - 3)) << (21 - (40 - (barsz - 3))); - x |= CFG_EXP_BAR_MAP_TYPE << EXP_BAR_MAP_TYPE_SHIFT; - x |= CFG_EXP_BAR_ADDR_SZ << EXP_BAR_LENGTH_SHIFT; - x |= tgt << EXP_BAR_TARGET_SHIFT; - - /* Getting expansion bar configuration register address */ - expbar_ptr = (uint32_t *)desc->cfg_base; - /* Each physical PCI BAR has 8 NFP expansion BARs */ - expbar_ptr += (desc->pcie_bar * 8) + expbar; - - /* Writing to the expansion BAR register */ - *expbar_ptr = (uint32_t)x; - - /* Getting the pcie offset to work with from userspace */ - y = addr & ((uint64_t)(1 << (barsz - 3)) - 1); - *pcie_offset = y; -} - -/* - * Configuring an expansion bar for accessing NSP userspace interface. This - * function configures always the same expansion bar, which implies access to - * previously configured NFP target is lost. - */ -static void -nspu_xlate(nspu_desc_t *desc, uint64_t addr, uint64_t *pcie_offset) -{ - nfp_nspu_mem_bar_cfg(desc, desc->exp_bar, NFP_NSP_TARGET, addr, - pcie_offset); -} - -int -nfp_nsp_get_abi_version(nspu_desc_t *desc, int *major, int *minor) -{ - uint64_t pcie_offset; - uint64_t nsp_reg; - - nspu_xlate(desc, NSP_BASE, &pcie_offset); - nsp_reg = NSP_REG_VAL(NSP_REG_ADDR(desc, pcie_offset, NSP_STATUS)); - - if (NSP_STATUS_MAGIC(nsp_reg) != NSP_MAGIC) - return -1; - - *major = NSP_STATUS_MAJOR(nsp_reg); - *minor = NSP_STATUS_MINOR(nsp_reg); - - return 0; -} - -int -nfp_nspu_init(nspu_desc_t *desc, int nfp, int pcie_bar, size_t pcie_barsz, - int exp_bar, void *exp_bar_cfg_base, void *exp_bar_mmap) -{ - uint64_t offset, buffaddr; - uint64_t nsp_reg; - - desc->nfp = nfp; - desc->pcie_bar = pcie_bar; - desc->exp_bar = exp_bar; - desc->barsz = pcie_barsz; - desc->windowsz = 1 << (desc->barsz - 3); - desc->cfg_base = exp_bar_cfg_base; - desc->mem_base = exp_bar_mmap; - - nspu_xlate(desc, NSP_BASE, &offset); - - /* - * Other NSPU clients can use other buffers. Let's tell NSPU we use the - * default buffer. - */ - buffaddr = NSP_REG_VAL(NSP_REG_ADDR(desc, offset, NSP_DEFAULT_BUF)); - NSP_REG_VAL(NSP_REG_ADDR(desc, offset, NSP_BUFFER)) = buffaddr; - - /* NFP internal addresses are 40 bits. Clean all other bits here */ - buffaddr = buffaddr & (((uint64_t)1 << 40) - 1); - desc->bufaddr = buffaddr; - - /* Lets get information about the buffer */ - nsp_reg = NSP_REG_VAL(NSP_REG_ADDR(desc, offset, NSP_DEFAULT_BUF_CFG)); - - /* Buffer size comes in MBs. Coversion to bytes */ - desc->buf_size = ((size_t)nsp_reg & NSP_BUFFER_CFG_SIZE_MASK) << 20; - - return 0; -} - -#define NSPU_NFP_BUF(addr, base, off) \ - (*(uint64_t *)((uint8_t *)(addr)->mem_base + ((base) | (off)))) - -#define NSPU_HOST_BUF(base, off) (*(uint64_t *)((uint8_t *)(base) + (off))) - -static int -nspu_buff_write(nspu_desc_t *desc, void *buffer, size_t size) -{ - uint64_t pcie_offset, pcie_window_base, pcie_window_offset; - uint64_t windowsz = desc->windowsz; - uint64_t buffaddr, j, i = 0; - int ret = 0; - - if (size > desc->buf_size) - return -1; - - buffaddr = desc->bufaddr; - windowsz = desc->windowsz; - - while (i < size) { - /* Expansion bar reconfiguration per window size */ - nspu_xlate(desc, buffaddr + i, &pcie_offset); - pcie_window_base = pcie_offset & (~(windowsz - 1)); - pcie_window_offset = pcie_offset & (windowsz - 1); - for (j = pcie_window_offset; ((j < windowsz) && (i < size)); - j += 8) { - NSPU_NFP_BUF(desc, pcie_window_base, j) = - NSPU_HOST_BUF(buffer, i); - i += 8; - } - } - - return ret; -} - -static int -nspu_buff_read(nspu_desc_t *desc, void *buffer, size_t size) -{ - uint64_t pcie_offset, pcie_window_base, pcie_window_offset; - uint64_t windowsz, i = 0, j; - uint64_t buffaddr; - int ret = 0; - - if (size > desc->buf_size) - return -1; - - buffaddr = desc->bufaddr; - windowsz = desc->windowsz; - - while (i < size) { - /* Expansion bar reconfiguration per window size */ - nspu_xlate(desc, buffaddr + i, &pcie_offset); - pcie_window_base = pcie_offset & (~(windowsz - 1)); - pcie_window_offset = pcie_offset & (windowsz - 1); - for (j = pcie_window_offset; ((j < windowsz) && (i < size)); - j += 8) { - NSPU_HOST_BUF(buffer, i) = - NSPU_NFP_BUF(desc, pcie_window_base, j); - i += 8; - } - } - - return ret; -} - -static int -nspu_command(nspu_desc_t *desc, uint16_t cmd, int read, int write, - void *buffer, size_t rsize, size_t wsize) -{ - uint64_t status, cmd_reg; - uint64_t offset; - int retry = 0; - int retries = 120; - int ret = 0; - - /* Same expansion BAR is used for different things */ - nspu_xlate(desc, NSP_BASE, &offset); - - status = NSP_REG_VAL(NSP_REG_ADDR(desc, offset, NSP_STATUS)); - - while ((status & 0x1) && (retry < retries)) { - status = NSP_REG_VAL(NSP_REG_ADDR(desc, offset, NSP_STATUS)); - retry++; - sleep(1); - } - - if (retry == retries) - return -1; - - if (write) { - ret = nspu_buff_write(desc, buffer, wsize); - if (ret) - return ret; - - /* Expansion BAR changes when writing the buffer */ - nspu_xlate(desc, NSP_BASE, &offset); - } - - NSP_REG_VAL(NSP_REG_ADDR(desc, offset, NSP_COMMAND)) = - (uint64_t)wsize << 32 | (uint64_t)cmd << 16 | 1; - - retry = 0; - - cmd_reg = NSP_REG_VAL(NSP_REG_ADDR(desc, offset, NSP_COMMAND)); - while ((cmd_reg & 0x1) && (retry < retries)) { - cmd_reg = NSP_REG_VAL(NSP_REG_ADDR(desc, offset, NSP_COMMAND)); - retry++; - sleep(1); - } - if (retry == retries) - return -1; - - retry = 0; - status = NSP_REG_VAL(NSP_REG_ADDR(desc, offset, NSP_STATUS)); - while ((status & 0x1) && (retry < retries)) { - status = NSP_REG_VAL(NSP_REG_ADDR(desc, offset, NSP_STATUS)); - retry++; - sleep(1); - } - - if (retry == retries) - return -1; - - ret = status & (0xff << 8); - if (ret) - return ret; - - if (read) { - ret = nspu_buff_read(desc, buffer, rsize); - if (ret) - return ret; - } - - return ret; -} - -static int -nfp_fw_reset(nspu_desc_t *nspu_desc) -{ - int res; - - res = nspu_command(nspu_desc, NSP_CMD_RESET, 0, 0, 0, 0, 0); - - if (res < 0) - RTE_LOG(INFO, PMD, "fw reset failed: error %d", res); - - return res; -} - -#define DEFAULT_FW_PATH "/lib/firmware/netronome" -#define DEFAULT_FW_FILENAME "nic_dpdk_default.nffw" - -static int -nfp_fw_upload(nspu_desc_t *nspu_desc) -{ - int fw_f; - char *fw_buf; - char filename[100]; - struct stat file_stat; - off_t fsize, bytes; - ssize_t size; - int ret; - - size = nspu_desc->buf_size; - - sprintf(filename, "%s/%s", DEFAULT_FW_PATH, DEFAULT_FW_FILENAME); - fw_f = open(filename, O_RDONLY); - if (fw_f < 0) { - RTE_LOG(INFO, PMD, "Firmware file %s/%s not found.", - DEFAULT_FW_PATH, DEFAULT_FW_FILENAME); - return -ENOENT; - } - - if (fstat(fw_f, &file_stat) < 0) { - RTE_LOG(INFO, PMD, "Firmware file %s/%s size is unknown", - DEFAULT_FW_PATH, DEFAULT_FW_FILENAME); - close(fw_f); - return -ENOENT; - } - - fsize = file_stat.st_size; - RTE_LOG(DEBUG, PMD, "Firmware file with size: %" PRIu64 "\n", - (uint64_t)fsize); - - if (fsize > (off_t)size) { - RTE_LOG(INFO, PMD, "fw file too big: %" PRIu64 - " bytes (%" PRIu64 " max)", - (uint64_t)fsize, (uint64_t)size); - close(fw_f); - return -EINVAL; - } - - fw_buf = malloc((size_t)size); - if (!fw_buf) { - RTE_LOG(INFO, PMD, "malloc failed for fw buffer"); - close(fw_f); - return -ENOMEM; - } - memset(fw_buf, 0, size); - - bytes = read(fw_f, fw_buf, fsize); - if (bytes != fsize) { - RTE_LOG(INFO, PMD, "Reading fw to buffer failed.\n" - "Just %" PRIu64 " of %" PRIu64 " bytes read.", - (uint64_t)bytes, (uint64_t)fsize); - free(fw_buf); - close(fw_f); - return -EIO; - } - - ret = nspu_command(nspu_desc, NSP_CMD_FW_LOAD, 0, 1, fw_buf, 0, bytes); - - free(fw_buf); - close(fw_f); - - return ret; -} - -/* Firmware symbol descriptor size */ -#define NFP_SYM_DESC_LEN 40 - -#define SYMBOL_DATA(b, off) (*(int64_t *)((b) + (off))) -#define SYMBOL_UDATA(b, off) (*(uint64_t *)((b) + (off))) - -/* Firmware symbols contain information about how to access what they - * represent. It can be as simple as an numeric variable declared at a - * specific NFP memory, but it can also be more complex structures and - * related to specific hardware functionalities or components. Target, - * domain and address allow to create the BAR window for accessing such - * hw object and size defines the length to map. - * - * A vNIC is a network interface implemented inside the NFP and using a - * subset of device PCI BARs. Specific firmware symbols allow to map those - * vNIC bars by host drivers like the NFP PMD. - * - * Accessing what the symbol represents implies to map the access through - * a PCI BAR window. NFP expansion BARs are used in this regard through - * the NSPU interface. - */ -static int -nfp_nspu_set_bar_from_symbl(nspu_desc_t *desc, const char *symbl, - uint32_t expbar, uint64_t *pcie_offset, - ssize_t *size) -{ - int64_t type; - int64_t target; - int64_t domain; - uint64_t addr; - char *sym_buf; - int ret = 0; - - sym_buf = malloc(desc->buf_size); - if (!sym_buf) - return -ENOMEM; - - strncpy(sym_buf, symbl, strlen(symbl)); - ret = nspu_command(desc, NSP_CMD_GET_SYMBOL, 1, 1, sym_buf, - NFP_SYM_DESC_LEN, strlen(symbl)); - if (ret) { - RTE_LOG(DEBUG, PMD, "symbol resolution (%s) failed\n", symbl); - goto clean; - } - - /* Reading symbol information */ - type = SYMBOL_DATA(sym_buf, 0); - target = SYMBOL_DATA(sym_buf, 8); - domain = SYMBOL_DATA(sym_buf, 16); - addr = SYMBOL_UDATA(sym_buf, 24); - *size = (ssize_t)SYMBOL_UDATA(sym_buf, 32); - - if (type != 1) { - RTE_LOG(INFO, PMD, "wrong symbol type\n"); - ret = -EINVAL; - goto clean; - } - if (!(target == 7 || target == -7)) { - RTE_LOG(INFO, PMD, "wrong symbol target\n"); - ret = -EINVAL; - goto clean; - } - if (domain == 8 || domain == 9) { - RTE_LOG(INFO, PMD, "wrong symbol domain\n"); - ret = -EINVAL; - goto clean; - } - - /* Adjusting address based on symbol location */ - if ((domain >= 24) && (domain < 28) && (target == 7)) { - addr = 1ULL << 37 | addr | ((uint64_t)domain & 0x3) << 35; - } else { - addr = 1ULL << 39 | addr | ((uint64_t)domain & 0x3f) << 32; - if (target == -7) - target = 7; - } - - /* Configuring NFP expansion bar for mapping specific PCI BAR window */ - nfp_nspu_mem_bar_cfg(desc, expbar, target, addr, pcie_offset); - - /* This is the PCI BAR offset to use by the host */ - *pcie_offset |= ((expbar & 0x7) << (desc->barsz - 3)); - -clean: - free(sym_buf); - return ret; -} - -int -nfp_nsp_fw_setup(nspu_desc_t *desc, const char *sym, uint64_t *pcie_offset) -{ - ssize_t bar0_sym_size; - - /* If the symbol resolution works, it implies a firmware app - * is already there. - */ - if (!nfp_nspu_set_bar_from_symbl(desc, sym, NFP_NET_PF_CFG_EXP_BAR, - pcie_offset, &bar0_sym_size)) - return 0; - - /* No firmware app detected or not the right one */ - RTE_LOG(INFO, PMD, "No firmware detected. Resetting NFP...\n"); - if (nfp_fw_reset(desc) < 0) { - RTE_LOG(ERR, PMD, "nfp fw reset failed\n"); - return -ENODEV; - } - - RTE_LOG(INFO, PMD, "Reset done.\n"); - RTE_LOG(INFO, PMD, "Uploading firmware...\n"); - - if (nfp_fw_upload(desc) < 0) { - RTE_LOG(ERR, PMD, "nfp fw upload failed\n"); - return -ENODEV; - } - - RTE_LOG(INFO, PMD, "Done.\n"); - - /* Now the symbol should be there */ - if (nfp_nspu_set_bar_from_symbl(desc, sym, NFP_NET_PF_CFG_EXP_BAR, - pcie_offset, &bar0_sym_size)) { - RTE_LOG(ERR, PMD, "nfp PF BAR symbol resolution failed\n"); - return -ENODEV; - } - - return 0; -} - -int -nfp_nsp_map_ctrl_bar(nspu_desc_t *desc, uint64_t *pcie_offset) -{ - ssize_t bar0_sym_size; - - if (nfp_nspu_set_bar_from_symbl(desc, "_pf0_net_bar0", - NFP_NET_PF_CFG_EXP_BAR, - pcie_offset, &bar0_sym_size)) - return -ENODEV; - - return 0; -} - -/* - * This is a hardcoded fixed NFP internal CPP bus address for the hw queues unit - * inside the PCIE island. - */ -#define NFP_CPP_PCIE_QUEUES ((uint64_t)(1ULL << 39) | 0x80000 | \ - ((uint64_t)0x4 & 0x3f) << 32) - -/* Configure a specific NFP expansion bar for accessing the vNIC rx/tx BARs */ -void -nfp_nsp_map_queues_bar(nspu_desc_t *desc, uint64_t *pcie_offset) -{ - nfp_nspu_mem_bar_cfg(desc, NFP_NET_PF_HW_QUEUES_EXP_BAR, 0, - NFP_CPP_PCIE_QUEUES, pcie_offset); - - /* This is the pcie offset to use by the host */ - *pcie_offset |= ((NFP_NET_PF_HW_QUEUES_EXP_BAR & 0x7) << (27 - 3)); -} - -int -nfp_nsp_eth_config(nspu_desc_t *desc, int port, int up) -{ - union eth_table_entry *entries, *entry; - int modified; - int ret, idx; - int i; - - idx = port; - - RTE_LOG(INFO, PMD, "Hw ethernet port %d configure...\n", port); - rte_spinlock_lock(&desc->nsp_lock); - entries = malloc(NSP_ETH_TABLE_SIZE); - if (!entries) { - rte_spinlock_unlock(&desc->nsp_lock); - return -ENOMEM; - } - - ret = nspu_command(desc, NSP_CMD_READ_ETH_TABLE, 1, 0, entries, - NSP_ETH_TABLE_SIZE, 0); - if (ret) { - rte_spinlock_unlock(&desc->nsp_lock); - free(entries); - return ret; - } - - entry = entries; - - for (i = 0; i < NSP_ETH_MAX_COUNT; i++) { - /* ports in use do not appear sequentially in the table */ - if (!(entry->port & NSP_ETH_PORT_LANES_MASK)) { - /* entry not in use */ - entry++; - continue; - } - if (idx == 0) - break; - idx--; - entry++; - } - - if (i == NSP_ETH_MAX_COUNT) { - rte_spinlock_unlock(&desc->nsp_lock); - free(entries); - return -EINVAL; - } - - if (up && !(entry->state & NSP_ETH_STATE_CONFIGURED)) { - entry->control |= NSP_ETH_STATE_CONFIGURED; - modified = 1; - } - - if (!up && (entry->state & NSP_ETH_STATE_CONFIGURED)) { - entry->control &= ~NSP_ETH_STATE_CONFIGURED; - modified = 1; - } - - if (modified) { - ret = nspu_command(desc, NSP_CMD_WRITE_ETH_TABLE, 0, 1, entries, - 0, NSP_ETH_TABLE_SIZE); - if (!ret) - RTE_LOG(INFO, PMD, - "Hw ethernet port %d configure done\n", port); - else - RTE_LOG(INFO, PMD, - "Hw ethernet port %d configure failed\n", port); - } - rte_spinlock_unlock(&desc->nsp_lock); - free(entries); - return ret; -} - -int -nfp_nsp_eth_read_table(nspu_desc_t *desc, union eth_table_entry **table) -{ - int ret; - - if (!table) - return -EINVAL; - - RTE_LOG(INFO, PMD, "Reading hw ethernet table...\n"); - - /* port 0 allocates the eth table and read it using NSPU */ - *table = malloc(NSP_ETH_TABLE_SIZE); - if (!*table) - return -ENOMEM; - - ret = nspu_command(desc, NSP_CMD_READ_ETH_TABLE, 1, 0, *table, - NSP_ETH_TABLE_SIZE, 0); - if (ret) - return ret; - - RTE_LOG(INFO, PMD, "Done\n"); - - return 0; -} diff --git a/drivers/net/nfp/nfp_nspu.h b/drivers/net/nfp/nfp_nspu.h deleted file mode 100644 index 8c33835e..00000000 --- a/drivers/net/nfp/nfp_nspu.h +++ /dev/null @@ -1,83 +0,0 @@ -/* - * Copyright (c) 2017 Netronome Systems, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * vim:shiftwidth=8:noexpandtab - * - * @file dpdk/pmd/nfp_nspu.h - * - * Netronome NFP_NET PDM driver - */ - -/* - * NSP is the NFP Service Processor. NSPU is NSP Userspace interface. - * - * NFP NSP helps with firmware/hardware configuration. NSP is another component - * in NFP programmable processor and accessing it from host requires to firstly - * configure a specific NFP PCI expansion BAR. - * - * Once access is ready, configuration can be done reading and writing - * from/to a specific PF PCI BAR window. This same interface will allow to - * create other PCI BAR windows for accessing other NFP components. - * - * This file includes low-level functions, using the NSPU interface, and high - * level functions, invoked by the PMD for using NSP services. This allows - * firmware upload, vNIC PCI BARs mapping and other low-level configurations - * like link setup. - * - * NSP access is done during initialization and it is not involved at all with - * the fast path. - */ - -#include <rte_spinlock.h> -#include "nfp_net_eth.h" - -typedef struct { - int nfp; /* NFP device */ - int pcie_bar; /* PF PCI BAR to work with */ - int exp_bar; /* Expansion BAR number used by NSPU */ - int barsz; /* PCIE BAR log2 size */ - uint64_t bufaddr; /* commands buffer address */ - size_t buf_size; /* commands buffer size */ - uint64_t windowsz; /* NSPU BAR window size */ - void *cfg_base; /* Expansion BARs address */ - void *mem_base; /* NSP interface */ - rte_spinlock_t nsp_lock; -} nspu_desc_t; - -int nfp_nspu_init(nspu_desc_t *desc, int nfp, int pcie_bar, size_t pcie_barsz, - int exp_bar, void *exp_bar_cfg_base, void *exp_bar_mmap); -int nfp_nsp_get_abi_version(nspu_desc_t *desc, int *major, int *minor); -int nfp_nsp_fw_setup(nspu_desc_t *desc, const char *sym, uint64_t *pcie_offset); -int nfp_nsp_map_ctrl_bar(nspu_desc_t *desc, uint64_t *pcie_offset); -void nfp_nsp_map_queues_bar(nspu_desc_t *desc, uint64_t *pcie_offset); -int nfp_nsp_eth_config(nspu_desc_t *desc, int port, int up); -int nfp_nsp_eth_read_table(nspu_desc_t *desc, union eth_table_entry **table); diff --git a/drivers/net/nfp/nfpcore/nfp-common/nfp_cppat.h b/drivers/net/nfp/nfpcore/nfp-common/nfp_cppat.h new file mode 100644 index 00000000..6e380cca --- /dev/null +++ b/drivers/net/nfp/nfpcore/nfp-common/nfp_cppat.h @@ -0,0 +1,722 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2018 Netronome Systems, Inc. + * All rights reserved. + */ + +#ifndef __NFP_CPPAT_H__ +#define __NFP_CPPAT_H__ + +#include "nfp_platform.h" +#include "nfp_resid.h" + +/* This file contains helpers for creating CPP commands + * + * All magic NFP-6xxx IMB 'mode' numbers here are from: + * Databook (1 August 2013) + * - System Overview and Connectivity + * -- Internal Connectivity + * --- Distributed Switch Fabric - Command Push/Pull (DSF-CPP) Bus + * ---- CPP addressing + * ----- Table 3.6. CPP Address Translation Mode Commands + */ + +#define _NIC_NFP6000_MU_LOCALITY_DIRECT 2 + +static inline int +_nfp6000_decode_basic(uint64_t addr, int *dest_island, int cpp_tgt, int mode, + int addr40, int isld1, int isld0); + +static uint64_t +_nic_mask64(int msb, int lsb, int at0) +{ + uint64_t v; + int w = msb - lsb + 1; + + if (w == 64) + return ~(uint64_t)0; + + if ((lsb + w) > 64) + return 0; + + v = (UINT64_C(1) << w) - 1; + + if (at0) + return v; + + return v << lsb; +} + +/* For VQDR, we may not modify the Channel bits, which might overlap + * with the Index bit. When it does, we need to ensure that isld0 == isld1. + */ +static inline int +_nfp6000_encode_basic(uint64_t *addr, int dest_island, int cpp_tgt, int mode, + int addr40, int isld1, int isld0) +{ + uint64_t _u64; + int iid_lsb, idx_lsb; + int i, v = 0; + int isld[2]; + + isld[0] = isld0; + isld[1] = isld1; + + switch (cpp_tgt) { + case NFP6000_CPPTGT_MU: + /* This function doesn't handle MU */ + return NFP_ERRNO(EINVAL); + case NFP6000_CPPTGT_CTXPB: + /* This function doesn't handle CTXPB */ + return NFP_ERRNO(EINVAL); + default: + break; + } + + switch (mode) { + case 0: + if (cpp_tgt == NFP6000_CPPTGT_VQDR && !addr40) { + /* + * In this specific mode we'd rather not modify the + * address but we can verify if the existing contents + * will point to a valid island. + */ + i = _nfp6000_decode_basic(*addr, &v, cpp_tgt, mode, + addr40, isld1, + isld0); + if (i != 0) + /* Full Island ID and channel bits overlap */ + return i; + + /* + * If dest_island is invalid, the current address won't + * go where expected. + */ + if (dest_island != -1 && dest_island != v) + return NFP_ERRNO(EINVAL); + + /* If dest_island was -1, we don't care */ + return 0; + } + + iid_lsb = (addr40) ? 34 : 26; + + /* <39:34> or <31:26> */ + _u64 = _nic_mask64((iid_lsb + 5), iid_lsb, 0); + *addr &= ~_u64; + *addr |= (((uint64_t)dest_island) << iid_lsb) & _u64; + return 0; + case 1: + if (cpp_tgt == NFP6000_CPPTGT_VQDR && !addr40) { + i = _nfp6000_decode_basic(*addr, &v, cpp_tgt, mode, + addr40, isld1, isld0); + if (i != 0) + /* Full Island ID and channel bits overlap */ + return i; + + /* + * If dest_island is invalid, the current address won't + * go where expected. + */ + if (dest_island != -1 && dest_island != v) + return NFP_ERRNO(EINVAL); + + /* If dest_island was -1, we don't care */ + return 0; + } + + idx_lsb = (addr40) ? 39 : 31; + if (dest_island == isld0) { + /* Only need to clear the Index bit */ + *addr &= ~_nic_mask64(idx_lsb, idx_lsb, 0); + return 0; + } + + if (dest_island == isld1) { + /* Only need to set the Index bit */ + *addr |= (UINT64_C(1) << idx_lsb); + return 0; + } + + return NFP_ERRNO(ENODEV); + case 2: + if (cpp_tgt == NFP6000_CPPTGT_VQDR && !addr40) { + /* iid<0> = addr<30> = channel<0> */ + /* channel<1> = addr<31> = Index */ + + /* + * Special case where we allow channel bits to be set + * before hand and with them select an island. + * So we need to confirm that it's at least plausible. + */ + i = _nfp6000_decode_basic(*addr, &v, cpp_tgt, mode, + addr40, isld1, isld0); + if (i != 0) + /* Full Island ID and channel bits overlap */ + return i; + + /* + * If dest_island is invalid, the current address won't + * go where expected. + */ + if (dest_island != -1 && dest_island != v) + return NFP_ERRNO(EINVAL); + + /* If dest_island was -1, we don't care */ + return 0; + } + + /* + * Make sure we compare against isldN values by clearing the + * LSB. This is what the silicon does. + **/ + isld[0] &= ~1; + isld[1] &= ~1; + + idx_lsb = (addr40) ? 39 : 31; + iid_lsb = idx_lsb - 1; + + /* + * Try each option, take first one that fits. Not sure if we + * would want to do some smarter searching and prefer 0 or non-0 + * island IDs. + */ + + for (i = 0; i < 2; i++) { + for (v = 0; v < 2; v++) { + if (dest_island != (isld[i] | v)) + continue; + *addr &= ~_nic_mask64(idx_lsb, iid_lsb, 0); + *addr |= (((uint64_t)i) << idx_lsb); + *addr |= (((uint64_t)v) << iid_lsb); + return 0; + } + } + + return NFP_ERRNO(ENODEV); + case 3: + if (cpp_tgt == NFP6000_CPPTGT_VQDR && !addr40) { + /* + * iid<0> = addr<29> = data + * iid<1> = addr<30> = channel<0> + * channel<1> = addr<31> = Index + */ + i = _nfp6000_decode_basic(*addr, &v, cpp_tgt, mode, + addr40, isld1, isld0); + if (i != 0) + /* Full Island ID and channel bits overlap */ + return i; + + if (dest_island != -1 && dest_island != v) + return NFP_ERRNO(EINVAL); + + /* If dest_island was -1, we don't care */ + return 0; + } + + isld[0] &= ~3; + isld[1] &= ~3; + + idx_lsb = (addr40) ? 39 : 31; + iid_lsb = idx_lsb - 2; + + for (i = 0; i < 2; i++) { + for (v = 0; v < 4; v++) { + if (dest_island != (isld[i] | v)) + continue; + *addr &= ~_nic_mask64(idx_lsb, iid_lsb, 0); + *addr |= (((uint64_t)i) << idx_lsb); + *addr |= (((uint64_t)v) << iid_lsb); + return 0; + } + } + return NFP_ERRNO(ENODEV); + default: + break; + } + + return NFP_ERRNO(EINVAL); +} + +static inline int +_nfp6000_decode_basic(uint64_t addr, int *dest_island, int cpp_tgt, int mode, + int addr40, int isld1, int isld0) +{ + int iid_lsb, idx_lsb; + + switch (cpp_tgt) { + case NFP6000_CPPTGT_MU: + /* This function doesn't handle MU */ + return NFP_ERRNO(EINVAL); + case NFP6000_CPPTGT_CTXPB: + /* This function doesn't handle CTXPB */ + return NFP_ERRNO(EINVAL); + default: + break; + } + + switch (mode) { + case 0: + /* + * For VQDR, in this mode for 32-bit addressing it would be + * islands 0, 16, 32 and 48 depending on channel and upper + * address bits. Since those are not all valid islands, most + * decode cases would result in bad island IDs, but we do them + * anyway since this is decoding an address that is already + * assumed to be used as-is to get to sram. + */ + iid_lsb = (addr40) ? 34 : 26; + *dest_island = (int)(addr >> iid_lsb) & 0x3F; + return 0; + case 1: + /* + * For VQDR 32-bit, this would decode as: + * Channel 0: island#0 + * Channel 1: island#0 + * Channel 2: island#1 + * Channel 3: island#1 + * + * That would be valid as long as both islands have VQDR. + * Let's allow this. + */ + + idx_lsb = (addr40) ? 39 : 31; + if (addr & _nic_mask64(idx_lsb, idx_lsb, 0)) + *dest_island = isld1; + else + *dest_island = isld0; + + return 0; + case 2: + /* + * For VQDR 32-bit: + * Channel 0: (island#0 | 0) + * Channel 1: (island#0 | 1) + * Channel 2: (island#1 | 0) + * Channel 3: (island#1 | 1) + * + * Make sure we compare against isldN values by clearing the + * LSB. This is what the silicon does. + */ + isld0 &= ~1; + isld1 &= ~1; + + idx_lsb = (addr40) ? 39 : 31; + iid_lsb = idx_lsb - 1; + + if (addr & _nic_mask64(idx_lsb, idx_lsb, 0)) + *dest_island = isld1 | (int)((addr >> iid_lsb) & 1); + else + *dest_island = isld0 | (int)((addr >> iid_lsb) & 1); + + return 0; + case 3: + /* + * In this mode the data address starts to affect the island ID + * so rather not allow it. In some really specific case one + * could use this to send the upper half of the VQDR channel to + * another MU, but this is getting very specific. However, as + * above for mode 0, this is the decoder and the caller should + * validate the resulting IID. This blindly does what the + * silicon would do. + */ + + isld0 &= ~3; + isld1 &= ~3; + + idx_lsb = (addr40) ? 39 : 31; + iid_lsb = idx_lsb - 2; + + if (addr & _nic_mask64(idx_lsb, idx_lsb, 0)) + *dest_island = isld1 | (int)((addr >> iid_lsb) & 3); + else + *dest_island = isld0 | (int)((addr >> iid_lsb) & 3); + + return 0; + default: + break; + } + + return NFP_ERRNO(EINVAL); +} + +static inline int +_nfp6000_cppat_mu_locality_lsb(int mode, int addr40) +{ + switch (mode) { + case 0: + case 1: + case 2: + case 3: + return (addr40) ? 38 : 30; + default: + break; + } + return NFP_ERRNO(EINVAL); +} + +static inline int +_nfp6000_encode_mu(uint64_t *addr, int dest_island, int mode, int addr40, + int isld1, int isld0) +{ + uint64_t _u64; + int iid_lsb, idx_lsb, locality_lsb; + int i, v; + int isld[2]; + int da; + + isld[0] = isld0; + isld[1] = isld1; + locality_lsb = _nfp6000_cppat_mu_locality_lsb(mode, addr40); + + if (((*addr >> locality_lsb) & 3) == _NIC_NFP6000_MU_LOCALITY_DIRECT) + da = 1; + else + da = 0; + + switch (mode) { + case 0: + iid_lsb = (addr40) ? 32 : 24; + _u64 = _nic_mask64((iid_lsb + 5), iid_lsb, 0); + *addr &= ~_u64; + *addr |= (((uint64_t)dest_island) << iid_lsb) & _u64; + return 0; + case 1: + if (da) { + iid_lsb = (addr40) ? 32 : 24; + _u64 = _nic_mask64((iid_lsb + 5), iid_lsb, 0); + *addr &= ~_u64; + *addr |= (((uint64_t)dest_island) << iid_lsb) & _u64; + return 0; + } + + idx_lsb = (addr40) ? 37 : 29; + if (dest_island == isld0) { + *addr &= ~_nic_mask64(idx_lsb, idx_lsb, 0); + return 0; + } + + if (dest_island == isld1) { + *addr |= (UINT64_C(1) << idx_lsb); + return 0; + } + + return NFP_ERRNO(ENODEV); + case 2: + if (da) { + iid_lsb = (addr40) ? 32 : 24; + _u64 = _nic_mask64((iid_lsb + 5), iid_lsb, 0); + *addr &= ~_u64; + *addr |= (((uint64_t)dest_island) << iid_lsb) & _u64; + return 0; + } + + /* + * Make sure we compare against isldN values by clearing the + * LSB. This is what the silicon does. + */ + isld[0] &= ~1; + isld[1] &= ~1; + + idx_lsb = (addr40) ? 37 : 29; + iid_lsb = idx_lsb - 1; + + /* + * Try each option, take first one that fits. Not sure if we + * would want to do some smarter searching and prefer 0 or + * non-0 island IDs. + */ + + for (i = 0; i < 2; i++) { + for (v = 0; v < 2; v++) { + if (dest_island != (isld[i] | v)) + continue; + *addr &= ~_nic_mask64(idx_lsb, iid_lsb, 0); + *addr |= (((uint64_t)i) << idx_lsb); + *addr |= (((uint64_t)v) << iid_lsb); + return 0; + } + } + return NFP_ERRNO(ENODEV); + case 3: + /* + * Only the EMU will use 40 bit addressing. Silently set the + * direct locality bit for everyone else. The SDK toolchain + * uses dest_island <= 0 to test for atypical address encodings + * to support access to local-island CTM with a 32-but address + * (high-locality is effectively ignored and just used for + * routing to island #0). + */ + if (dest_island > 0 && + (dest_island < 24 || dest_island > 26)) { + *addr |= ((uint64_t)_NIC_NFP6000_MU_LOCALITY_DIRECT) + << locality_lsb; + da = 1; + } + + if (da) { + iid_lsb = (addr40) ? 32 : 24; + _u64 = _nic_mask64((iid_lsb + 5), iid_lsb, 0); + *addr &= ~_u64; + *addr |= (((uint64_t)dest_island) << iid_lsb) & _u64; + return 0; + } + + isld[0] &= ~3; + isld[1] &= ~3; + + idx_lsb = (addr40) ? 37 : 29; + iid_lsb = idx_lsb - 2; + + for (i = 0; i < 2; i++) { + for (v = 0; v < 4; v++) { + if (dest_island != (isld[i] | v)) + continue; + *addr &= ~_nic_mask64(idx_lsb, iid_lsb, 0); + *addr |= (((uint64_t)i) << idx_lsb); + *addr |= (((uint64_t)v) << iid_lsb); + return 0; + } + } + + return NFP_ERRNO(ENODEV); + default: + break; + } + + return NFP_ERRNO(EINVAL); +} + +static inline int +_nfp6000_decode_mu(uint64_t addr, int *dest_island, int mode, int addr40, + int isld1, int isld0) +{ + int iid_lsb, idx_lsb, locality_lsb; + int da; + + locality_lsb = _nfp6000_cppat_mu_locality_lsb(mode, addr40); + + if (((addr >> locality_lsb) & 3) == _NIC_NFP6000_MU_LOCALITY_DIRECT) + da = 1; + else + da = 0; + + switch (mode) { + case 0: + iid_lsb = (addr40) ? 32 : 24; + *dest_island = (int)(addr >> iid_lsb) & 0x3F; + return 0; + case 1: + if (da) { + iid_lsb = (addr40) ? 32 : 24; + *dest_island = (int)(addr >> iid_lsb) & 0x3F; + return 0; + } + + idx_lsb = (addr40) ? 37 : 29; + + if (addr & _nic_mask64(idx_lsb, idx_lsb, 0)) + *dest_island = isld1; + else + *dest_island = isld0; + + return 0; + case 2: + if (da) { + iid_lsb = (addr40) ? 32 : 24; + *dest_island = (int)(addr >> iid_lsb) & 0x3F; + return 0; + } + /* + * Make sure we compare against isldN values by clearing the + * LSB. This is what the silicon does. + */ + isld0 &= ~1; + isld1 &= ~1; + + idx_lsb = (addr40) ? 37 : 29; + iid_lsb = idx_lsb - 1; + + if (addr & _nic_mask64(idx_lsb, idx_lsb, 0)) + *dest_island = isld1 | (int)((addr >> iid_lsb) & 1); + else + *dest_island = isld0 | (int)((addr >> iid_lsb) & 1); + + return 0; + case 3: + if (da) { + iid_lsb = (addr40) ? 32 : 24; + *dest_island = (int)(addr >> iid_lsb) & 0x3F; + return 0; + } + + isld0 &= ~3; + isld1 &= ~3; + + idx_lsb = (addr40) ? 37 : 29; + iid_lsb = idx_lsb - 2; + + if (addr & _nic_mask64(idx_lsb, idx_lsb, 0)) + *dest_island = isld1 | (int)((addr >> iid_lsb) & 3); + else + *dest_island = isld0 | (int)((addr >> iid_lsb) & 3); + + return 0; + default: + break; + } + + return NFP_ERRNO(EINVAL); +} + +static inline int +_nfp6000_cppat_addr_encode(uint64_t *addr, int dest_island, int cpp_tgt, + int mode, int addr40, int isld1, int isld0) +{ + switch (cpp_tgt) { + case NFP6000_CPPTGT_NBI: + case NFP6000_CPPTGT_VQDR: + case NFP6000_CPPTGT_ILA: + case NFP6000_CPPTGT_PCIE: + case NFP6000_CPPTGT_ARM: + case NFP6000_CPPTGT_CRYPTO: + case NFP6000_CPPTGT_CLS: + return _nfp6000_encode_basic(addr, dest_island, cpp_tgt, mode, + addr40, isld1, isld0); + + case NFP6000_CPPTGT_MU: + return _nfp6000_encode_mu(addr, dest_island, mode, addr40, + isld1, isld0); + + case NFP6000_CPPTGT_CTXPB: + if (mode != 1 || addr40 != 0) + return NFP_ERRNO(EINVAL); + + *addr &= ~_nic_mask64(29, 24, 0); + *addr |= (((uint64_t)dest_island) << 24) & + _nic_mask64(29, 24, 0); + return 0; + default: + break; + } + + return NFP_ERRNO(EINVAL); +} + +static inline int +_nfp6000_cppat_addr_decode(uint64_t addr, int *dest_island, int cpp_tgt, + int mode, int addr40, int isld1, int isld0) +{ + switch (cpp_tgt) { + case NFP6000_CPPTGT_NBI: + case NFP6000_CPPTGT_VQDR: + case NFP6000_CPPTGT_ILA: + case NFP6000_CPPTGT_PCIE: + case NFP6000_CPPTGT_ARM: + case NFP6000_CPPTGT_CRYPTO: + case NFP6000_CPPTGT_CLS: + return _nfp6000_decode_basic(addr, dest_island, cpp_tgt, mode, + addr40, isld1, isld0); + + case NFP6000_CPPTGT_MU: + return _nfp6000_decode_mu(addr, dest_island, mode, addr40, + isld1, isld0); + + case NFP6000_CPPTGT_CTXPB: + if (mode != 1 || addr40 != 0) + return -EINVAL; + *dest_island = (int)(addr >> 24) & 0x3F; + return 0; + default: + break; + } + + return -EINVAL; +} + +static inline int +_nfp6000_cppat_addr_iid_clear(uint64_t *addr, int cpp_tgt, int mode, int addr40) +{ + int iid_lsb, locality_lsb, da; + + switch (cpp_tgt) { + case NFP6000_CPPTGT_NBI: + case NFP6000_CPPTGT_VQDR: + case NFP6000_CPPTGT_ILA: + case NFP6000_CPPTGT_PCIE: + case NFP6000_CPPTGT_ARM: + case NFP6000_CPPTGT_CRYPTO: + case NFP6000_CPPTGT_CLS: + switch (mode) { + case 0: + iid_lsb = (addr40) ? 34 : 26; + *addr &= ~(UINT64_C(0x3F) << iid_lsb); + return 0; + case 1: + iid_lsb = (addr40) ? 39 : 31; + *addr &= ~_nic_mask64(iid_lsb, iid_lsb, 0); + return 0; + case 2: + iid_lsb = (addr40) ? 38 : 30; + *addr &= ~_nic_mask64(iid_lsb + 1, iid_lsb, 0); + return 0; + case 3: + iid_lsb = (addr40) ? 37 : 29; + *addr &= ~_nic_mask64(iid_lsb + 2, iid_lsb, 0); + return 0; + default: + break; + } + case NFP6000_CPPTGT_MU: + locality_lsb = _nfp6000_cppat_mu_locality_lsb(mode, addr40); + da = (((*addr >> locality_lsb) & 3) == + _NIC_NFP6000_MU_LOCALITY_DIRECT); + switch (mode) { + case 0: + iid_lsb = (addr40) ? 32 : 24; + *addr &= ~(UINT64_C(0x3F) << iid_lsb); + return 0; + case 1: + if (da) { + iid_lsb = (addr40) ? 32 : 24; + *addr &= ~(UINT64_C(0x3F) << iid_lsb); + return 0; + } + iid_lsb = (addr40) ? 37 : 29; + *addr &= ~_nic_mask64(iid_lsb, iid_lsb, 0); + return 0; + case 2: + if (da) { + iid_lsb = (addr40) ? 32 : 24; + *addr &= ~(UINT64_C(0x3F) << iid_lsb); + return 0; + } + + iid_lsb = (addr40) ? 36 : 28; + *addr &= ~_nic_mask64(iid_lsb + 1, iid_lsb, 0); + return 0; + case 3: + if (da) { + iid_lsb = (addr40) ? 32 : 24; + *addr &= ~(UINT64_C(0x3F) << iid_lsb); + return 0; + } + + iid_lsb = (addr40) ? 35 : 27; + *addr &= ~_nic_mask64(iid_lsb + 2, iid_lsb, 0); + return 0; + default: + break; + } + case NFP6000_CPPTGT_CTXPB: + if (mode != 1 || addr40 != 0) + return 0; + *addr &= ~(UINT64_C(0x3F) << 24); + return 0; + default: + break; + } + + return NFP_ERRNO(EINVAL); +} + +#endif /* __NFP_CPPAT_H__ */ diff --git a/drivers/net/nfp/nfpcore/nfp-common/nfp_platform.h b/drivers/net/nfp/nfpcore/nfp-common/nfp_platform.h new file mode 100644 index 00000000..d46574b1 --- /dev/null +++ b/drivers/net/nfp/nfpcore/nfp-common/nfp_platform.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2018 Netronome Systems, Inc. + * All rights reserved. + */ + +#ifndef __NFP_PLATFORM_H__ +#define __NFP_PLATFORM_H__ + +#include <fcntl.h> +#include <unistd.h> +#include <stdint.h> +#include <string.h> +#include <stdlib.h> +#include <ctype.h> +#include <inttypes.h> +#include <sys/stat.h> +#include <limits.h> +#include <errno.h> + +#ifndef BIT_ULL +#define BIT(x) (1 << (x)) +#define BIT_ULL(x) (1ULL << (x)) +#endif + +#ifndef ARRAY_SIZE +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) +#endif + +#define NFP_ERRNO(err) (errno = (err), -1) +#define NFP_ERRNO_RET(err, ret) (errno = (err), (ret)) +#define NFP_NOERR(errv) (errno) +#define NFP_ERRPTR(err) (errno = (err), NULL) +#define NFP_PTRERR(errv) (errno) + +#endif /* __NFP_PLATFORM_H__ */ diff --git a/drivers/net/nfp/nfpcore/nfp-common/nfp_resid.h b/drivers/net/nfp/nfpcore/nfp-common/nfp_resid.h new file mode 100644 index 00000000..0e03948e --- /dev/null +++ b/drivers/net/nfp/nfpcore/nfp-common/nfp_resid.h @@ -0,0 +1,592 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2018 Netronome Systems, Inc. + * All rights reserved. + */ + +#ifndef __NFP_RESID_H__ +#define __NFP_RESID_H__ + +#if (!defined(_NFP_RESID_NO_C_FUNC) && \ + (defined(__NFP_TOOL_NFCC) || defined(__NFP_TOOL_NFAS))) +#define _NFP_RESID_NO_C_FUNC +#endif + +#ifndef _NFP_RESID_NO_C_FUNC +#include "nfp_platform.h" +#endif + +/* + * NFP Chip Architectures + * + * These are semi-arbitrary values to indicate an NFP architecture. + * They serve as a software view of a group of chip families, not necessarily a + * direct mapping to actual hardware design. + */ +#define NFP_CHIP_ARCH_YD 1 +#define NFP_CHIP_ARCH_TH 2 + +/* + * NFP Chip Families. + * + * These are not enums, because they need to be microcode compatible. + * They are also not maskable. + * + * Note: The NFP-4xxx family is handled as NFP-6xxx in most software + * components. + * + */ +#define NFP_CHIP_FAMILY_NFP6000 0x6000 /* ARCH_TH */ + +/* NFP Microengine/Flow Processing Core Versions */ +#define NFP_CHIP_ME_VERSION_2_7 0x0207 +#define NFP_CHIP_ME_VERSION_2_8 0x0208 +#define NFP_CHIP_ME_VERSION_2_9 0x0209 + +/* NFP Chip Base Revisions. Minor stepping can just be added to these */ +#define NFP_CHIP_REVISION_A0 0x00 +#define NFP_CHIP_REVISION_B0 0x10 +#define NFP_CHIP_REVISION_C0 0x20 +#define NFP_CHIP_REVISION_PF 0xff /* Maximum possible revision */ + +/* CPP Targets for each chip architecture */ +#define NFP6000_CPPTGT_NBI 1 +#define NFP6000_CPPTGT_VQDR 2 +#define NFP6000_CPPTGT_ILA 6 +#define NFP6000_CPPTGT_MU 7 +#define NFP6000_CPPTGT_PCIE 9 +#define NFP6000_CPPTGT_ARM 10 +#define NFP6000_CPPTGT_CRYPTO 12 +#define NFP6000_CPPTGT_CTXPB 14 +#define NFP6000_CPPTGT_CLS 15 + +/* + * Wildcard indicating a CPP read or write action + * + * The action used will be either read or write depending on whether a read or + * write instruction/call is performed on the NFP_CPP_ID. It is recomended that + * the RW action is used even if all actions to be performed on a NFP_CPP_ID are + * known to be only reads or writes. Doing so will in many cases save NFP CPP + * internal software resources. + */ +#define NFP_CPP_ACTION_RW 32 + +#define NFP_CPP_TARGET_ID_MASK 0x1f + +/* + * NFP_CPP_ID - pack target, token, and action into a CPP ID. + * + * Create a 32-bit CPP identifier representing the access to be made. + * These identifiers are used as parameters to other NFP CPP functions. Some + * CPP devices may allow wildcard identifiers to be specified. + * + * @param[in] target NFP CPP target id + * @param[in] action NFP CPP action id + * @param[in] token NFP CPP token id + * @return NFP CPP ID + */ +#define NFP_CPP_ID(target, action, token) \ + ((((target) & 0x7f) << 24) | (((token) & 0xff) << 16) | \ + (((action) & 0xff) << 8)) + +#define NFP_CPP_ISLAND_ID(target, action, token, island) \ + ((((target) & 0x7f) << 24) | (((token) & 0xff) << 16) | \ + (((action) & 0xff) << 8) | (((island) & 0xff) << 0)) + +#ifndef _NFP_RESID_NO_C_FUNC + +/** + * Return the NFP CPP target of a NFP CPP ID + * @param[in] id NFP CPP ID + * @return NFP CPP target + */ +static inline uint8_t +NFP_CPP_ID_TARGET_of(uint32_t id) +{ + return (id >> 24) & NFP_CPP_TARGET_ID_MASK; +} + +/* + * Return the NFP CPP token of a NFP CPP ID + * @param[in] id NFP CPP ID + * @return NFP CPP token + */ +static inline uint8_t +NFP_CPP_ID_TOKEN_of(uint32_t id) +{ + return (id >> 16) & 0xff; +} + +/* + * Return the NFP CPP action of a NFP CPP ID + * @param[in] id NFP CPP ID + * @return NFP CPP action + */ +static inline uint8_t +NFP_CPP_ID_ACTION_of(uint32_t id) +{ + return (id >> 8) & 0xff; +} + +/* + * Return the NFP CPP action of a NFP CPP ID + * @param[in] id NFP CPP ID + * @return NFP CPP action + */ +static inline uint8_t +NFP_CPP_ID_ISLAND_of(uint32_t id) +{ + return (id) & 0xff; +} + +#endif /* _NFP_RESID_NO_C_FUNC */ + +/* + * Check if @p chip_family is an ARCH_TH chip. + * @param chip_family One of NFP_CHIP_FAMILY_* + */ +#define NFP_FAMILY_IS_ARCH_TH(chip_family) \ + ((int)(chip_family) == (int)NFP_CHIP_FAMILY_NFP6000) + +/* + * Get the NFP_CHIP_ARCH_* of @p chip_family. + * @param chip_family One of NFP_CHIP_FAMILY_* + */ +#define NFP_FAMILY_ARCH(x) \ + (__extension__ ({ \ + typeof(x) _x = (x); \ + (NFP_FAMILY_IS_ARCH_TH(_x) ? NFP_CHIP_ARCH_TH : \ + NFP_FAMILY_IS_ARCH_YD(_x) ? NFP_CHIP_ARCH_YD : -1) \ + })) + +/* + * Check if @p chip_family is an NFP-6xxx chip. + * @param chip_family One of NFP_CHIP_FAMILY_* + */ +#define NFP_FAMILY_IS_NFP6000(chip_family) \ + ((int)(chip_family) == (int)NFP_CHIP_FAMILY_NFP6000) + +/* + * Make microengine ID for NFP-6xxx. + * @param island_id Island ID. + * @param menum ME number, 0 based, within island. + * + * NOTE: menum should really be unsigned - MSC compiler throws error (not + * warning) if a clause is always true i.e. menum >= 0 if cluster_num is type + * unsigned int hence the cast of the menum to an int in that particular clause + */ +#define NFP6000_MEID(a, b) \ + (__extension__ ({ \ + typeof(a) _a = (a); \ + typeof(b) _b = (b); \ + (((((int)(_a) & 0x3F) == (int)(_a)) && \ + (((int)(_b) >= 0) && ((int)(_b) < 12))) ? \ + (int)(((_a) << 4) | ((_b) + 4)) : -1) \ + })) + +/* + * Do a general sanity check on the ME ID. + * The check is on the highest possible island ID for the chip family and the + * microengine number must be a master ID. + * @param meid ME ID as created by NFP6000_MEID + */ +#define NFP6000_MEID_IS_VALID(meid) \ + (__extension__ ({ \ + typeof(meid) _a = (meid); \ + ((((_a) >> 4) < 64) && (((_a) >> 4) >= 0) && \ + (((_a) & 0xF) >= 4)) \ + })) + +/* + * Extract island ID from ME ID. + * @param meid ME ID as created by NFP6000_MEID + */ +#define NFP6000_MEID_ISLAND_of(meid) (((meid) >> 4) & 0x3F) + +/* + * Extract microengine number (0 based) from ME ID. + * @param meid ME ID as created by NFP6000_MEID + */ +#define NFP6000_MEID_MENUM_of(meid) (((meid) & 0xF) - 4) + +/* + * Extract microengine group number (0 based) from ME ID. + * The group is two code-sharing microengines, so group 0 refers to MEs 0,1, + * group 1 refers to MEs 2,3 etc. + * @param meid ME ID as created by NFP6000_MEID + */ +#define NFP6000_MEID_MEGRP_of(meid) (NFP6000_MEID_MENUM_of(meid) >> 1) + +#ifndef _NFP_RESID_NO_C_FUNC + +/* + * Convert a string to an ME ID. + * + * @param s A string of format iX.meY + * @param endptr If non-NULL, *endptr will point to the trailing string + * after the ME ID part of the string, which is either + * an empty string or the first character after the separating + * period. + * @return ME ID on success, -1 on error. + */ +int nfp6000_idstr2meid(const char *s, const char **endptr); + +/* + * Extract island ID from string. + * + * Example: + * char *c; + * int val = nfp6000_idstr2island("i32.me5", &c); + * // val == 32, c == "me5" + * val = nfp6000_idstr2island("i32", &c); + * // val == 32, c == "" + * + * @param s A string of format "iX.anything" or "iX" + * @param endptr If non-NULL, *endptr will point to the trailing string + * after the island part of the string, which is either + * an empty string or the first character after the separating + * period. + * @return If successful, the island ID, -1 on error. + */ +int nfp6000_idstr2island(const char *s, const char **endptr); + +/* + * Extract microengine number from string. + * + * Example: + * char *c; + * int menum = nfp6000_idstr2menum("me5.anything", &c); + * // menum == 5, c == "anything" + * menum = nfp6000_idstr2menum("me5", &c); + * // menum == 5, c == "" + * + * @param s A string of format "meX.anything" or "meX" + * @param endptr If non-NULL, *endptr will point to the trailing string + * after the ME number part of the string, which is either + * an empty string or the first character after the separating + * period. + * @return If successful, the ME number, -1 on error. + */ +int nfp6000_idstr2menum(const char *s, const char **endptr); + +/* + * Extract context number from string. + * + * Example: + * char *c; + * int val = nfp6000_idstr2ctxnum("ctx5.anything", &c); + * // val == 5, c == "anything" + * val = nfp6000_idstr2ctxnum("ctx5", &c); + * // val == 5, c == "" + * + * @param s A string of format "ctxN.anything" or "ctxN" + * @param endptr If non-NULL, *endptr will point to the trailing string + * after the context number part of the string, which is either + * an empty string or the first character after the separating + * period. + * @return If successful, the context number, -1 on error. + */ +int nfp6000_idstr2ctxnum(const char *s, const char **endptr); + +/* + * Extract microengine group number from string. + * + * Example: + * char *c; + * int val = nfp6000_idstr2megrp("tg2.anything", &c); + * // val == 2, c == "anything" + * val = nfp6000_idstr2megrp("tg5", &c); + * // val == 2, c == "" + * + * @param s A string of format "tgX.anything" or "tgX" + * @param endptr If non-NULL, *endptr will point to the trailing string + * after the ME group part of the string, which is either + * an empty string or the first character after the separating + * period. + * @return If successful, the ME group number, -1 on error. + */ +int nfp6000_idstr2megrp(const char *s, const char **endptr); + +/* + * Create ME ID string of format "iX[.meY]". + * + * @param s Pointer to char buffer of size NFP_MEID_STR_SZ. + * The resulting string is output here. + * @param meid Microengine ID. + * @return Pointer to "s" on success, NULL on error. + */ +const char *nfp6000_meid2str(char *s, int meid); + +/* + * Create ME ID string of format "name[.meY]" or "iX[.meY]". + * + * @param s Pointer to char buffer of size NFP_MEID_STR_SZ. + * The resulting string is output here. + * @param meid Microengine ID. + * @return Pointer to "s" on success, NULL on error. + * + * Similar to nfp6000_meid2str() except use an alias instead of "iX" + * if one exists for the island. + */ +const char *nfp6000_meid2altstr(char *s, int meid); + +/* + * Create string of format "iX". + * + * @param s Pointer to char buffer of size NFP_MEID_STR_SZ. + * The resulting string is output here. + * @param island_id Island ID. + * @return Pointer to "s" on success, NULL on error. + */ +const char *nfp6000_island2str(char *s, int island_id); + +/* + * Create string of format "name", an island alias. + * + * @param s Pointer to char buffer of size NFP_MEID_STR_SZ. + * The resulting string is output here. + * @param island_id Island ID. + * @return Pointer to "s" on success, NULL on error. + */ +const char *nfp6000_island2altstr(char *s, int island_id); + +/* + * Create string of format "meY". + * + * @param s Pointer to char buffer of size NFP_MEID_STR_SZ. + * The resulting string is output here. + * @param menum Microengine number within island. + * @return Pointer to "s" on success, NULL on error. + */ +const char *nfp6000_menum2str(char *s, int menum); + +/* + * Create string of format "ctxY". + * + * @param s Pointer to char buffer of size NFP_MEID_STR_SZ. + * The resulting string is output here. + * @param ctxnum Context number within microengine. + * @return Pointer to "s" on success, NULL on error. + */ +const char *nfp6000_ctxnum2str(char *s, int ctxnum); + +/* + * Create string of format "tgY". + * + * @param s Pointer to char buffer of size NFP_MEID_STR_SZ. + * The resulting string is output here. + * @param megrp Microengine group number within cluster. + * @return Pointer to "s" on success, NULL on error. + */ +const char *nfp6000_megrp2str(char *s, int megrp); + +/* + * Convert a string to an ME ID. + * + * @param chip_family Chip family ID + * @param s A string of format iX.meY (or clX.meY) + * @param endptr If non-NULL, *endptr will point to the trailing + * string after the ME ID part of the string, which + * is either an empty string or the first character + * after the separating period. + * @return ME ID on success, -1 on error. + */ +int nfp_idstr2meid(int chip_family, const char *s, const char **endptr); + +/* + * Extract island ID from string. + * + * Example: + * char *c; + * int val = nfp_idstr2island(chip, "i32.me5", &c); + * // val == 32, c == "me5" + * val = nfp_idstr2island(chip, "i32", &c); + * // val == 32, c == "" + * + * @param chip_family Chip family ID + * @param s A string of format "iX.anything" or "iX" + * @param endptr If non-NULL, *endptr will point to the trailing + * striong after the ME ID part of the string, which + * is either an empty string or the first character + * after the separating period. + * @return The island ID on succes, -1 on error. + */ +int nfp_idstr2island(int chip_family, const char *s, const char **endptr); + +/* + * Extract microengine number from string. + * + * Example: + * char *c; + * int menum = nfp_idstr2menum("me5.anything", &c); + * // menum == 5, c == "anything" + * menum = nfp_idstr2menum("me5", &c); + * // menum == 5, c == "" + * + * @param chip_family Chip family ID + * @param s A string of format "meX.anything" or "meX" + * @param endptr If non-NULL, *endptr will point to the trailing + * striong after the ME ID part of the string, which + * is either an empty string or the first character + * after the separating period. + * @return The ME number on succes, -1 on error. + */ +int nfp_idstr2menum(int chip_family, const char *s, const char **endptr); + +/* + * Extract context number from string. + * + * Example: + * char *c; + * int val = nfp_idstr2ctxnum("ctx5.anything", &c); + * // val == 5, c == "anything" + * val = nfp_idstr2ctxnum("ctx5", &c); + * // val == 5, c == "" + * + * @param s A string of format "ctxN.anything" or "ctxN" + * @param endptr If non-NULL, *endptr will point to the trailing string + * after the context number part of the string, which is either + * an empty string or the first character after the separating + * period. + * @return If successful, the context number, -1 on error. + */ +int nfp_idstr2ctxnum(int chip_family, const char *s, const char **endptr); + +/* + * Extract microengine group number from string. + * + * Example: + * char *c; + * int val = nfp_idstr2megrp("tg2.anything", &c); + * // val == 2, c == "anything" + * val = nfp_idstr2megrp("tg5", &c); + * // val == 5, c == "" + * + * @param s A string of format "tgX.anything" or "tgX" + * @param endptr If non-NULL, *endptr will point to the trailing string + * after the ME group part of the string, which is either + * an empty string or the first character after the separating + * period. + * @return If successful, the ME group number, -1 on error. + */ +int nfp_idstr2megrp(int chip_family, const char *s, const char **endptr); + +/* + * Create ME ID string of format "iX[.meY]". + * + * @param chip_family Chip family ID + * @param s Pointer to char buffer of size NFP_MEID_STR_SZ. + * The resulting string is output here. + * @param meid Microengine ID. + * @return Pointer to "s" on success, NULL on error. + */ +const char *nfp_meid2str(int chip_family, char *s, int meid); + +/* + * Create ME ID string of format "name[.meY]" or "iX[.meY]". + * + * @param chip_family Chip family ID + * @param s Pointer to char buffer of size NFP_MEID_STR_SZ. + * The resulting string is output here. + * @param meid Microengine ID. + * @return Pointer to "s" on success, NULL on error. + * + * Similar to nfp_meid2str() except use an alias instead of "iX" + * if one exists for the island. + */ +const char *nfp_meid2altstr(int chip_family, char *s, int meid); + +/* + * Create string of format "iX". + * + * @param chip_family Chip family ID + * @param s Pointer to char buffer of size NFP_MEID_STR_SZ. + * The resulting string is output here. + * @param island_id Island ID. + * @return Pointer to "s" on success, NULL on error. + */ +const char *nfp_island2str(int chip_family, char *s, int island_id); + +/* + * Create string of format "name", an island alias. + * + * @param chip_family Chip family ID + * @param s Pointer to char buffer of size NFP_MEID_STR_SZ. + * The resulting string is output here. + * @param island_id Island ID. + * @return Pointer to "s" on success, NULL on error. + */ +const char *nfp_island2altstr(int chip_family, char *s, int island_id); + +/* + * Create string of format "meY". + * + * @param chip_family Chip family ID + * @param s Pointer to char buffer of size NFP_MEID_STR_SZ. + * The resulting string is output here. + * @param menum Microengine number within island. + * @return Pointer to "s" on success, NULL on error. + */ +const char *nfp_menum2str(int chip_family, char *s, int menum); + +/* + * Create string of format "ctxY". + * + * @param s Pointer to char buffer of size NFP_MEID_STR_SZ. + * The resulting string is output here. + * @param ctxnum Context number within microengine. + * @return Pointer to "s" on success, NULL on error. + */ +const char *nfp_ctxnum2str(int chip_family, char *s, int ctxnum); + +/* + * Create string of format "tgY". + * + * @param s Pointer to char buffer of size NFP_MEID_STR_SZ. + * The resulting string is output here. + * @param megrp Microengine group number within cluster. + * @return Pointer to "s" on success, NULL on error. + */ +const char *nfp_megrp2str(int chip_family, char *s, int megrp); + +/* + * Convert a two character string to revision number. + * + * Revision integer is 0x00 for A0, 0x11 for B1 etc. + * + * @param s Two character string. + * @return Revision number, -1 on error + */ +int nfp_idstr2rev(const char *s); + +/* + * Create string from revision number. + * + * String will be upper case. + * + * @param s Pointer to char buffer with size of at least 3 + * for 2 characters and string terminator. + * @param rev Revision number. + * @return Pointer to "s" on success, NULL on error. + */ +const char *nfp_rev2str(char *s, int rev); + +/* + * Get the NFP CPP address from a string + * + * String is in the format [island@]target[:[action:[token:]]address] + * + * @param chip_family Chip family ID + * @param tid Pointer to string to parse + * @param cpp_idp Pointer to CPP ID + * @param cpp_addrp Pointer to CPP address + * @return 0 on success, or -1 and errno + */ +int nfp_str2cpp(int chip_family, + const char *tid, + uint32_t *cpp_idp, + uint64_t *cpp_addrp); + + +#endif /* _NFP_RESID_NO_C_FUNC */ + +#endif /* __NFP_RESID_H__ */ diff --git a/drivers/net/nfp/nfpcore/nfp6000/nfp6000.h b/drivers/net/nfp/nfpcore/nfp6000/nfp6000.h new file mode 100644 index 00000000..47e1ddae --- /dev/null +++ b/drivers/net/nfp/nfpcore/nfp6000/nfp6000.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2018 Netronome Systems, Inc. + * All rights reserved. + */ + +#ifndef __NFP_NFP6000_H__ +#define __NFP_NFP6000_H__ + +/* CPP Target IDs */ +#define NFP_CPP_TARGET_INVALID 0 +#define NFP_CPP_TARGET_NBI 1 +#define NFP_CPP_TARGET_QDR 2 +#define NFP_CPP_TARGET_ILA 6 +#define NFP_CPP_TARGET_MU 7 +#define NFP_CPP_TARGET_PCIE 9 +#define NFP_CPP_TARGET_ARM 10 +#define NFP_CPP_TARGET_CRYPTO 12 +#define NFP_CPP_TARGET_ISLAND_XPB 14 /* Shared with CAP */ +#define NFP_CPP_TARGET_ISLAND_CAP 14 /* Shared with XPB */ +#define NFP_CPP_TARGET_CT_XPB 14 +#define NFP_CPP_TARGET_LOCAL_SCRATCH 15 +#define NFP_CPP_TARGET_CLS NFP_CPP_TARGET_LOCAL_SCRATCH + +#define NFP_ISL_EMEM0 24 + +#define NFP_MU_ADDR_ACCESS_TYPE_MASK 3ULL +#define NFP_MU_ADDR_ACCESS_TYPE_DIRECT 2ULL + +static inline int +nfp_cppat_mu_locality_lsb(int mode, int addr40) +{ + switch (mode) { + case 0 ... 3: + return addr40 ? 38 : 30; + default: + return -EINVAL; + } +} + +#endif /* NFP_NFP6000_H */ diff --git a/drivers/net/nfp/nfpcore/nfp6000/nfp_xpb.h b/drivers/net/nfp/nfpcore/nfp6000/nfp_xpb.h new file mode 100644 index 00000000..7ada1bb2 --- /dev/null +++ b/drivers/net/nfp/nfpcore/nfp6000/nfp_xpb.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2018 Netronome Systems, Inc. + * All rights reserved. + */ + +#ifndef __NFP_XPB_H__ +#define __NFP_XPB_H__ + +/* + * For use with NFP6000 Databook "XPB Addressing" section + */ +#define NFP_XPB_OVERLAY(island) (((island) & 0x3f) << 24) + +#define NFP_XPB_ISLAND(island) (NFP_XPB_OVERLAY(island) + 0x60000) + +#define NFP_XPB_ISLAND_of(offset) (((offset) >> 24) & 0x3F) + +/* + * For use with NFP6000 Databook "XPB Island and Device IDs" chapter + */ +#define NFP_XPB_DEVICE(island, slave, device) \ + (NFP_XPB_OVERLAY(island) | \ + (((slave) & 3) << 22) | \ + (((device) & 0x3f) << 16)) + +#endif /* NFP_XPB_H */ diff --git a/drivers/net/nfp/nfpcore/nfp_cpp.h b/drivers/net/nfp/nfpcore/nfp_cpp.h new file mode 100644 index 00000000..1427954c --- /dev/null +++ b/drivers/net/nfp/nfpcore/nfp_cpp.h @@ -0,0 +1,781 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2018 Netronome Systems, Inc. + * All rights reserved. + */ + +#ifndef __NFP_CPP_H__ +#define __NFP_CPP_H__ + +#include <rte_ethdev_pci.h> + +#include "nfp-common/nfp_platform.h" +#include "nfp-common/nfp_resid.h" + +struct nfp_cpp_mutex; + +/* + * NFP CPP handle + */ +struct nfp_cpp { + uint32_t model; + uint32_t interface; + uint8_t *serial; + int serial_len; + void *priv; + + /* Mutex cache */ + struct nfp_cpp_mutex *mutex_cache; + const struct nfp_cpp_operations *op; + + /* + * NFP-6xxx originating island IMB CPP Address Translation. CPP Target + * ID is index into array. Values are obtained at runtime from local + * island XPB CSRs. + */ + uint32_t imb_cat_table[16]; + + int driver_lock_needed; +}; + +/* + * NFP CPP device area handle + */ +struct nfp_cpp_area { + struct nfp_cpp *cpp; + char *name; + unsigned long long offset; + unsigned long size; + /* Here follows the 'priv' part of nfp_cpp_area. */ +}; + +/* + * NFP CPP operations structure + */ +struct nfp_cpp_operations { + /* Size of priv area in struct nfp_cpp_area */ + size_t area_priv_size; + + /* Instance an NFP CPP */ + int (*init)(struct nfp_cpp *cpp, struct rte_pci_device *dev); + + /* + * Free the bus. + * Called only once, during nfp_cpp_unregister() + */ + void (*free)(struct nfp_cpp *cpp); + + /* + * Initialize a new NFP CPP area + * NOTE: This is _not_ serialized + */ + int (*area_init)(struct nfp_cpp_area *area, + uint32_t dest, + unsigned long long address, + unsigned long size); + /* + * Clean up a NFP CPP area before it is freed + * NOTE: This is _not_ serialized + */ + void (*area_cleanup)(struct nfp_cpp_area *area); + + /* + * Acquire resources for a NFP CPP area + * Serialized + */ + int (*area_acquire)(struct nfp_cpp_area *area); + /* + * Release resources for a NFP CPP area + * Serialized + */ + void (*area_release)(struct nfp_cpp_area *area); + /* + * Return a void IO pointer to a NFP CPP area + * NOTE: This is _not_ serialized + */ + + void *(*area_iomem)(struct nfp_cpp_area *area); + + void *(*area_mapped)(struct nfp_cpp_area *area); + /* + * Perform a read from a NFP CPP area + * Serialized + */ + int (*area_read)(struct nfp_cpp_area *area, + void *kernel_vaddr, + unsigned long offset, + unsigned int length); + /* + * Perform a write to a NFP CPP area + * Serialized + */ + int (*area_write)(struct nfp_cpp_area *area, + const void *kernel_vaddr, + unsigned long offset, + unsigned int length); +}; + +/* + * This should be the only external function the transport + * module supplies + */ +const struct nfp_cpp_operations *nfp_cpp_transport_operations(void); + +/* + * Set the model id + * + * @param cpp NFP CPP operations structure + * @param model Model ID + */ +void nfp_cpp_model_set(struct nfp_cpp *cpp, uint32_t model); + +/* + * Set the private instance owned data of a nfp_cpp struct + * + * @param cpp NFP CPP operations structure + * @param interface Interface ID + */ +void nfp_cpp_interface_set(struct nfp_cpp *cpp, uint32_t interface); + +/* + * Set the private instance owned data of a nfp_cpp struct + * + * @param cpp NFP CPP operations structure + * @param serial NFP serial byte array + * @param len Length of the serial byte array + */ +int nfp_cpp_serial_set(struct nfp_cpp *cpp, const uint8_t *serial, + size_t serial_len); + +/* + * Set the private data of the nfp_cpp instance + * + * @param cpp NFP CPP operations structure + * @return Opaque device pointer + */ +void nfp_cpp_priv_set(struct nfp_cpp *cpp, void *priv); + +/* + * Return the private data of the nfp_cpp instance + * + * @param cpp NFP CPP operations structure + * @return Opaque device pointer + */ +void *nfp_cpp_priv(struct nfp_cpp *cpp); + +/* + * Get the privately allocated portion of a NFP CPP area handle + * + * @param cpp_area NFP CPP area handle + * @return Pointer to the private area, or NULL on failure + */ +void *nfp_cpp_area_priv(struct nfp_cpp_area *cpp_area); + +uint32_t __nfp_cpp_model_autodetect(struct nfp_cpp *cpp); + +/* + * NFP CPP core interface for CPP clients. + */ + +/* + * Open a NFP CPP handle to a CPP device + * + * @param[in] id 0-based ID for the CPP interface to use + * + * @return NFP CPP handle, or NULL on failure (and set errno accordingly). + */ +struct nfp_cpp *nfp_cpp_from_device_name(struct rte_pci_device *dev, + int driver_lock_needed); + +/* + * Free a NFP CPP handle + * + * @param[in] cpp NFP CPP handle + */ +void nfp_cpp_free(struct nfp_cpp *cpp); + +#define NFP_CPP_MODEL_INVALID 0xffffffff + +/* + * NFP_CPP_MODEL_CHIP_of - retrieve the chip ID from the model ID + * + * The chip ID is a 16-bit BCD+A-F encoding for the chip type. + * + * @param[in] model NFP CPP model id + * @return NFP CPP chip id + */ +#define NFP_CPP_MODEL_CHIP_of(model) (((model) >> 16) & 0xffff) + +/* + * NFP_CPP_MODEL_IS_6000 - Check for the NFP6000 family of devices + * + * NOTE: The NFP4000 series is considered as a NFP6000 series variant. + * + * @param[in] model NFP CPP model id + * @return true if model is in the NFP6000 family, false otherwise. + */ +#define NFP_CPP_MODEL_IS_6000(model) \ + ((NFP_CPP_MODEL_CHIP_of(model) >= 0x4000) && \ + (NFP_CPP_MODEL_CHIP_of(model) < 0x7000)) + +/* + * nfp_cpp_model - Retrieve the Model ID of the NFP + * + * @param[in] cpp NFP CPP handle + * @return NFP CPP Model ID + */ +uint32_t nfp_cpp_model(struct nfp_cpp *cpp); + +/* + * NFP Interface types - logical interface for this CPP connection 4 bits are + * reserved for interface type. + */ +#define NFP_CPP_INTERFACE_TYPE_INVALID 0x0 +#define NFP_CPP_INTERFACE_TYPE_PCI 0x1 +#define NFP_CPP_INTERFACE_TYPE_ARM 0x2 +#define NFP_CPP_INTERFACE_TYPE_RPC 0x3 +#define NFP_CPP_INTERFACE_TYPE_ILA 0x4 + +/* + * Construct a 16-bit NFP Interface ID + * + * Interface IDs consists of 4 bits of interface type, 4 bits of unit + * identifier, and 8 bits of channel identifier. + * + * The NFP Interface ID is used in the implementation of NFP CPP API mutexes, + * which use the MU Atomic CompareAndWrite operation - hence the limit to 16 + * bits to be able to use the NFP Interface ID as a lock owner. + * + * @param[in] type NFP Interface Type + * @param[in] unit Unit identifier for the interface type + * @param[in] channel Channel identifier for the interface unit + * @return Interface ID + */ +#define NFP_CPP_INTERFACE(type, unit, channel) \ + ((((type) & 0xf) << 12) | \ + (((unit) & 0xf) << 8) | \ + (((channel) & 0xff) << 0)) + +/* + * Get the interface type of a NFP Interface ID + * @param[in] interface NFP Interface ID + * @return NFP Interface ID's type + */ +#define NFP_CPP_INTERFACE_TYPE_of(interface) (((interface) >> 12) & 0xf) + +/* + * Get the interface unit of a NFP Interface ID + * @param[in] interface NFP Interface ID + * @return NFP Interface ID's unit + */ +#define NFP_CPP_INTERFACE_UNIT_of(interface) (((interface) >> 8) & 0xf) + +/* + * Get the interface channel of a NFP Interface ID + * @param[in] interface NFP Interface ID + * @return NFP Interface ID's channel + */ +#define NFP_CPP_INTERFACE_CHANNEL_of(interface) (((interface) >> 0) & 0xff) + +/* + * Retrieve the Interface ID of the NFP + * @param[in] cpp NFP CPP handle + * @return NFP CPP Interface ID + */ +uint16_t nfp_cpp_interface(struct nfp_cpp *cpp); + +/* + * Retrieve the NFP Serial Number (unique per NFP) + * @param[in] cpp NFP CPP handle + * @param[out] serial Pointer to reference the serial number array + * + * @return size of the NFP6000 serial number, in bytes + */ +int nfp_cpp_serial(struct nfp_cpp *cpp, const uint8_t **serial); + +/* + * Allocate a NFP CPP area handle, as an offset into a CPP ID + * @param[in] cpp NFP CPP handle + * @param[in] cpp_id NFP CPP ID + * @param[in] address Offset into the NFP CPP ID address space + * @param[in] size Size of the area to reserve + * + * @return NFP CPP handle, or NULL on failure (and set errno accordingly). + */ +struct nfp_cpp_area *nfp_cpp_area_alloc(struct nfp_cpp *cpp, uint32_t cpp_id, + unsigned long long address, + unsigned long size); + +/* + * Allocate a NFP CPP area handle, as an offset into a CPP ID, by a named owner + * @param[in] cpp NFP CPP handle + * @param[in] cpp_id NFP CPP ID + * @param[in] name Name of owner of the area + * @param[in] address Offset into the NFP CPP ID address space + * @param[in] size Size of the area to reserve + * + * @return NFP CPP handle, or NULL on failure (and set errno accordingly). + */ +struct nfp_cpp_area *nfp_cpp_area_alloc_with_name(struct nfp_cpp *cpp, + uint32_t cpp_id, + const char *name, + unsigned long long address, + unsigned long size); + +/* + * Free an allocated NFP CPP area handle + * @param[in] area NFP CPP area handle + */ +void nfp_cpp_area_free(struct nfp_cpp_area *area); + +/* + * Acquire the resources needed to access the NFP CPP area handle + * + * @param[in] area NFP CPP area handle + * + * @return 0 on success, -1 on failure (and set errno accordingly). + */ +int nfp_cpp_area_acquire(struct nfp_cpp_area *area); + +/* + * Release the resources needed to access the NFP CPP area handle + * + * @param[in] area NFP CPP area handle + */ +void nfp_cpp_area_release(struct nfp_cpp_area *area); + +/* + * Allocate, then acquire the resources needed to access the NFP CPP area handle + * @param[in] cpp NFP CPP handle + * @param[in] cpp_id NFP CPP ID + * @param[in] address Offset into the NFP CPP ID address space + * @param[in] size Size of the area to reserve + * + * @return NFP CPP handle, or NULL on failure (and set errno accordingly). + */ +struct nfp_cpp_area *nfp_cpp_area_alloc_acquire(struct nfp_cpp *cpp, + uint32_t cpp_id, + unsigned long long address, + unsigned long size); + +/* + * Release the resources, then free the NFP CPP area handle + * @param[in] area NFP CPP area handle + */ +void nfp_cpp_area_release_free(struct nfp_cpp_area *area); + +uint8_t *nfp_cpp_map_area(struct nfp_cpp *cpp, int domain, int target, + uint64_t addr, unsigned long size, + struct nfp_cpp_area **area); +/* + * Return an IO pointer to the beginning of the NFP CPP area handle. The area + * must be acquired with 'nfp_cpp_area_acquire()' before calling this operation. + * + * @param[in] area NFP CPP area handle + * + * @return Pointer to IO memory, or NULL on failure (and set errno accordingly). + */ +void *nfp_cpp_area_mapped(struct nfp_cpp_area *area); + +/* + * Read from a NFP CPP area handle into a buffer. The area must be acquired with + * 'nfp_cpp_area_acquire()' before calling this operation. + * + * @param[in] area NFP CPP area handle + * @param[in] offset Offset into the area + * @param[in] buffer Location of buffer to receive the data + * @param[in] length Length of the data to read + * + * @return bytes read on success, -1 on failure (and set errno accordingly). + * + */ +int nfp_cpp_area_read(struct nfp_cpp_area *area, unsigned long offset, + void *buffer, size_t length); + +/* + * Write to a NFP CPP area handle from a buffer. The area must be acquired with + * 'nfp_cpp_area_acquire()' before calling this operation. + * + * @param[in] area NFP CPP area handle + * @param[in] offset Offset into the area + * @param[in] buffer Location of buffer that holds the data + * @param[in] length Length of the data to read + * + * @return bytes written on success, -1 on failure (and set errno accordingly). + */ +int nfp_cpp_area_write(struct nfp_cpp_area *area, unsigned long offset, + const void *buffer, size_t length); + +/* + * nfp_cpp_area_iomem() - get IOMEM region for CPP area + * @area: CPP area handle + * + * Returns an iomem pointer for use with readl()/writel() style operations. + * + * NOTE: Area must have been locked down with an 'acquire'. + * + * Return: pointer to the area, or NULL + */ +void *nfp_cpp_area_iomem(struct nfp_cpp_area *area); + +/* + * Verify that IO can be performed on an offset in an area + * + * @param[in] area NFP CPP area handle + * @param[in] offset Offset into the area + * @param[in] size Size of region to validate + * + * @return 0 on success, -1 on failure (and set errno accordingly). + */ +int nfp_cpp_area_check_range(struct nfp_cpp_area *area, + unsigned long long offset, unsigned long size); + +/* + * Get the NFP CPP handle that is the parent of a NFP CPP area handle + * + * @param cpp_area NFP CPP area handle + * @return NFP CPP handle + */ +struct nfp_cpp *nfp_cpp_area_cpp(struct nfp_cpp_area *cpp_area); + +/* + * Get the name passed during allocation of the NFP CPP area handle + * + * @param cpp_area NFP CPP area handle + * @return Pointer to the area's name + */ +const char *nfp_cpp_area_name(struct nfp_cpp_area *cpp_area); + +/* + * Read a block of data from a NFP CPP ID + * + * @param[in] cpp NFP CPP handle + * @param[in] cpp_id NFP CPP ID + * @param[in] address Offset into the NFP CPP ID address space + * @param[in] kernel_vaddr Buffer to copy read data to + * @param[in] length Size of the area to reserve + * + * @return bytes read on success, -1 on failure (and set errno accordingly). + */ +int nfp_cpp_read(struct nfp_cpp *cpp, uint32_t cpp_id, + unsigned long long address, void *kernel_vaddr, size_t length); + +/* + * Write a block of data to a NFP CPP ID + * + * @param[in] cpp NFP CPP handle + * @param[in] cpp_id NFP CPP ID + * @param[in] address Offset into the NFP CPP ID address space + * @param[in] kernel_vaddr Buffer to copy write data from + * @param[in] length Size of the area to reserve + * + * @return bytes written on success, -1 on failure (and set errno accordingly). + */ +int nfp_cpp_write(struct nfp_cpp *cpp, uint32_t cpp_id, + unsigned long long address, const void *kernel_vaddr, + size_t length); + + + +/* + * Fill a NFP CPP area handle and offset with a value + * + * @param[in] area NFP CPP area handle + * @param[in] offset Offset into the NFP CPP ID address space + * @param[in] value 32-bit value to fill area with + * @param[in] length Size of the area to reserve + * + * @return bytes written on success, -1 on failure (and set errno accordingly). + */ +int nfp_cpp_area_fill(struct nfp_cpp_area *area, unsigned long offset, + uint32_t value, size_t length); + +/* + * Read a single 32-bit value from a NFP CPP area handle + * + * @param area NFP CPP area handle + * @param offset offset into NFP CPP area handle + * @param value output value + * + * The area must be acquired with 'nfp_cpp_area_acquire()' before calling this + * operation. + * + * NOTE: offset must be 32-bit aligned. + * + * @return 0 on success, or -1 on error (and set errno accordingly). + */ +int nfp_cpp_area_readl(struct nfp_cpp_area *area, unsigned long offset, + uint32_t *value); + +/* + * Write a single 32-bit value to a NFP CPP area handle + * + * @param area NFP CPP area handle + * @param offset offset into NFP CPP area handle + * @param value value to write + * + * The area must be acquired with 'nfp_cpp_area_acquire()' before calling this + * operation. + * + * NOTE: offset must be 32-bit aligned. + * + * @return 0 on success, or -1 on error (and set errno accordingly). + */ +int nfp_cpp_area_writel(struct nfp_cpp_area *area, unsigned long offset, + uint32_t value); + +/* + * Read a single 64-bit value from a NFP CPP area handle + * + * @param area NFP CPP area handle + * @param offset offset into NFP CPP area handle + * @param value output value + * + * The area must be acquired with 'nfp_cpp_area_acquire()' before calling this + * operation. + * + * NOTE: offset must be 64-bit aligned. + * + * @return 0 on success, or -1 on error (and set errno accordingly). + */ +int nfp_cpp_area_readq(struct nfp_cpp_area *area, unsigned long offset, + uint64_t *value); + +/* + * Write a single 64-bit value to a NFP CPP area handle + * + * @param area NFP CPP area handle + * @param offset offset into NFP CPP area handle + * @param value value to write + * + * The area must be acquired with 'nfp_cpp_area_acquire()' before calling this + * operation. + * + * NOTE: offset must be 64-bit aligned. + * + * @return 0 on success, or -1 on error (and set errno accordingly). + */ +int nfp_cpp_area_writeq(struct nfp_cpp_area *area, unsigned long offset, + uint64_t value); + +/* + * Write a single 32-bit value on the XPB bus + * + * @param cpp NFP CPP device handle + * @param xpb_tgt XPB target and address + * @param value value to write + * + * @return 0 on success, or -1 on failure (and set errno accordingly). + */ +int nfp_xpb_writel(struct nfp_cpp *cpp, uint32_t xpb_tgt, uint32_t value); + +/* + * Read a single 32-bit value from the XPB bus + * + * @param cpp NFP CPP device handle + * @param xpb_tgt XPB target and address + * @param value output value + * + * @return 0 on success, or -1 on failure (and set errno accordingly). + */ +int nfp_xpb_readl(struct nfp_cpp *cpp, uint32_t xpb_tgt, uint32_t *value); + +/* + * Modify bits of a 32-bit value from the XPB bus + * + * @param cpp NFP CPP device handle + * @param xpb_tgt XPB target and address + * @param mask mask of bits to alter + * @param value value to modify + * + * @return 0 on success, or -1 on failure (and set errno accordingly). + */ +int nfp_xpb_writelm(struct nfp_cpp *cpp, uint32_t xpb_tgt, uint32_t mask, + uint32_t value); + +/* + * Modify bits of a 32-bit value from the XPB bus + * + * @param cpp NFP CPP device handle + * @param xpb_tgt XPB target and address + * @param mask mask of bits to alter + * @param value value to monitor for + * @param timeout_us maximum number of us to wait (-1 for forever) + * + * @return >= 0 on success, or -1 on failure (and set errno accordingly). + */ +int nfp_xpb_waitlm(struct nfp_cpp *cpp, uint32_t xpb_tgt, uint32_t mask, + uint32_t value, int timeout_us); + +/* + * Read a 32-bit word from a NFP CPP ID + * + * @param cpp NFP CPP handle + * @param cpp_id NFP CPP ID + * @param address offset into the NFP CPP ID address space + * @param value output value + * + * @return 0 on success, or -1 on failure (and set errno accordingly). + */ +int nfp_cpp_readl(struct nfp_cpp *cpp, uint32_t cpp_id, + unsigned long long address, uint32_t *value); + +/* + * Write a 32-bit value to a NFP CPP ID + * + * @param cpp NFP CPP handle + * @param cpp_id NFP CPP ID + * @param address offset into the NFP CPP ID address space + * @param value value to write + * + * @return 0 on success, or -1 on failure (and set errno accordingly). + * + */ +int nfp_cpp_writel(struct nfp_cpp *cpp, uint32_t cpp_id, + unsigned long long address, uint32_t value); + +/* + * Read a 64-bit work from a NFP CPP ID + * + * @param cpp NFP CPP handle + * @param cpp_id NFP CPP ID + * @param address offset into the NFP CPP ID address space + * @param value output value + * + * @return 0 on success, or -1 on failure (and set errno accordingly). + */ +int nfp_cpp_readq(struct nfp_cpp *cpp, uint32_t cpp_id, + unsigned long long address, uint64_t *value); + +/* + * Write a 64-bit value to a NFP CPP ID + * + * @param cpp NFP CPP handle + * @param cpp_id NFP CPP ID + * @param address offset into the NFP CPP ID address space + * @param value value to write + * + * @return 0 on success, or -1 on failure (and set errno accordingly). + */ +int nfp_cpp_writeq(struct nfp_cpp *cpp, uint32_t cpp_id, + unsigned long long address, uint64_t value); + +/* + * Initialize a mutex location + + * The CPP target:address must point to a 64-bit aligned location, and will + * initialize 64 bits of data at the location. + * + * This creates the initial mutex state, as locked by this nfp_cpp_interface(). + * + * This function should only be called when setting up the initial lock state + * upon boot-up of the system. + * + * @param cpp NFP CPP handle + * @param target NFP CPP target ID + * @param address Offset into the address space of the NFP CPP target ID + * @param key_id Unique 32-bit value for this mutex + * + * @return 0 on success, or -1 on failure (and set errno accordingly). + */ +int nfp_cpp_mutex_init(struct nfp_cpp *cpp, int target, + unsigned long long address, uint32_t key_id); + +/* + * Create a mutex handle from an address controlled by a MU Atomic engine + * + * The CPP target:address must point to a 64-bit aligned location, and reserve + * 64 bits of data at the location for use by the handle. + * + * Only target/address pairs that point to entities that support the MU Atomic + * Engine's CmpAndSwap32 command are supported. + * + * @param cpp NFP CPP handle + * @param target NFP CPP target ID + * @param address Offset into the address space of the NFP CPP target ID + * @param key_id 32-bit unique key (must match the key at this location) + * + * @return A non-NULL struct nfp_cpp_mutex * on success, NULL on + * failure. + */ +struct nfp_cpp_mutex *nfp_cpp_mutex_alloc(struct nfp_cpp *cpp, int target, + unsigned long long address, + uint32_t key_id); + +/* + * Get the NFP CPP handle the mutex was created with + * + * @param mutex NFP mutex handle + * @return NFP CPP handle + */ +struct nfp_cpp *nfp_cpp_mutex_cpp(struct nfp_cpp_mutex *mutex); + +/* + * Get the mutex key + * + * @param mutex NFP mutex handle + * @return Mutex key + */ +uint32_t nfp_cpp_mutex_key(struct nfp_cpp_mutex *mutex); + +/* + * Get the mutex owner + * + * @param mutex NFP mutex handle + * @return Interface ID of the mutex owner + * + * NOTE: This is for debug purposes ONLY - the owner may change at any time, + * unless it has been locked by this NFP CPP handle. + */ +uint16_t nfp_cpp_mutex_owner(struct nfp_cpp_mutex *mutex); + +/* + * Get the mutex target + * + * @param mutex NFP mutex handle + * @return Mutex CPP target (ie NFP_CPP_TARGET_MU) + */ +int nfp_cpp_mutex_target(struct nfp_cpp_mutex *mutex); + +/* + * Get the mutex address + * + * @param mutex NFP mutex handle + * @return Mutex CPP address + */ +uint64_t nfp_cpp_mutex_address(struct nfp_cpp_mutex *mutex); + +/* + * Free a mutex handle - does not alter the lock state + * + * @param mutex NFP CPP Mutex handle + */ +void nfp_cpp_mutex_free(struct nfp_cpp_mutex *mutex); + +/* + * Lock a mutex handle, using the NFP MU Atomic Engine + * + * @param mutex NFP CPP Mutex handle + * + * @return 0 on success, or -1 on failure (and set errno accordingly). + */ +int nfp_cpp_mutex_lock(struct nfp_cpp_mutex *mutex); + +/* + * Unlock a mutex handle, using the NFP MU Atomic Engine + * + * @param mutex NFP CPP Mutex handle + * + * @return 0 on success, or -1 on failure (and set errno accordingly). + */ +int nfp_cpp_mutex_unlock(struct nfp_cpp_mutex *mutex); + +/* + * Attempt to lock a mutex handle, using the NFP MU Atomic Engine + * + * @param mutex NFP CPP Mutex handle + * @return 0 if the lock succeeded, -1 on failure (and errno set + * appropriately). + */ +int nfp_cpp_mutex_trylock(struct nfp_cpp_mutex *mutex); + +#endif /* !__NFP_CPP_H__ */ diff --git a/drivers/net/nfp/nfpcore/nfp_cpp_pcie_ops.c b/drivers/net/nfp/nfpcore/nfp_cpp_pcie_ops.c new file mode 100644 index 00000000..c68d9400 --- /dev/null +++ b/drivers/net/nfp/nfpcore/nfp_cpp_pcie_ops.c @@ -0,0 +1,845 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2018 Netronome Systems, Inc. + * All rights reserved. + */ + +/* + * nfp_cpp_pcie_ops.c + * Authors: Vinayak Tammineedi <vinayak.tammineedi@netronome.com> + * + * Multiplexes the NFP BARs between NFP internal resources and + * implements the PCIe specific interface for generic CPP bus access. + * + * The BARs are managed and allocated if they are available. + * The generic CPP bus abstraction builds upon this BAR interface. + */ + +#include <assert.h> +#include <stdio.h> +#include <execinfo.h> +#include <stdlib.h> +#include <unistd.h> +#include <stdint.h> +#include <stdbool.h> +#include <fcntl.h> +#include <string.h> +#include <errno.h> +#include <dirent.h> +#include <libgen.h> + +#include <sys/mman.h> +#include <sys/file.h> +#include <sys/stat.h> + +#include <rte_ethdev_pci.h> +#include <rte_string_fns.h> + +#include "nfp_cpp.h" +#include "nfp_target.h" +#include "nfp6000/nfp6000.h" + +#define NFP_PCIE_BAR(_pf) (0x30000 + ((_pf) & 7) * 0xc0) + +#define NFP_PCIE_BAR_PCIE2CPP_ACTION_BASEADDRESS(_x) (((_x) & 0x1f) << 16) +#define NFP_PCIE_BAR_PCIE2CPP_BASEADDRESS(_x) (((_x) & 0xffff) << 0) +#define NFP_PCIE_BAR_PCIE2CPP_LENGTHSELECT(_x) (((_x) & 0x3) << 27) +#define NFP_PCIE_BAR_PCIE2CPP_LENGTHSELECT_32BIT 0 +#define NFP_PCIE_BAR_PCIE2CPP_LENGTHSELECT_64BIT 1 +#define NFP_PCIE_BAR_PCIE2CPP_LENGTHSELECT_0BYTE 3 +#define NFP_PCIE_BAR_PCIE2CPP_MAPTYPE(_x) (((_x) & 0x7) << 29) +#define NFP_PCIE_BAR_PCIE2CPP_MAPTYPE_OF(_x) (((_x) >> 29) & 0x7) +#define NFP_PCIE_BAR_PCIE2CPP_MAPTYPE_FIXED 0 +#define NFP_PCIE_BAR_PCIE2CPP_MAPTYPE_BULK 1 +#define NFP_PCIE_BAR_PCIE2CPP_MAPTYPE_TARGET 2 +#define NFP_PCIE_BAR_PCIE2CPP_MAPTYPE_GENERAL 3 +#define NFP_PCIE_BAR_PCIE2CPP_TARGET_BASEADDRESS(_x) (((_x) & 0xf) << 23) +#define NFP_PCIE_BAR_PCIE2CPP_TOKEN_BASEADDRESS(_x) (((_x) & 0x3) << 21) + +/* + * Minimal size of the PCIe cfg memory we depend on being mapped, + * queue controller and DMA controller don't have to be covered. + */ +#define NFP_PCI_MIN_MAP_SIZE 0x080000 + +#define NFP_PCIE_P2C_FIXED_SIZE(bar) (1 << (bar)->bitsize) +#define NFP_PCIE_P2C_BULK_SIZE(bar) (1 << (bar)->bitsize) +#define NFP_PCIE_P2C_GENERAL_TARGET_OFFSET(bar, x) ((x) << ((bar)->bitsize - 2)) +#define NFP_PCIE_P2C_GENERAL_TOKEN_OFFSET(bar, x) ((x) << ((bar)->bitsize - 4)) +#define NFP_PCIE_P2C_GENERAL_SIZE(bar) (1 << ((bar)->bitsize - 4)) + +#define NFP_PCIE_CFG_BAR_PCIETOCPPEXPBAR(bar, slot) \ + (NFP_PCIE_BAR(0) + ((bar) * 8 + (slot)) * 4) + +#define NFP_PCIE_CPP_BAR_PCIETOCPPEXPBAR(bar, slot) \ + (((bar) * 8 + (slot)) * 4) + +/* + * Define to enable a bit more verbose debug output. + * Set to 1 to enable a bit more verbose debug output. + */ +struct nfp_pcie_user; +struct nfp6000_area_priv; + +/* + * struct nfp_bar - describes BAR configuration and usage + * @nfp: backlink to owner + * @barcfg: cached contents of BAR config CSR + * @base: the BAR's base CPP offset + * @mask: mask for the BAR aperture (read only) + * @bitsize: bitsize of BAR aperture (read only) + * @index: index of the BAR + * @lock: lock to specify if bar is in use + * @refcnt: number of current users + * @iomem: mapped IO memory + */ +#define NFP_BAR_MAX 7 +struct nfp_bar { + struct nfp_pcie_user *nfp; + uint32_t barcfg; + uint64_t base; /* CPP address base */ + uint64_t mask; /* Bit mask of the bar */ + uint32_t bitsize; /* Bit size of the bar */ + int index; + int lock; + + char *csr; + char *iomem; +}; + +#define BUSDEV_SZ 13 +struct nfp_pcie_user { + struct nfp_bar bar[NFP_BAR_MAX]; + + int device; + int lock; + char busdev[BUSDEV_SZ]; + int barsz; + char *cfg; +}; + +static uint32_t +nfp_bar_maptype(struct nfp_bar *bar) +{ + return NFP_PCIE_BAR_PCIE2CPP_MAPTYPE_OF(bar->barcfg); +} + +#define TARGET_WIDTH_32 4 +#define TARGET_WIDTH_64 8 + +static int +nfp_compute_bar(const struct nfp_bar *bar, uint32_t *bar_config, + uint64_t *bar_base, int tgt, int act, int tok, + uint64_t offset, size_t size, int width) +{ + uint32_t bitsize; + uint32_t newcfg; + uint64_t mask; + + if (tgt >= 16) + return -EINVAL; + + switch (width) { + case 8: + newcfg = + NFP_PCIE_BAR_PCIE2CPP_LENGTHSELECT + (NFP_PCIE_BAR_PCIE2CPP_LENGTHSELECT_64BIT); + break; + case 4: + newcfg = + NFP_PCIE_BAR_PCIE2CPP_LENGTHSELECT + (NFP_PCIE_BAR_PCIE2CPP_LENGTHSELECT_32BIT); + break; + case 0: + newcfg = + NFP_PCIE_BAR_PCIE2CPP_LENGTHSELECT + (NFP_PCIE_BAR_PCIE2CPP_LENGTHSELECT_0BYTE); + break; + default: + return -EINVAL; + } + + if (act != NFP_CPP_ACTION_RW && act != 0) { + /* Fixed CPP mapping with specific action */ + mask = ~(NFP_PCIE_P2C_FIXED_SIZE(bar) - 1); + + newcfg |= + NFP_PCIE_BAR_PCIE2CPP_MAPTYPE + (NFP_PCIE_BAR_PCIE2CPP_MAPTYPE_FIXED); + newcfg |= NFP_PCIE_BAR_PCIE2CPP_TARGET_BASEADDRESS(tgt); + newcfg |= NFP_PCIE_BAR_PCIE2CPP_ACTION_BASEADDRESS(act); + newcfg |= NFP_PCIE_BAR_PCIE2CPP_TOKEN_BASEADDRESS(tok); + + if ((offset & mask) != ((offset + size - 1) & mask)) { + printf("BAR%d: Won't use for Fixed mapping\n", + bar->index); + printf("\t<%#llx,%#llx>, action=%d\n", + (unsigned long long)offset, + (unsigned long long)(offset + size), act); + printf("\tBAR too small (0x%llx).\n", + (unsigned long long)mask); + return -EINVAL; + } + offset &= mask; + +#ifdef DEBUG + printf("BAR%d: Created Fixed mapping\n", bar->index); + printf("\t%d:%d:%d:0x%#llx-0x%#llx>\n", tgt, act, tok, + (unsigned long long)offset, + (unsigned long long)(offset + mask)); +#endif + + bitsize = 40 - 16; + } else { + mask = ~(NFP_PCIE_P2C_BULK_SIZE(bar) - 1); + + /* Bulk mapping */ + newcfg |= + NFP_PCIE_BAR_PCIE2CPP_MAPTYPE + (NFP_PCIE_BAR_PCIE2CPP_MAPTYPE_BULK); + + newcfg |= NFP_PCIE_BAR_PCIE2CPP_TARGET_BASEADDRESS(tgt); + newcfg |= NFP_PCIE_BAR_PCIE2CPP_TOKEN_BASEADDRESS(tok); + + if ((offset & mask) != ((offset + size - 1) & mask)) { + printf("BAR%d: Won't use for bulk mapping\n", + bar->index); + printf("\t<%#llx,%#llx>\n", (unsigned long long)offset, + (unsigned long long)(offset + size)); + printf("\ttarget=%d, token=%d\n", tgt, tok); + printf("\tBAR too small (%#llx) - (%#llx != %#llx).\n", + (unsigned long long)mask, + (unsigned long long)(offset & mask), + (unsigned long long)(offset + size - 1) & mask); + + return -EINVAL; + } + + offset &= mask; + +#ifdef DEBUG + printf("BAR%d: Created bulk mapping %d:x:%d:%#llx-%#llx\n", + bar->index, tgt, tok, (unsigned long long)offset, + (unsigned long long)(offset + ~mask)); +#endif + + bitsize = 40 - 21; + } + + if (bar->bitsize < bitsize) { + printf("BAR%d: Too small for %d:%d:%d\n", bar->index, tgt, tok, + act); + return -EINVAL; + } + + newcfg |= offset >> bitsize; + + if (bar_base) + *bar_base = offset; + + if (bar_config) + *bar_config = newcfg; + + return 0; +} + +static int +nfp_bar_write(struct nfp_pcie_user *nfp, struct nfp_bar *bar, + uint32_t newcfg) +{ + int base, slot; + + base = bar->index >> 3; + slot = bar->index & 7; + + if (!nfp->cfg) + return (-ENOMEM); + + bar->csr = nfp->cfg + + NFP_PCIE_CFG_BAR_PCIETOCPPEXPBAR(base, slot); + + *(uint32_t *)(bar->csr) = newcfg; + + bar->barcfg = newcfg; +#ifdef DEBUG + printf("BAR%d: updated to 0x%08x\n", bar->index, newcfg); +#endif + + return 0; +} + +static int +nfp_reconfigure_bar(struct nfp_pcie_user *nfp, struct nfp_bar *bar, int tgt, + int act, int tok, uint64_t offset, size_t size, int width) +{ + uint64_t newbase; + uint32_t newcfg; + int err; + + err = nfp_compute_bar(bar, &newcfg, &newbase, tgt, act, tok, offset, + size, width); + if (err) + return err; + + bar->base = newbase; + + return nfp_bar_write(nfp, bar, newcfg); +} + +/* + * Map all PCI bars. We assume that the BAR with the PCIe config block is + * already mapped. + * + * BAR0.0: Reserved for General Mapping (for MSI-X access to PCIe SRAM) + */ +static int +nfp_enable_bars(struct nfp_pcie_user *nfp) +{ + struct nfp_bar *bar; + int x; + + for (x = ARRAY_SIZE(nfp->bar); x > 0; x--) { + bar = &nfp->bar[x - 1]; + bar->barcfg = 0; + bar->nfp = nfp; + bar->index = x; + bar->mask = (1 << (nfp->barsz - 3)) - 1; + bar->bitsize = nfp->barsz - 3; + bar->base = 0; + bar->iomem = NULL; + bar->lock = 0; + bar->csr = nfp->cfg + + NFP_PCIE_CFG_BAR_PCIETOCPPEXPBAR(bar->index >> 3, + bar->index & 7); + + bar->iomem = nfp->cfg + (bar->index << bar->bitsize); + } + return 0; +} + +static struct nfp_bar * +nfp_alloc_bar(struct nfp_pcie_user *nfp) +{ + struct nfp_bar *bar; + int x; + + for (x = ARRAY_SIZE(nfp->bar); x > 0; x--) { + bar = &nfp->bar[x - 1]; + if (!bar->lock) { + bar->lock = 1; + return bar; + } + } + return NULL; +} + +static void +nfp_disable_bars(struct nfp_pcie_user *nfp) +{ + struct nfp_bar *bar; + int x; + + for (x = ARRAY_SIZE(nfp->bar); x > 0; x--) { + bar = &nfp->bar[x - 1]; + if (bar->iomem) { + bar->iomem = NULL; + bar->lock = 0; + } + } +} + +/* + * Generic CPP bus access interface. + */ + +struct nfp6000_area_priv { + struct nfp_bar *bar; + uint32_t bar_offset; + + uint32_t target; + uint32_t action; + uint32_t token; + uint64_t offset; + struct { + int read; + int write; + int bar; + } width; + size_t size; + char *iomem; +}; + +static int +nfp6000_area_init(struct nfp_cpp_area *area, uint32_t dest, + unsigned long long address, unsigned long size) +{ + struct nfp_pcie_user *nfp = nfp_cpp_priv(nfp_cpp_area_cpp(area)); + struct nfp6000_area_priv *priv = nfp_cpp_area_priv(area); + uint32_t target = NFP_CPP_ID_TARGET_of(dest); + uint32_t action = NFP_CPP_ID_ACTION_of(dest); + uint32_t token = NFP_CPP_ID_TOKEN_of(dest); + int pp, ret = 0; + + pp = nfp6000_target_pushpull(NFP_CPP_ID(target, action, token), + address); + if (pp < 0) + return pp; + + priv->width.read = PUSH_WIDTH(pp); + priv->width.write = PULL_WIDTH(pp); + + if (priv->width.read > 0 && + priv->width.write > 0 && priv->width.read != priv->width.write) + return -EINVAL; + + if (priv->width.read > 0) + priv->width.bar = priv->width.read; + else + priv->width.bar = priv->width.write; + + priv->bar = nfp_alloc_bar(nfp); + if (priv->bar == NULL) + return -ENOMEM; + + priv->target = target; + priv->action = action; + priv->token = token; + priv->offset = address; + priv->size = size; + + ret = nfp_reconfigure_bar(nfp, priv->bar, priv->target, priv->action, + priv->token, priv->offset, priv->size, + priv->width.bar); + + return ret; +} + +static int +nfp6000_area_acquire(struct nfp_cpp_area *area) +{ + struct nfp6000_area_priv *priv = nfp_cpp_area_priv(area); + + /* Calculate offset into BAR. */ + if (nfp_bar_maptype(priv->bar) == + NFP_PCIE_BAR_PCIE2CPP_MAPTYPE_GENERAL) { + priv->bar_offset = priv->offset & + (NFP_PCIE_P2C_GENERAL_SIZE(priv->bar) - 1); + priv->bar_offset += + NFP_PCIE_P2C_GENERAL_TARGET_OFFSET(priv->bar, + priv->target); + priv->bar_offset += + NFP_PCIE_P2C_GENERAL_TOKEN_OFFSET(priv->bar, priv->token); + } else { + priv->bar_offset = priv->offset & priv->bar->mask; + } + + /* Must have been too big. Sub-allocate. */ + if (!priv->bar->iomem) + return (-ENOMEM); + + priv->iomem = priv->bar->iomem + priv->bar_offset; + + return 0; +} + +static void * +nfp6000_area_mapped(struct nfp_cpp_area *area) +{ + struct nfp6000_area_priv *area_priv = nfp_cpp_area_priv(area); + + if (!area_priv->iomem) + return NULL; + + return area_priv->iomem; +} + +static void +nfp6000_area_release(struct nfp_cpp_area *area) +{ + struct nfp6000_area_priv *priv = nfp_cpp_area_priv(area); + priv->bar->lock = 0; + priv->bar = NULL; + priv->iomem = NULL; +} + +static void * +nfp6000_area_iomem(struct nfp_cpp_area *area) +{ + struct nfp6000_area_priv *priv = nfp_cpp_area_priv(area); + return priv->iomem; +} + +static int +nfp6000_area_read(struct nfp_cpp_area *area, void *kernel_vaddr, + unsigned long offset, unsigned int length) +{ + uint64_t *wrptr64 = kernel_vaddr; + const volatile uint64_t *rdptr64; + struct nfp6000_area_priv *priv; + uint32_t *wrptr32 = kernel_vaddr; + const volatile uint32_t *rdptr32; + int width; + unsigned int n; + bool is_64; + + priv = nfp_cpp_area_priv(area); + rdptr64 = (uint64_t *)(priv->iomem + offset); + rdptr32 = (uint32_t *)(priv->iomem + offset); + + if (offset + length > priv->size) + return -EFAULT; + + width = priv->width.read; + + if (width <= 0) + return -EINVAL; + + /* Unaligned? Translate to an explicit access */ + if ((priv->offset + offset) & (width - 1)) { + printf("aread_read unaligned!!!\n"); + return -EINVAL; + } + + is_64 = width == TARGET_WIDTH_64; + + /* MU reads via a PCIe2CPP BAR supports 32bit (and other) lengths */ + if (priv->target == (NFP_CPP_TARGET_ID_MASK & NFP_CPP_TARGET_MU) && + priv->action == NFP_CPP_ACTION_RW) { + is_64 = false; + } + + if (is_64) { + if (offset % sizeof(uint64_t) != 0 || + length % sizeof(uint64_t) != 0) + return -EINVAL; + } else { + if (offset % sizeof(uint32_t) != 0 || + length % sizeof(uint32_t) != 0) + return -EINVAL; + } + + if (!priv->bar) + return -EFAULT; + + if (is_64) + for (n = 0; n < length; n += sizeof(uint64_t)) { + *wrptr64 = *rdptr64; + wrptr64++; + rdptr64++; + } + else + for (n = 0; n < length; n += sizeof(uint32_t)) { + *wrptr32 = *rdptr32; + wrptr32++; + rdptr32++; + } + + return n; +} + +static int +nfp6000_area_write(struct nfp_cpp_area *area, const void *kernel_vaddr, + unsigned long offset, unsigned int length) +{ + const uint64_t *rdptr64 = kernel_vaddr; + uint64_t *wrptr64; + const uint32_t *rdptr32 = kernel_vaddr; + struct nfp6000_area_priv *priv; + uint32_t *wrptr32; + int width; + unsigned int n; + bool is_64; + + priv = nfp_cpp_area_priv(area); + wrptr64 = (uint64_t *)(priv->iomem + offset); + wrptr32 = (uint32_t *)(priv->iomem + offset); + + if (offset + length > priv->size) + return -EFAULT; + + width = priv->width.write; + + if (width <= 0) + return -EINVAL; + + /* Unaligned? Translate to an explicit access */ + if ((priv->offset + offset) & (width - 1)) + return -EINVAL; + + is_64 = width == TARGET_WIDTH_64; + + /* MU writes via a PCIe2CPP BAR supports 32bit (and other) lengths */ + if (priv->target == (NFP_CPP_TARGET_ID_MASK & NFP_CPP_TARGET_MU) && + priv->action == NFP_CPP_ACTION_RW) + is_64 = false; + + if (is_64) { + if (offset % sizeof(uint64_t) != 0 || + length % sizeof(uint64_t) != 0) + return -EINVAL; + } else { + if (offset % sizeof(uint32_t) != 0 || + length % sizeof(uint32_t) != 0) + return -EINVAL; + } + + if (!priv->bar) + return -EFAULT; + + if (is_64) + for (n = 0; n < length; n += sizeof(uint64_t)) { + *wrptr64 = *rdptr64; + wrptr64++; + rdptr64++; + } + else + for (n = 0; n < length; n += sizeof(uint32_t)) { + *wrptr32 = *rdptr32; + wrptr32++; + rdptr32++; + } + + return n; +} + +#define PCI_DEVICES "/sys/bus/pci/devices" + +static int +nfp_acquire_process_lock(struct nfp_pcie_user *desc) +{ + int rc; + struct flock lock; + char lockname[30]; + + memset(&lock, 0, sizeof(lock)); + + snprintf(lockname, sizeof(lockname), "/var/lock/nfp_%s", desc->busdev); + desc->lock = open(lockname, O_RDWR | O_CREAT, 0666); + if (desc->lock < 0) + return desc->lock; + + lock.l_type = F_WRLCK; + lock.l_whence = SEEK_SET; + rc = -1; + while (rc != 0) { + rc = fcntl(desc->lock, F_SETLKW, &lock); + if (rc < 0) { + if (errno != EAGAIN && errno != EACCES) { + close(desc->lock); + return rc; + } + } + } + + return 0; +} + +static int +nfp6000_set_model(struct rte_pci_device *dev, struct nfp_cpp *cpp) +{ + uint32_t model; + + if (rte_pci_read_config(dev, &model, 4, 0x2e) < 0) { + printf("nfp set model failed\n"); + return -1; + } + + model = model << 16; + nfp_cpp_model_set(cpp, model); + + return 0; +} + +static int +nfp6000_set_interface(struct rte_pci_device *dev, struct nfp_cpp *cpp) +{ + uint16_t interface; + + if (rte_pci_read_config(dev, &interface, 2, 0x154) < 0) { + printf("nfp set interface failed\n"); + return -1; + } + + nfp_cpp_interface_set(cpp, interface); + + return 0; +} + +#define PCI_CFG_SPACE_SIZE 256 +#define PCI_CFG_SPACE_EXP_SIZE 4096 +#define PCI_EXT_CAP_ID(header) (int)(header & 0x0000ffff) +#define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc) +#define PCI_EXT_CAP_ID_DSN 0x03 +static int +nfp_pci_find_next_ext_capability(struct rte_pci_device *dev, int cap) +{ + uint32_t header; + int ttl; + int pos = PCI_CFG_SPACE_SIZE; + + /* minimum 8 bytes per capability */ + ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; + + if (rte_pci_read_config(dev, &header, 4, pos) < 0) { + printf("nfp error reading extended capabilities\n"); + return -1; + } + + /* + * If we have no capabilities, this is indicated by cap ID, + * cap version and next pointer all being 0. + */ + if (header == 0) + return 0; + + while (ttl-- > 0) { + if (PCI_EXT_CAP_ID(header) == cap) + return pos; + + pos = PCI_EXT_CAP_NEXT(header); + if (pos < PCI_CFG_SPACE_SIZE) + break; + + if (rte_pci_read_config(dev, &header, 4, pos) < 0) { + printf("nfp error reading extended capabilities\n"); + return -1; + } + } + + return 0; +} + +static int +nfp6000_set_serial(struct rte_pci_device *dev, struct nfp_cpp *cpp) +{ + uint16_t tmp; + uint8_t serial[6]; + int serial_len = 6; + int pos; + + pos = nfp_pci_find_next_ext_capability(dev, PCI_EXT_CAP_ID_DSN); + if (pos <= 0) { + printf("PCI_EXT_CAP_ID_DSN not found. nfp set serial failed\n"); + return -1; + } else { + pos += 6; + } + + if (rte_pci_read_config(dev, &tmp, 2, pos) < 0) { + printf("nfp set serial failed\n"); + return -1; + } + + serial[4] = (uint8_t)((tmp >> 8) & 0xff); + serial[5] = (uint8_t)(tmp & 0xff); + + pos += 2; + if (rte_pci_read_config(dev, &tmp, 2, pos) < 0) { + printf("nfp set serial failed\n"); + return -1; + } + + serial[2] = (uint8_t)((tmp >> 8) & 0xff); + serial[3] = (uint8_t)(tmp & 0xff); + + pos += 2; + if (rte_pci_read_config(dev, &tmp, 2, pos) < 0) { + printf("nfp set serial failed\n"); + return -1; + } + + serial[0] = (uint8_t)((tmp >> 8) & 0xff); + serial[1] = (uint8_t)(tmp & 0xff); + + nfp_cpp_serial_set(cpp, serial, serial_len); + + return 0; +} + +static int +nfp6000_set_barsz(struct rte_pci_device *dev, struct nfp_pcie_user *desc) +{ + unsigned long tmp; + int i = 0; + + tmp = dev->mem_resource[0].len; + + while (tmp >>= 1) + i++; + + desc->barsz = i; + return 0; +} + +static int +nfp6000_init(struct nfp_cpp *cpp, struct rte_pci_device *dev) +{ + int ret = 0; + uint32_t model; + struct nfp_pcie_user *desc; + + desc = malloc(sizeof(*desc)); + if (!desc) + return -1; + + + memset(desc->busdev, 0, BUSDEV_SZ); + strlcpy(desc->busdev, dev->device.name, sizeof(desc->busdev)); + + if (cpp->driver_lock_needed) { + ret = nfp_acquire_process_lock(desc); + if (ret) + return -1; + } + + if (nfp6000_set_model(dev, cpp) < 0) + return -1; + if (nfp6000_set_interface(dev, cpp) < 0) + return -1; + if (nfp6000_set_serial(dev, cpp) < 0) + return -1; + if (nfp6000_set_barsz(dev, desc) < 0) + return -1; + + desc->cfg = (char *)dev->mem_resource[0].addr; + + nfp_enable_bars(desc); + + nfp_cpp_priv_set(cpp, desc); + + model = __nfp_cpp_model_autodetect(cpp); + nfp_cpp_model_set(cpp, model); + + return ret; +} + +static void +nfp6000_free(struct nfp_cpp *cpp) +{ + struct nfp_pcie_user *desc = nfp_cpp_priv(cpp); + + nfp_disable_bars(desc); + if (cpp->driver_lock_needed) + close(desc->lock); + close(desc->device); + free(desc); +} + +static const struct nfp_cpp_operations nfp6000_pcie_ops = { + .init = nfp6000_init, + .free = nfp6000_free, + + .area_priv_size = sizeof(struct nfp6000_area_priv), + .area_init = nfp6000_area_init, + .area_acquire = nfp6000_area_acquire, + .area_release = nfp6000_area_release, + .area_mapped = nfp6000_area_mapped, + .area_read = nfp6000_area_read, + .area_write = nfp6000_area_write, + .area_iomem = nfp6000_area_iomem, +}; + +const struct +nfp_cpp_operations *nfp_cpp_transport_operations(void) +{ + return &nfp6000_pcie_ops; +} diff --git a/drivers/net/nfp/nfpcore/nfp_cppcore.c b/drivers/net/nfp/nfpcore/nfp_cppcore.c new file mode 100644 index 00000000..75d3c974 --- /dev/null +++ b/drivers/net/nfp/nfpcore/nfp_cppcore.c @@ -0,0 +1,858 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2018 Netronome Systems, Inc. + * All rights reserved. + */ + +#include <assert.h> +#include <stdint.h> +#include <stdio.h> +#include <string.h> +#include <stdlib.h> +#include <errno.h> +#include <sys/types.h> + +#include <rte_byteorder.h> +#include <rte_ethdev_pci.h> + +#include "nfp_cpp.h" +#include "nfp_target.h" +#include "nfp6000/nfp6000.h" +#include "nfp6000/nfp_xpb.h" +#include "nfp_nffw.h" + +#define NFP_PL_DEVICE_ID 0x00000004 +#define NFP_PL_DEVICE_ID_MASK 0xff + +#define NFP6000_ARM_GCSR_SOFTMODEL0 0x00400144 + +void +nfp_cpp_priv_set(struct nfp_cpp *cpp, void *priv) +{ + cpp->priv = priv; +} + +void * +nfp_cpp_priv(struct nfp_cpp *cpp) +{ + return cpp->priv; +} + +void +nfp_cpp_model_set(struct nfp_cpp *cpp, uint32_t model) +{ + cpp->model = model; +} + +uint32_t +nfp_cpp_model(struct nfp_cpp *cpp) +{ + if (!cpp) + return NFP_CPP_MODEL_INVALID; + + if (cpp->model == 0) + cpp->model = __nfp_cpp_model_autodetect(cpp); + + return cpp->model; +} + +void +nfp_cpp_interface_set(struct nfp_cpp *cpp, uint32_t interface) +{ + cpp->interface = interface; +} + +int +nfp_cpp_serial(struct nfp_cpp *cpp, const uint8_t **serial) +{ + *serial = cpp->serial; + return cpp->serial_len; +} + +int +nfp_cpp_serial_set(struct nfp_cpp *cpp, const uint8_t *serial, + size_t serial_len) +{ + if (cpp->serial_len) + free(cpp->serial); + + cpp->serial = malloc(serial_len); + if (!cpp->serial) + return -1; + + memcpy(cpp->serial, serial, serial_len); + cpp->serial_len = serial_len; + + return 0; +} + +uint16_t +nfp_cpp_interface(struct nfp_cpp *cpp) +{ + if (!cpp) + return NFP_CPP_INTERFACE(NFP_CPP_INTERFACE_TYPE_INVALID, 0, 0); + + return cpp->interface; +} + +void * +nfp_cpp_area_priv(struct nfp_cpp_area *cpp_area) +{ + return &cpp_area[1]; +} + +struct nfp_cpp * +nfp_cpp_area_cpp(struct nfp_cpp_area *cpp_area) +{ + return cpp_area->cpp; +} + +const char * +nfp_cpp_area_name(struct nfp_cpp_area *cpp_area) +{ + return cpp_area->name; +} + +/* + * nfp_cpp_area_alloc - allocate a new CPP area + * @cpp: CPP handle + * @dest: CPP id + * @address: start address on CPP target + * @size: size of area in bytes + * + * Allocate and initialize a CPP area structure. The area must later + * be locked down with an 'acquire' before it can be safely accessed. + * + * NOTE: @address and @size must be 32-bit aligned values. + */ +struct nfp_cpp_area * +nfp_cpp_area_alloc_with_name(struct nfp_cpp *cpp, uint32_t dest, + const char *name, unsigned long long address, + unsigned long size) +{ + struct nfp_cpp_area *area; + uint64_t tmp64 = (uint64_t)address; + int tmp, err; + + if (!cpp) + return NULL; + + /* CPP bus uses only a 40-bit address */ + if ((address + size) > (1ULL << 40)) + return NFP_ERRPTR(EFAULT); + + /* Remap from cpp_island to cpp_target */ + err = nfp_target_cpp(dest, tmp64, &dest, &tmp64, cpp->imb_cat_table); + if (err < 0) + return NULL; + + address = (unsigned long long)tmp64; + + if (!name) + name = ""; + + area = calloc(1, sizeof(*area) + cpp->op->area_priv_size + + strlen(name) + 1); + if (!area) + return NULL; + + area->cpp = cpp; + area->name = ((char *)area) + sizeof(*area) + cpp->op->area_priv_size; + memcpy(area->name, name, strlen(name) + 1); + + /* + * Preserve errno around the call to area_init, since most + * implementations will blindly call nfp_target_action_width()for both + * read or write modes, and that will set errno to EINVAL. + */ + tmp = errno; + + err = cpp->op->area_init(area, dest, address, size); + if (err < 0) { + free(area); + return NULL; + } + + /* Restore errno */ + errno = tmp; + + area->offset = address; + area->size = size; + + return area; +} + +struct nfp_cpp_area * +nfp_cpp_area_alloc(struct nfp_cpp *cpp, uint32_t dest, + unsigned long long address, unsigned long size) +{ + return nfp_cpp_area_alloc_with_name(cpp, dest, NULL, address, size); +} + +/* + * nfp_cpp_area_alloc_acquire - allocate a new CPP area and lock it down + * + * @cpp: CPP handle + * @dest: CPP id + * @address: start address on CPP target + * @size: size of area + * + * Allocate and initilizae a CPP area structure, and lock it down so + * that it can be accessed directly. + * + * NOTE: @address and @size must be 32-bit aligned values. + * + * NOTE: The area must also be 'released' when the structure is freed. + */ +struct nfp_cpp_area * +nfp_cpp_area_alloc_acquire(struct nfp_cpp *cpp, uint32_t destination, + unsigned long long address, unsigned long size) +{ + struct nfp_cpp_area *area; + + area = nfp_cpp_area_alloc(cpp, destination, address, size); + if (!area) + return NULL; + + if (nfp_cpp_area_acquire(area)) { + nfp_cpp_area_free(area); + return NULL; + } + + return area; +} + +/* + * nfp_cpp_area_free - free up the CPP area + * area: CPP area handle + * + * Frees up memory resources held by the CPP area. + */ +void +nfp_cpp_area_free(struct nfp_cpp_area *area) +{ + if (area->cpp->op->area_cleanup) + area->cpp->op->area_cleanup(area); + free(area); +} + +/* + * nfp_cpp_area_release_free - release CPP area and free it + * area: CPP area handle + * + * Releases CPP area and frees up memory resources held by the it. + */ +void +nfp_cpp_area_release_free(struct nfp_cpp_area *area) +{ + nfp_cpp_area_release(area); + nfp_cpp_area_free(area); +} + +/* + * nfp_cpp_area_acquire - lock down a CPP area for access + * @area: CPP area handle + * + * Locks down the CPP area for a potential long term activity. Area + * must always be locked down before being accessed. + */ +int +nfp_cpp_area_acquire(struct nfp_cpp_area *area) +{ + if (area->cpp->op->area_acquire) { + int err = area->cpp->op->area_acquire(area); + + if (err < 0) + return -1; + } + + return 0; +} + +/* + * nfp_cpp_area_release - release a locked down CPP area + * @area: CPP area handle + * + * Releases a previously locked down CPP area. + */ +void +nfp_cpp_area_release(struct nfp_cpp_area *area) +{ + if (area->cpp->op->area_release) + area->cpp->op->area_release(area); +} + +/* + * nfp_cpp_area_iomem() - get IOMEM region for CPP area + * + * @area: CPP area handle + * + * Returns an iomem pointer for use with readl()/writel() style operations. + * + * NOTE: Area must have been locked down with an 'acquire'. + * + * Return: pointer to the area, or NULL + */ +void * +nfp_cpp_area_iomem(struct nfp_cpp_area *area) +{ + void *iomem = NULL; + + if (area->cpp->op->area_iomem) + iomem = area->cpp->op->area_iomem(area); + + return iomem; +} + +/* + * nfp_cpp_area_read - read data from CPP area + * + * @area: CPP area handle + * @offset: offset into CPP area + * @kernel_vaddr: kernel address to put data into + * @length: number of bytes to read + * + * Read data from indicated CPP region. + * + * NOTE: @offset and @length must be 32-bit aligned values. + * + * NOTE: Area must have been locked down with an 'acquire'. + */ +int +nfp_cpp_area_read(struct nfp_cpp_area *area, unsigned long offset, + void *kernel_vaddr, size_t length) +{ + if ((offset + length) > area->size) + return NFP_ERRNO(EFAULT); + + return area->cpp->op->area_read(area, kernel_vaddr, offset, length); +} + +/* + * nfp_cpp_area_write - write data to CPP area + * + * @area: CPP area handle + * @offset: offset into CPP area + * @kernel_vaddr: kernel address to read data from + * @length: number of bytes to write + * + * Write data to indicated CPP region. + * + * NOTE: @offset and @length must be 32-bit aligned values. + * + * NOTE: Area must have been locked down with an 'acquire'. + */ +int +nfp_cpp_area_write(struct nfp_cpp_area *area, unsigned long offset, + const void *kernel_vaddr, size_t length) +{ + if ((offset + length) > area->size) + return NFP_ERRNO(EFAULT); + + return area->cpp->op->area_write(area, kernel_vaddr, offset, length); +} + +void * +nfp_cpp_area_mapped(struct nfp_cpp_area *area) +{ + if (area->cpp->op->area_mapped) + return area->cpp->op->area_mapped(area); + return NULL; +} + +/* + * nfp_cpp_area_check_range - check if address range fits in CPP area + * + * @area: CPP area handle + * @offset: offset into CPP area + * @length: size of address range in bytes + * + * Check if address range fits within CPP area. Return 0 if area fits + * or -1 on error. + */ +int +nfp_cpp_area_check_range(struct nfp_cpp_area *area, unsigned long long offset, + unsigned long length) +{ + if (((offset + length) > area->size)) + return NFP_ERRNO(EFAULT); + + return 0; +} + +/* + * Return the correct CPP address, and fixup xpb_addr as needed, + * based upon NFP model. + */ +static uint32_t +nfp_xpb_to_cpp(struct nfp_cpp *cpp, uint32_t *xpb_addr) +{ + uint32_t xpb; + int island; + + if (!NFP_CPP_MODEL_IS_6000(cpp->model)) + return 0; + + xpb = NFP_CPP_ID(14, NFP_CPP_ACTION_RW, 0); + + /* + * Ensure that non-local XPB accesses go out through the + * global XPBM bus. + */ + island = ((*xpb_addr) >> 24) & 0x3f; + + if (!island) + return xpb; + + if (island == 1) { + /* + * Accesses to the ARM Island overlay uses Island 0 + * Global Bit + */ + (*xpb_addr) &= ~0x7f000000; + if (*xpb_addr < 0x60000) + *xpb_addr |= (1 << 30); + else + /* And only non-ARM interfaces use island id = 1 */ + if (NFP_CPP_INTERFACE_TYPE_of(nfp_cpp_interface(cpp)) != + NFP_CPP_INTERFACE_TYPE_ARM) + *xpb_addr |= (1 << 24); + } else { + (*xpb_addr) |= (1 << 30); + } + + return xpb; +} + +int +nfp_cpp_area_readl(struct nfp_cpp_area *area, unsigned long offset, + uint32_t *value) +{ + int sz; + uint32_t tmp = 0; + + sz = nfp_cpp_area_read(area, offset, &tmp, sizeof(tmp)); + *value = rte_le_to_cpu_32(tmp); + + return (sz == sizeof(*value)) ? 0 : -1; +} + +int +nfp_cpp_area_writel(struct nfp_cpp_area *area, unsigned long offset, + uint32_t value) +{ + int sz; + + value = rte_cpu_to_le_32(value); + sz = nfp_cpp_area_write(area, offset, &value, sizeof(value)); + return (sz == sizeof(value)) ? 0 : -1; +} + +int +nfp_cpp_area_readq(struct nfp_cpp_area *area, unsigned long offset, + uint64_t *value) +{ + int sz; + uint64_t tmp = 0; + + sz = nfp_cpp_area_read(area, offset, &tmp, sizeof(tmp)); + *value = rte_le_to_cpu_64(tmp); + + return (sz == sizeof(*value)) ? 0 : -1; +} + +int +nfp_cpp_area_writeq(struct nfp_cpp_area *area, unsigned long offset, + uint64_t value) +{ + int sz; + + value = rte_cpu_to_le_64(value); + sz = nfp_cpp_area_write(area, offset, &value, sizeof(value)); + + return (sz == sizeof(value)) ? 0 : -1; +} + +int +nfp_cpp_readl(struct nfp_cpp *cpp, uint32_t cpp_id, unsigned long long address, + uint32_t *value) +{ + int sz; + uint32_t tmp; + + sz = nfp_cpp_read(cpp, cpp_id, address, &tmp, sizeof(tmp)); + *value = rte_le_to_cpu_32(tmp); + + return (sz == sizeof(*value)) ? 0 : -1; +} + +int +nfp_cpp_writel(struct nfp_cpp *cpp, uint32_t cpp_id, unsigned long long address, + uint32_t value) +{ + int sz; + + value = rte_cpu_to_le_32(value); + sz = nfp_cpp_write(cpp, cpp_id, address, &value, sizeof(value)); + + return (sz == sizeof(value)) ? 0 : -1; +} + +int +nfp_cpp_readq(struct nfp_cpp *cpp, uint32_t cpp_id, unsigned long long address, + uint64_t *value) +{ + int sz; + uint64_t tmp; + + sz = nfp_cpp_read(cpp, cpp_id, address, &tmp, sizeof(tmp)); + *value = rte_le_to_cpu_64(tmp); + + return (sz == sizeof(*value)) ? 0 : -1; +} + +int +nfp_cpp_writeq(struct nfp_cpp *cpp, uint32_t cpp_id, unsigned long long address, + uint64_t value) +{ + int sz; + + value = rte_cpu_to_le_64(value); + sz = nfp_cpp_write(cpp, cpp_id, address, &value, sizeof(value)); + + return (sz == sizeof(value)) ? 0 : -1; +} + +int +nfp_xpb_writel(struct nfp_cpp *cpp, uint32_t xpb_addr, uint32_t value) +{ + uint32_t cpp_dest; + + cpp_dest = nfp_xpb_to_cpp(cpp, &xpb_addr); + + return nfp_cpp_writel(cpp, cpp_dest, xpb_addr, value); +} + +int +nfp_xpb_readl(struct nfp_cpp *cpp, uint32_t xpb_addr, uint32_t *value) +{ + uint32_t cpp_dest; + + cpp_dest = nfp_xpb_to_cpp(cpp, &xpb_addr); + + return nfp_cpp_readl(cpp, cpp_dest, xpb_addr, value); +} + +static struct nfp_cpp * +nfp_cpp_alloc(struct rte_pci_device *dev, int driver_lock_needed) +{ + const struct nfp_cpp_operations *ops; + struct nfp_cpp *cpp; + int err; + + ops = nfp_cpp_transport_operations(); + + if (!ops || !ops->init) + return NFP_ERRPTR(EINVAL); + + cpp = calloc(1, sizeof(*cpp)); + if (!cpp) + return NULL; + + cpp->op = ops; + cpp->driver_lock_needed = driver_lock_needed; + + if (cpp->op->init) { + err = cpp->op->init(cpp, dev); + if (err < 0) { + free(cpp); + return NULL; + } + } + + if (NFP_CPP_MODEL_IS_6000(nfp_cpp_model(cpp))) { + uint32_t xpbaddr; + size_t tgt; + + for (tgt = 0; tgt < ARRAY_SIZE(cpp->imb_cat_table); tgt++) { + /* Hardcoded XPB IMB Base, island 0 */ + xpbaddr = 0x000a0000 + (tgt * 4); + err = nfp_xpb_readl(cpp, xpbaddr, + (uint32_t *)&cpp->imb_cat_table[tgt]); + if (err < 0) { + free(cpp); + return NULL; + } + } + } + + return cpp; +} + +/* + * nfp_cpp_free - free the CPP handle + * @cpp: CPP handle + */ +void +nfp_cpp_free(struct nfp_cpp *cpp) +{ + if (cpp->op && cpp->op->free) + cpp->op->free(cpp); + + if (cpp->serial_len) + free(cpp->serial); + + free(cpp); +} + +struct nfp_cpp * +nfp_cpp_from_device_name(struct rte_pci_device *dev, int driver_lock_needed) +{ + return nfp_cpp_alloc(dev, driver_lock_needed); +} + +/* + * Modify bits of a 32-bit value from the XPB bus + * + * @param cpp NFP CPP device handle + * @param xpb_tgt XPB target and address + * @param mask mask of bits to alter + * @param value value to modify + * + * @return 0 on success, or -1 on failure (and set errno accordingly). + */ +int +nfp_xpb_writelm(struct nfp_cpp *cpp, uint32_t xpb_tgt, uint32_t mask, + uint32_t value) +{ + int err; + uint32_t tmp; + + err = nfp_xpb_readl(cpp, xpb_tgt, &tmp); + if (err < 0) + return err; + + tmp &= ~mask; + tmp |= (mask & value); + return nfp_xpb_writel(cpp, xpb_tgt, tmp); +} + +/* + * Modify bits of a 32-bit value from the XPB bus + * + * @param cpp NFP CPP device handle + * @param xpb_tgt XPB target and address + * @param mask mask of bits to alter + * @param value value to monitor for + * @param timeout_us maximum number of us to wait (-1 for forever) + * + * @return >= 0 on success, or -1 on failure (and set errno accordingly). + */ +int +nfp_xpb_waitlm(struct nfp_cpp *cpp, uint32_t xpb_tgt, uint32_t mask, + uint32_t value, int timeout_us) +{ + uint32_t tmp; + int err; + + do { + err = nfp_xpb_readl(cpp, xpb_tgt, &tmp); + if (err < 0) + goto exit; + + if ((tmp & mask) == (value & mask)) { + if (timeout_us < 0) + timeout_us = 0; + break; + } + + if (timeout_us < 0) + continue; + + timeout_us -= 100; + usleep(100); + } while (timeout_us >= 0); + + if (timeout_us < 0) + err = NFP_ERRNO(ETIMEDOUT); + else + err = timeout_us; + +exit: + return err; +} + +/* + * nfp_cpp_read - read from CPP target + * @cpp: CPP handle + * @destination: CPP id + * @address: offset into CPP target + * @kernel_vaddr: kernel buffer for result + * @length: number of bytes to read + */ +int +nfp_cpp_read(struct nfp_cpp *cpp, uint32_t destination, + unsigned long long address, void *kernel_vaddr, size_t length) +{ + struct nfp_cpp_area *area; + int err; + + area = nfp_cpp_area_alloc_acquire(cpp, destination, address, length); + if (!area) { + printf("Area allocation/acquire failed\n"); + return -1; + } + + err = nfp_cpp_area_read(area, 0, kernel_vaddr, length); + + nfp_cpp_area_release_free(area); + return err; +} + +/* + * nfp_cpp_write - write to CPP target + * @cpp: CPP handle + * @destination: CPP id + * @address: offset into CPP target + * @kernel_vaddr: kernel buffer to read from + * @length: number of bytes to write + */ +int +nfp_cpp_write(struct nfp_cpp *cpp, uint32_t destination, + unsigned long long address, const void *kernel_vaddr, + size_t length) +{ + struct nfp_cpp_area *area; + int err; + + area = nfp_cpp_area_alloc_acquire(cpp, destination, address, length); + if (!area) + return -1; + + err = nfp_cpp_area_write(area, 0, kernel_vaddr, length); + + nfp_cpp_area_release_free(area); + return err; +} + +/* + * nfp_cpp_area_fill - fill a CPP area with a value + * @area: CPP area + * @offset: offset into CPP area + * @value: value to fill with + * @length: length of area to fill + */ +int +nfp_cpp_area_fill(struct nfp_cpp_area *area, unsigned long offset, + uint32_t value, size_t length) +{ + int err; + size_t i; + uint64_t value64; + + value = rte_cpu_to_le_32(value); + value64 = ((uint64_t)value << 32) | value; + + if ((offset + length) > area->size) + return NFP_ERRNO(EINVAL); + + if ((area->offset + offset) & 3) + return NFP_ERRNO(EINVAL); + + if (((area->offset + offset) & 7) == 4 && length >= 4) { + err = nfp_cpp_area_write(area, offset, &value, sizeof(value)); + if (err < 0) + return err; + if (err != sizeof(value)) + return NFP_ERRNO(ENOSPC); + offset += sizeof(value); + length -= sizeof(value); + } + + for (i = 0; (i + sizeof(value)) < length; i += sizeof(value64)) { + err = + nfp_cpp_area_write(area, offset + i, &value64, + sizeof(value64)); + if (err < 0) + return err; + if (err != sizeof(value64)) + return NFP_ERRNO(ENOSPC); + } + + if ((i + sizeof(value)) <= length) { + err = + nfp_cpp_area_write(area, offset + i, &value, sizeof(value)); + if (err < 0) + return err; + if (err != sizeof(value)) + return NFP_ERRNO(ENOSPC); + i += sizeof(value); + } + + return (int)i; +} + +/* + * NOTE: This code should not use nfp_xpb_* functions, + * as those are model-specific + */ +uint32_t +__nfp_cpp_model_autodetect(struct nfp_cpp *cpp) +{ + uint32_t arm_id = NFP_CPP_ID(NFP_CPP_TARGET_ARM, 0, 0); + uint32_t model = 0; + + nfp_cpp_readl(cpp, arm_id, NFP6000_ARM_GCSR_SOFTMODEL0, &model); + + if (NFP_CPP_MODEL_IS_6000(model)) { + uint32_t tmp; + + nfp_cpp_model_set(cpp, model); + + /* The PL's PluDeviceID revision code is authoratative */ + model &= ~0xff; + nfp_xpb_readl(cpp, NFP_XPB_DEVICE(1, 1, 16) + + NFP_PL_DEVICE_ID, &tmp); + model |= (NFP_PL_DEVICE_ID_MASK & tmp) - 0x10; + } + + return model; +} + +/* + * nfp_cpp_map_area() - Helper function to map an area + * @cpp: NFP CPP handler + * @domain: CPP domain + * @target: CPP target + * @addr: CPP address + * @size: Size of the area + * @area: Area handle (output) + * + * Map an area of IOMEM access. To undo the effect of this function call + * @nfp_cpp_area_release_free(*area). + * + * Return: Pointer to memory mapped area or ERR_PTR + */ +uint8_t * +nfp_cpp_map_area(struct nfp_cpp *cpp, int domain, int target, uint64_t addr, + unsigned long size, struct nfp_cpp_area **area) +{ + uint8_t *res; + uint32_t dest; + + dest = NFP_CPP_ISLAND_ID(target, NFP_CPP_ACTION_RW, 0, domain); + + *area = nfp_cpp_area_alloc_acquire(cpp, dest, addr, size); + if (!*area) + goto err_eio; + + res = nfp_cpp_area_iomem(*area); + if (!res) + goto err_release_free; + + return res; + +err_release_free: + nfp_cpp_area_release_free(*area); +err_eio: + return NULL; +} diff --git a/drivers/net/nfp/nfpcore/nfp_crc.c b/drivers/net/nfp/nfpcore/nfp_crc.c new file mode 100644 index 00000000..20431bf8 --- /dev/null +++ b/drivers/net/nfp/nfpcore/nfp_crc.c @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2018 Netronome Systems, Inc. + * All rights reserved. + */ + +#include <stdio.h> +#include <inttypes.h> + +#include "nfp_crc.h" + +static inline uint32_t +nfp_crc32_be_generic(uint32_t crc, unsigned char const *p, size_t len, + uint32_t polynomial) +{ + int i; + while (len--) { + crc ^= *p++ << 24; + for (i = 0; i < 8; i++) + crc = (crc << 1) ^ ((crc & 0x80000000) ? polynomial : + 0); + } + return crc; +} + +static inline uint32_t +nfp_crc32_be(uint32_t crc, unsigned char const *p, size_t len) +{ + return nfp_crc32_be_generic(crc, p, len, CRCPOLY_BE); +} + +static uint32_t +nfp_crc32_posix_end(uint32_t crc, size_t total_len) +{ + /* Extend with the length of the string. */ + while (total_len != 0) { + uint8_t c = total_len & 0xff; + + crc = nfp_crc32_be(crc, &c, 1); + total_len >>= 8; + } + + return ~crc; +} + +uint32_t +nfp_crc32_posix(const void *buff, size_t len) +{ + return nfp_crc32_posix_end(nfp_crc32_be(0, buff, len), len); +} diff --git a/drivers/net/nfp/nfpcore/nfp_crc.h b/drivers/net/nfp/nfpcore/nfp_crc.h new file mode 100644 index 00000000..f99c89fc --- /dev/null +++ b/drivers/net/nfp/nfpcore/nfp_crc.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2018 Netronome Systems, Inc. + * All rights reserved. + */ + +#ifndef __NFP_CRC_H__ +#define __NFP_CRC_H__ + +/* + * There are multiple 16-bit CRC polynomials in common use, but this is + * *the* standard CRC-32 polynomial, first popularized by Ethernet. + * x^32+x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x^1+x^0 + */ +#define CRCPOLY_LE 0xedb88320 +#define CRCPOLY_BE 0x04c11db7 + +uint32_t nfp_crc32_posix(const void *buff, size_t len); + +#endif diff --git a/drivers/net/nfp/nfpcore/nfp_hwinfo.c b/drivers/net/nfp/nfpcore/nfp_hwinfo.c new file mode 100644 index 00000000..c0516bf8 --- /dev/null +++ b/drivers/net/nfp/nfpcore/nfp_hwinfo.c @@ -0,0 +1,199 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2018 Netronome Systems, Inc. + * All rights reserved. + */ + +/* Parse the hwinfo table that the ARM firmware builds in the ARM scratch SRAM + * after chip reset. + * + * Examples of the fields: + * me.count = 40 + * me.mask = 0x7f_ffff_ffff + * + * me.count is the total number of MEs on the system. + * me.mask is the bitmask of MEs that are available for application usage. + * + * (ie, in this example, ME 39 has been reserved by boardconfig.) + */ + +#include <stdio.h> +#include <time.h> + +#include "nfp_cpp.h" +#include "nfp6000/nfp6000.h" +#include "nfp_resource.h" +#include "nfp_hwinfo.h" +#include "nfp_crc.h" + +static int +nfp_hwinfo_is_updating(struct nfp_hwinfo *hwinfo) +{ + return hwinfo->version & NFP_HWINFO_VERSION_UPDATING; +} + +static int +nfp_hwinfo_db_walk(struct nfp_hwinfo *hwinfo, uint32_t size) +{ + const char *key, *val, *end = hwinfo->data + size; + + for (key = hwinfo->data; *key && key < end; + key = val + strlen(val) + 1) { + val = key + strlen(key) + 1; + if (val >= end) { + printf("Bad HWINFO - overflowing key\n"); + return -EINVAL; + } + + if (val + strlen(val) + 1 > end) { + printf("Bad HWINFO - overflowing value\n"); + return -EINVAL; + } + } + return 0; +} + +static int +nfp_hwinfo_db_validate(struct nfp_hwinfo *db, uint32_t len) +{ + uint32_t size, new_crc, *crc; + + size = db->size; + if (size > len) { + printf("Unsupported hwinfo size %u > %u\n", size, len); + return -EINVAL; + } + + size -= sizeof(uint32_t); + new_crc = nfp_crc32_posix((char *)db, size); + crc = (uint32_t *)(db->start + size); + if (new_crc != *crc) { + printf("Corrupt hwinfo table (CRC mismatch)\n"); + printf("\tcalculated 0x%x, expected 0x%x\n", new_crc, *crc); + return -EINVAL; + } + + return nfp_hwinfo_db_walk(db, size); +} + +static struct nfp_hwinfo * +nfp_hwinfo_try_fetch(struct nfp_cpp *cpp, size_t *cpp_size) +{ + struct nfp_hwinfo *header; + void *res; + uint64_t cpp_addr; + uint32_t cpp_id; + int err; + uint8_t *db; + + res = nfp_resource_acquire(cpp, NFP_RESOURCE_NFP_HWINFO); + if (res) { + cpp_id = nfp_resource_cpp_id(res); + cpp_addr = nfp_resource_address(res); + *cpp_size = nfp_resource_size(res); + + nfp_resource_release(res); + + if (*cpp_size < HWINFO_SIZE_MIN) + return NULL; + } else { + return NULL; + } + + db = malloc(*cpp_size + 1); + if (!db) + return NULL; + + err = nfp_cpp_read(cpp, cpp_id, cpp_addr, db, *cpp_size); + if (err != (int)*cpp_size) + goto exit_free; + + header = (void *)db; + printf("NFP HWINFO header: %08x\n", *(uint32_t *)header); + if (nfp_hwinfo_is_updating(header)) + goto exit_free; + + if (header->version != NFP_HWINFO_VERSION_2) { + printf("Unknown HWInfo version: 0x%08x\n", + header->version); + goto exit_free; + } + + /* NULL-terminate for safety */ + db[*cpp_size] = '\0'; + + return (void *)db; +exit_free: + free(db); + return NULL; +} + +static struct nfp_hwinfo * +nfp_hwinfo_fetch(struct nfp_cpp *cpp, size_t *hwdb_size) +{ + struct timespec wait; + struct nfp_hwinfo *db; + int count; + + wait.tv_sec = 0; + wait.tv_nsec = 10000000; + count = 0; + + for (;;) { + db = nfp_hwinfo_try_fetch(cpp, hwdb_size); + if (db) + return db; + + nanosleep(&wait, NULL); + if (count++ > 200) { + printf("NFP access error\n"); + return NULL; + } + } +} + +struct nfp_hwinfo * +nfp_hwinfo_read(struct nfp_cpp *cpp) +{ + struct nfp_hwinfo *db; + size_t hwdb_size = 0; + int err; + + db = nfp_hwinfo_fetch(cpp, &hwdb_size); + if (!db) + return NULL; + + err = nfp_hwinfo_db_validate(db, hwdb_size); + if (err) { + free(db); + return NULL; + } + return db; +} + +/* + * nfp_hwinfo_lookup() - Find a value in the HWInfo table by name + * @hwinfo: NFP HWinfo table + * @lookup: HWInfo name to search for + * + * Return: Value of the HWInfo name, or NULL + */ +const char * +nfp_hwinfo_lookup(struct nfp_hwinfo *hwinfo, const char *lookup) +{ + const char *key, *val, *end; + + if (!hwinfo || !lookup) + return NULL; + + end = hwinfo->data + hwinfo->size - sizeof(uint32_t); + + for (key = hwinfo->data; *key && key < end; + key = val + strlen(val) + 1) { + val = key + strlen(key) + 1; + + if (strcmp(key, lookup) == 0) + return val; + } + + return NULL; +} diff --git a/drivers/net/nfp/nfpcore/nfp_hwinfo.h b/drivers/net/nfp/nfpcore/nfp_hwinfo.h new file mode 100644 index 00000000..ccc61632 --- /dev/null +++ b/drivers/net/nfp/nfpcore/nfp_hwinfo.h @@ -0,0 +1,85 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2018 Netronome Systems, Inc. + * All rights reserved. + */ + +#ifndef __NFP_HWINFO_H__ +#define __NFP_HWINFO_H__ + +#include <inttypes.h> + +#define HWINFO_SIZE_MIN 0x100 + +/* + * The Hardware Info Table defines the properties of the system. + * + * HWInfo v1 Table (fixed size) + * + * 0x0000: uint32_t version Hardware Info Table version (1.0) + * 0x0004: uint32_t size Total size of the table, including the + * CRC32 (IEEE 802.3) + * 0x0008: uint32_t jumptab Offset of key/value table + * 0x000c: uint32_t keys Total number of keys in the key/value + * table + * NNNNNN: Key/value jump table and string data + * (size - 4): uint32_t crc32 CRC32 (same as IEEE 802.3, POSIX csum, etc) + * CRC32("",0) = ~0, CRC32("a",1) = 0x48C279FE + * + * HWInfo v2 Table (variable size) + * + * 0x0000: uint32_t version Hardware Info Table version (2.0) + * 0x0004: uint32_t size Current size of the data area, excluding + * CRC32 + * 0x0008: uint32_t limit Maximum size of the table + * 0x000c: uint32_t reserved Unused, set to zero + * NNNNNN: Key/value data + * (size - 4): uint32_t crc32 CRC32 (same as IEEE 802.3, POSIX csum, etc) + * CRC32("",0) = ~0, CRC32("a",1) = 0x48C279FE + * + * If the HWInfo table is in the process of being updated, the low bit of + * version will be set. + * + * HWInfo v1 Key/Value Table + * ------------------------- + * + * The key/value table is a set of offsets to ASCIIZ strings which have + * been strcmp(3) sorted (yes, please use bsearch(3) on the table). + * + * All keys are guaranteed to be unique. + * + * N+0: uint32_t key_1 Offset to the first key + * N+4: uint32_t val_1 Offset to the first value + * N+8: uint32_t key_2 Offset to the second key + * N+c: uint32_t val_2 Offset to the second value + * ... + * + * HWInfo v2 Key/Value Table + * ------------------------- + * + * Packed UTF8Z strings, ie 'key1\000value1\000key2\000value2\000' + * + * Unsorted. + */ + +#define NFP_HWINFO_VERSION_1 ('H' << 24 | 'I' << 16 | 1 << 8 | 0 << 1 | 0) +#define NFP_HWINFO_VERSION_2 ('H' << 24 | 'I' << 16 | 2 << 8 | 0 << 1 | 0) +#define NFP_HWINFO_VERSION_UPDATING BIT(0) + +struct nfp_hwinfo { + uint8_t start[0]; + + uint32_t version; + uint32_t size; + + /* v2 specific fields */ + uint32_t limit; + uint32_t resv; + + char data[]; +}; + +struct nfp_hwinfo *nfp_hwinfo_read(struct nfp_cpp *cpp); + +const char *nfp_hwinfo_lookup(struct nfp_hwinfo *hwinfo, const char *lookup); + +#endif diff --git a/drivers/net/nfp/nfpcore/nfp_mip.c b/drivers/net/nfp/nfpcore/nfp_mip.c new file mode 100644 index 00000000..c86966df --- /dev/null +++ b/drivers/net/nfp/nfpcore/nfp_mip.c @@ -0,0 +1,154 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2018 Netronome Systems, Inc. + * All rights reserved. + */ + +#include <stdio.h> +#include <rte_byteorder.h> + +#include "nfp_cpp.h" +#include "nfp_mip.h" +#include "nfp_nffw.h" + +#define NFP_MIP_SIGNATURE rte_cpu_to_le_32(0x0050494d) /* "MIP\0" */ +#define NFP_MIP_VERSION rte_cpu_to_le_32(1) +#define NFP_MIP_MAX_OFFSET (256 * 1024) + +struct nfp_mip { + uint32_t signature; + uint32_t mip_version; + uint32_t mip_size; + uint32_t first_entry; + + uint32_t version; + uint32_t buildnum; + uint32_t buildtime; + uint32_t loadtime; + + uint32_t symtab_addr; + uint32_t symtab_size; + uint32_t strtab_addr; + uint32_t strtab_size; + + char name[16]; + char toolchain[32]; +}; + +/* Read memory and check if it could be a valid MIP */ +static int +nfp_mip_try_read(struct nfp_cpp *cpp, uint32_t cpp_id, uint64_t addr, + struct nfp_mip *mip) +{ + int ret; + + ret = nfp_cpp_read(cpp, cpp_id, addr, mip, sizeof(*mip)); + if (ret != sizeof(*mip)) { + printf("Failed to read MIP data (%d, %zu)\n", + ret, sizeof(*mip)); + return -EIO; + } + if (mip->signature != NFP_MIP_SIGNATURE) { + printf("Incorrect MIP signature (0x%08x)\n", + rte_le_to_cpu_32(mip->signature)); + return -EINVAL; + } + if (mip->mip_version != NFP_MIP_VERSION) { + printf("Unsupported MIP version (%d)\n", + rte_le_to_cpu_32(mip->mip_version)); + return -EINVAL; + } + + return 0; +} + +/* Try to locate MIP using the resource table */ +static int +nfp_mip_read_resource(struct nfp_cpp *cpp, struct nfp_mip *mip) +{ + struct nfp_nffw_info *nffw_info; + uint32_t cpp_id; + uint64_t addr; + int err; + + nffw_info = nfp_nffw_info_open(cpp); + if (!nffw_info) + return -ENODEV; + + err = nfp_nffw_info_mip_first(nffw_info, &cpp_id, &addr); + if (err) + goto exit_close_nffw; + + err = nfp_mip_try_read(cpp, cpp_id, addr, mip); +exit_close_nffw: + nfp_nffw_info_close(nffw_info); + return err; +} + +/* + * nfp_mip_open() - Get device MIP structure + * @cpp: NFP CPP Handle + * + * Copy MIP structure from NFP device and return it. The returned + * structure is handled internally by the library and should be + * freed by calling nfp_mip_close(). + * + * Return: pointer to mip, NULL on failure. + */ +struct nfp_mip * +nfp_mip_open(struct nfp_cpp *cpp) +{ + struct nfp_mip *mip; + int err; + + mip = malloc(sizeof(*mip)); + if (!mip) + return NULL; + + err = nfp_mip_read_resource(cpp, mip); + if (err) { + free(mip); + return NULL; + } + + mip->name[sizeof(mip->name) - 1] = 0; + + return mip; +} + +void +nfp_mip_close(struct nfp_mip *mip) +{ + free(mip); +} + +const char * +nfp_mip_name(const struct nfp_mip *mip) +{ + return mip->name; +} + +/* + * nfp_mip_symtab() - Get the address and size of the MIP symbol table + * @mip: MIP handle + * @addr: Location for NFP DDR address of MIP symbol table + * @size: Location for size of MIP symbol table + */ +void +nfp_mip_symtab(const struct nfp_mip *mip, uint32_t *addr, uint32_t *size) +{ + *addr = rte_le_to_cpu_32(mip->symtab_addr); + *size = rte_le_to_cpu_32(mip->symtab_size); +} + +/* + * nfp_mip_strtab() - Get the address and size of the MIP symbol name table + * @mip: MIP handle + * @addr: Location for NFP DDR address of MIP symbol name table + * @size: Location for size of MIP symbol name table + */ +void +nfp_mip_strtab(const struct nfp_mip *mip, uint32_t *addr, uint32_t *size) +{ + *addr = rte_le_to_cpu_32(mip->strtab_addr); + *size = rte_le_to_cpu_32(mip->strtab_size); +} diff --git a/drivers/net/nfp/nfpcore/nfp_mip.h b/drivers/net/nfp/nfpcore/nfp_mip.h new file mode 100644 index 00000000..d0919b58 --- /dev/null +++ b/drivers/net/nfp/nfpcore/nfp_mip.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2018 Netronome Systems, Inc. + * All rights reserved. + */ + +#ifndef __NFP_MIP_H__ +#define __NFP_MIP_H__ + +#include "nfp_nffw.h" + +struct nfp_mip; + +struct nfp_mip *nfp_mip_open(struct nfp_cpp *cpp); +void nfp_mip_close(struct nfp_mip *mip); + +const char *nfp_mip_name(const struct nfp_mip *mip); +void nfp_mip_symtab(const struct nfp_mip *mip, uint32_t *addr, uint32_t *size); +void nfp_mip_strtab(const struct nfp_mip *mip, uint32_t *addr, uint32_t *size); +int nfp_nffw_info_mip_first(struct nfp_nffw_info *state, uint32_t *cpp_id, + uint64_t *off); +#endif diff --git a/drivers/net/nfp/nfpcore/nfp_mutex.c b/drivers/net/nfp/nfpcore/nfp_mutex.c new file mode 100644 index 00000000..318c5800 --- /dev/null +++ b/drivers/net/nfp/nfpcore/nfp_mutex.c @@ -0,0 +1,424 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2018 Netronome Systems, Inc. + * All rights reserved. + */ + +#include <errno.h> + +#include <malloc.h> +#include <time.h> +#include <sched.h> + +#include "nfp_cpp.h" +#include "nfp6000/nfp6000.h" + +#define MUTEX_LOCKED(interface) ((((uint32_t)(interface)) << 16) | 0x000f) +#define MUTEX_UNLOCK(interface) (0 | 0x0000) + +#define MUTEX_IS_LOCKED(value) (((value) & 0xffff) == 0x000f) +#define MUTEX_IS_UNLOCKED(value) (((value) & 0xffff) == 0x0000) +#define MUTEX_INTERFACE(value) (((value) >> 16) & 0xffff) + +/* + * If you need more than 65536 recursive locks, please + * rethink your code. + */ +#define MUTEX_DEPTH_MAX 0xffff + +struct nfp_cpp_mutex { + struct nfp_cpp *cpp; + uint8_t target; + uint16_t depth; + unsigned long long address; + uint32_t key; + unsigned int usage; + struct nfp_cpp_mutex *prev, *next; +}; + +static int +_nfp_cpp_mutex_validate(uint32_t model, int *target, unsigned long long address) +{ + /* Address must be 64-bit aligned */ + if (address & 7) + return NFP_ERRNO(EINVAL); + + if (NFP_CPP_MODEL_IS_6000(model)) { + if (*target != NFP_CPP_TARGET_MU) + return NFP_ERRNO(EINVAL); + } else { + return NFP_ERRNO(EINVAL); + } + + return 0; +} + +/* + * Initialize a mutex location + * + * The CPP target:address must point to a 64-bit aligned location, and + * will initialize 64 bits of data at the location. + * + * This creates the initial mutex state, as locked by this + * nfp_cpp_interface(). + * + * This function should only be called when setting up + * the initial lock state upon boot-up of the system. + * + * @param mutex NFP CPP Mutex handle + * @param target NFP CPP target ID (ie NFP_CPP_TARGET_CLS or + * NFP_CPP_TARGET_MU) + * @param address Offset into the address space of the NFP CPP target ID + * @param key Unique 32-bit value for this mutex + * + * @return 0 on success, or -1 on failure (and set errno accordingly). + */ +int +nfp_cpp_mutex_init(struct nfp_cpp *cpp, int target, unsigned long long address, + uint32_t key) +{ + uint32_t model = nfp_cpp_model(cpp); + uint32_t muw = NFP_CPP_ID(target, 4, 0); /* atomic_write */ + int err; + + err = _nfp_cpp_mutex_validate(model, &target, address); + if (err < 0) + return err; + + err = nfp_cpp_writel(cpp, muw, address + 4, key); + if (err < 0) + return err; + + err = + nfp_cpp_writel(cpp, muw, address + 0, + MUTEX_LOCKED(nfp_cpp_interface(cpp))); + if (err < 0) + return err; + + return 0; +} + +/* + * Create a mutex handle from an address controlled by a MU Atomic engine + * + * The CPP target:address must point to a 64-bit aligned location, and + * reserve 64 bits of data at the location for use by the handle. + * + * Only target/address pairs that point to entities that support the + * MU Atomic Engine are supported. + * + * @param cpp NFP CPP handle + * @param target NFP CPP target ID (ie NFP_CPP_TARGET_CLS or + * NFP_CPP_TARGET_MU) + * @param address Offset into the address space of the NFP CPP target ID + * @param key 32-bit unique key (must match the key at this location) + * + * @return A non-NULL struct nfp_cpp_mutex * on success, NULL on failure. + */ +struct nfp_cpp_mutex * +nfp_cpp_mutex_alloc(struct nfp_cpp *cpp, int target, + unsigned long long address, uint32_t key) +{ + uint32_t model = nfp_cpp_model(cpp); + struct nfp_cpp_mutex *mutex; + uint32_t mur = NFP_CPP_ID(target, 3, 0); /* atomic_read */ + int err; + uint32_t tmp; + + /* Look for cached mutex */ + for (mutex = cpp->mutex_cache; mutex; mutex = mutex->next) { + if (mutex->target == target && mutex->address == address) + break; + } + + if (mutex) { + if (mutex->key == key) { + mutex->usage++; + return mutex; + } + + /* If the key doesn't match... */ + return NFP_ERRPTR(EEXIST); + } + + err = _nfp_cpp_mutex_validate(model, &target, address); + if (err < 0) + return NULL; + + err = nfp_cpp_readl(cpp, mur, address + 4, &tmp); + if (err < 0) + return NULL; + + if (tmp != key) + return NFP_ERRPTR(EEXIST); + + mutex = calloc(sizeof(*mutex), 1); + if (!mutex) + return NFP_ERRPTR(ENOMEM); + + mutex->cpp = cpp; + mutex->target = target; + mutex->address = address; + mutex->key = key; + mutex->depth = 0; + mutex->usage = 1; + + /* Add mutex to the cache */ + if (cpp->mutex_cache) { + cpp->mutex_cache->prev = mutex; + mutex->next = cpp->mutex_cache; + cpp->mutex_cache = mutex; + } else { + cpp->mutex_cache = mutex; + } + + return mutex; +} + +struct nfp_cpp * +nfp_cpp_mutex_cpp(struct nfp_cpp_mutex *mutex) +{ + return mutex->cpp; +} + +uint32_t +nfp_cpp_mutex_key(struct nfp_cpp_mutex *mutex) +{ + return mutex->key; +} + +uint16_t +nfp_cpp_mutex_owner(struct nfp_cpp_mutex *mutex) +{ + uint32_t mur = NFP_CPP_ID(mutex->target, 3, 0); /* atomic_read */ + uint32_t value, key; + int err; + + err = nfp_cpp_readl(mutex->cpp, mur, mutex->address, &value); + if (err < 0) + return err; + + err = nfp_cpp_readl(mutex->cpp, mur, mutex->address + 4, &key); + if (err < 0) + return err; + + if (key != mutex->key) + return NFP_ERRNO(EPERM); + + if (!MUTEX_IS_LOCKED(value)) + return 0; + + return MUTEX_INTERFACE(value); +} + +int +nfp_cpp_mutex_target(struct nfp_cpp_mutex *mutex) +{ + return mutex->target; +} + +uint64_t +nfp_cpp_mutex_address(struct nfp_cpp_mutex *mutex) +{ + return mutex->address; +} + +/* + * Free a mutex handle - does not alter the lock state + * + * @param mutex NFP CPP Mutex handle + */ +void +nfp_cpp_mutex_free(struct nfp_cpp_mutex *mutex) +{ + mutex->usage--; + if (mutex->usage > 0) + return; + + /* Remove mutex from the cache */ + if (mutex->next) + mutex->next->prev = mutex->prev; + if (mutex->prev) + mutex->prev->next = mutex->next; + + /* If mutex->cpp == NULL, something broke */ + if (mutex->cpp && mutex == mutex->cpp->mutex_cache) + mutex->cpp->mutex_cache = mutex->next; + + free(mutex); +} + +/* + * Lock a mutex handle, using the NFP MU Atomic Engine + * + * @param mutex NFP CPP Mutex handle + * + * @return 0 on success, or -1 on failure (and set errno accordingly). + */ +int +nfp_cpp_mutex_lock(struct nfp_cpp_mutex *mutex) +{ + int err; + time_t warn_at = time(NULL) + 15; + + while ((err = nfp_cpp_mutex_trylock(mutex)) != 0) { + /* If errno != EBUSY, then the lock was damaged */ + if (err < 0 && errno != EBUSY) + return err; + if (time(NULL) >= warn_at) { + printf("Warning: waiting for NFP mutex\n"); + printf("\tusage:%u\n", mutex->usage); + printf("\tdepth:%hd]\n", mutex->depth); + printf("\ttarget:%d\n", mutex->target); + printf("\taddr:%llx\n", mutex->address); + printf("\tkey:%08x]\n", mutex->key); + warn_at = time(NULL) + 60; + } + sched_yield(); + } + return 0; +} + +/* + * Unlock a mutex handle, using the NFP MU Atomic Engine + * + * @param mutex NFP CPP Mutex handle + * + * @return 0 on success, or -1 on failure (and set errno accordingly). + */ +int +nfp_cpp_mutex_unlock(struct nfp_cpp_mutex *mutex) +{ + uint32_t muw = NFP_CPP_ID(mutex->target, 4, 0); /* atomic_write */ + uint32_t mur = NFP_CPP_ID(mutex->target, 3, 0); /* atomic_read */ + struct nfp_cpp *cpp = mutex->cpp; + uint32_t key, value; + uint16_t interface = nfp_cpp_interface(cpp); + int err; + + if (mutex->depth > 1) { + mutex->depth--; + return 0; + } + + err = nfp_cpp_readl(mutex->cpp, mur, mutex->address, &value); + if (err < 0) + goto exit; + + err = nfp_cpp_readl(mutex->cpp, mur, mutex->address + 4, &key); + if (err < 0) + goto exit; + + if (key != mutex->key) { + err = NFP_ERRNO(EPERM); + goto exit; + } + + if (value != MUTEX_LOCKED(interface)) { + err = NFP_ERRNO(EACCES); + goto exit; + } + + err = nfp_cpp_writel(cpp, muw, mutex->address, MUTEX_UNLOCK(interface)); + if (err < 0) + goto exit; + + mutex->depth = 0; + +exit: + return err; +} + +/* + * Attempt to lock a mutex handle, using the NFP MU Atomic Engine + * + * Valid lock states: + * + * 0x....0000 - Unlocked + * 0x....000f - Locked + * + * @param mutex NFP CPP Mutex handle + * @return 0 if the lock succeeded, -1 on failure (and errno set + * appropriately). + */ +int +nfp_cpp_mutex_trylock(struct nfp_cpp_mutex *mutex) +{ + uint32_t mur = NFP_CPP_ID(mutex->target, 3, 0); /* atomic_read */ + uint32_t muw = NFP_CPP_ID(mutex->target, 4, 0); /* atomic_write */ + uint32_t mus = NFP_CPP_ID(mutex->target, 5, 3); /* test_set_imm */ + uint32_t key, value, tmp; + struct nfp_cpp *cpp = mutex->cpp; + int err; + + if (mutex->depth > 0) { + if (mutex->depth == MUTEX_DEPTH_MAX) + return NFP_ERRNO(E2BIG); + + mutex->depth++; + return 0; + } + + /* Verify that the lock marker is not damaged */ + err = nfp_cpp_readl(cpp, mur, mutex->address + 4, &key); + if (err < 0) + goto exit; + + if (key != mutex->key) { + err = NFP_ERRNO(EPERM); + goto exit; + } + + /* + * Compare against the unlocked state, and if true, + * write the interface id into the top 16 bits, and + * mark as locked. + */ + value = MUTEX_LOCKED(nfp_cpp_interface(cpp)); + + /* + * We use test_set_imm here, as it implies a read + * of the current state, and sets the bits in the + * bytemask of the command to 1s. Since the mutex + * is guaranteed to be 64-bit aligned, the bytemask + * of this 32-bit command is ensured to be 8'b00001111, + * which implies that the lower 4 bits will be set to + * ones regardless of the initial state. + * + * Since this is a 'Readback' operation, with no Pull + * data, we can treat this as a normal Push (read) + * atomic, which returns the original value. + */ + err = nfp_cpp_readl(cpp, mus, mutex->address, &tmp); + if (err < 0) + goto exit; + + /* Was it unlocked? */ + if (MUTEX_IS_UNLOCKED(tmp)) { + /* + * The read value can only be 0x....0000 in the unlocked state. + * If there was another contending for this lock, then + * the lock state would be 0x....000f + * + * Write our owner ID into the lock + * While not strictly necessary, this helps with + * debug and bookkeeping. + */ + err = nfp_cpp_writel(cpp, muw, mutex->address, value); + if (err < 0) + goto exit; + + mutex->depth = 1; + goto exit; + } + + /* Already locked by us? Success! */ + if (tmp == value) { + mutex->depth = 1; + goto exit; + } + + err = NFP_ERRNO(MUTEX_IS_LOCKED(tmp) ? EBUSY : EINVAL); + +exit: + return err; +} diff --git a/drivers/net/nfp/nfpcore/nfp_nffw.c b/drivers/net/nfp/nfpcore/nfp_nffw.c new file mode 100644 index 00000000..8bec0e3c --- /dev/null +++ b/drivers/net/nfp/nfpcore/nfp_nffw.c @@ -0,0 +1,235 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2018 Netronome Systems, Inc. + * All rights reserved. + */ + +#include "nfp_cpp.h" +#include "nfp_nffw.h" +#include "nfp_mip.h" +#include "nfp6000/nfp6000.h" +#include "nfp_resource.h" + +/* + * flg_info_version = flags[0]<27:16> + * This is a small version counter intended only to detect if the current + * implementation can read the current struct. Struct changes should be very + * rare and as such a 12-bit counter should cover large spans of time. By the + * time it wraps around, we don't expect to have 4096 versions of this struct + * to be in use at the same time. + */ +static uint32_t +nffw_res_info_version_get(const struct nfp_nffw_info_data *res) +{ + return (res->flags[0] >> 16) & 0xfff; +} + +/* flg_init = flags[0]<0> */ +static uint32_t +nffw_res_flg_init_get(const struct nfp_nffw_info_data *res) +{ + return (res->flags[0] >> 0) & 1; +} + +/* loaded = loaded__mu_da__mip_off_hi<31:31> */ +static uint32_t +nffw_fwinfo_loaded_get(const struct nffw_fwinfo *fi) +{ + return (fi->loaded__mu_da__mip_off_hi >> 31) & 1; +} + +/* mip_cppid = mip_cppid */ +static uint32_t +nffw_fwinfo_mip_cppid_get(const struct nffw_fwinfo *fi) +{ + return fi->mip_cppid; +} + +/* loaded = loaded__mu_da__mip_off_hi<8:8> */ +static uint32_t +nffw_fwinfo_mip_mu_da_get(const struct nffw_fwinfo *fi) +{ + return (fi->loaded__mu_da__mip_off_hi >> 8) & 1; +} + +/* mip_offset = (loaded__mu_da__mip_off_hi<7:0> << 8) | mip_offset_lo */ +static uint64_t +nffw_fwinfo_mip_offset_get(const struct nffw_fwinfo *fi) +{ + uint64_t mip_off_hi = fi->loaded__mu_da__mip_off_hi; + + return (mip_off_hi & 0xFF) << 32 | fi->mip_offset_lo; +} + +#define NFP_IMB_TGTADDRESSMODECFG_MODE_of(_x) (((_x) >> 13) & 0x7) +#define NFP_IMB_TGTADDRESSMODECFG_ADDRMODE BIT(12) +#define NFP_IMB_TGTADDRESSMODECFG_ADDRMODE_32_BIT 0 +#define NFP_IMB_TGTADDRESSMODECFG_ADDRMODE_40_BIT BIT(12) + +static int +nfp_mip_mu_locality_lsb(struct nfp_cpp *cpp) +{ + unsigned int mode, addr40; + uint32_t xpbaddr, imbcppat; + int err; + + /* Hardcoded XPB IMB Base, island 0 */ + xpbaddr = 0x000a0000 + NFP_CPP_TARGET_MU * 4; + err = nfp_xpb_readl(cpp, xpbaddr, &imbcppat); + if (err < 0) + return err; + + mode = NFP_IMB_TGTADDRESSMODECFG_MODE_of(imbcppat); + addr40 = !!(imbcppat & NFP_IMB_TGTADDRESSMODECFG_ADDRMODE); + + return nfp_cppat_mu_locality_lsb(mode, addr40); +} + +static unsigned int +nffw_res_fwinfos(struct nfp_nffw_info_data *fwinf, struct nffw_fwinfo **arr) +{ + /* + * For the this code, version 0 is most likely to be version 1 in this + * case. Since the kernel driver does not take responsibility for + * initialising the nfp.nffw resource, any previous code (CA firmware or + * userspace) that left the version 0 and did set the init flag is going + * to be version 1. + */ + switch (nffw_res_info_version_get(fwinf)) { + case 0: + case 1: + *arr = &fwinf->info.v1.fwinfo[0]; + return NFFW_FWINFO_CNT_V1; + case 2: + *arr = &fwinf->info.v2.fwinfo[0]; + return NFFW_FWINFO_CNT_V2; + default: + *arr = NULL; + return 0; + } +} + +/* + * nfp_nffw_info_open() - Acquire the lock on the NFFW table + * @cpp: NFP CPP handle + * + * Return: 0, or -ERRNO + */ +struct nfp_nffw_info * +nfp_nffw_info_open(struct nfp_cpp *cpp) +{ + struct nfp_nffw_info_data *fwinf; + struct nfp_nffw_info *state; + uint32_t info_ver; + int err; + + state = malloc(sizeof(*state)); + if (!state) + return NULL; + + memset(state, 0, sizeof(*state)); + + state->res = nfp_resource_acquire(cpp, NFP_RESOURCE_NFP_NFFW); + if (!state->res) + goto err_free; + + fwinf = &state->fwinf; + + if (sizeof(*fwinf) > nfp_resource_size(state->res)) + goto err_release; + + err = nfp_cpp_read(cpp, nfp_resource_cpp_id(state->res), + nfp_resource_address(state->res), + fwinf, sizeof(*fwinf)); + if (err < (int)sizeof(*fwinf)) + goto err_release; + + if (!nffw_res_flg_init_get(fwinf)) + goto err_release; + + info_ver = nffw_res_info_version_get(fwinf); + if (info_ver > NFFW_INFO_VERSION_CURRENT) + goto err_release; + + state->cpp = cpp; + return state; + +err_release: + nfp_resource_release(state->res); +err_free: + free(state); + return NULL; +} + +/* + * nfp_nffw_info_release() - Release the lock on the NFFW table + * @state: NFP FW info state + * + * Return: 0, or -ERRNO + */ +void +nfp_nffw_info_close(struct nfp_nffw_info *state) +{ + nfp_resource_release(state->res); + free(state); +} + +/* + * nfp_nffw_info_fwid_first() - Return the first firmware ID in the NFFW + * @state: NFP FW info state + * + * Return: First NFFW firmware info, NULL on failure + */ +static struct nffw_fwinfo * +nfp_nffw_info_fwid_first(struct nfp_nffw_info *state) +{ + struct nffw_fwinfo *fwinfo; + unsigned int cnt, i; + + cnt = nffw_res_fwinfos(&state->fwinf, &fwinfo); + if (!cnt) + return NULL; + + for (i = 0; i < cnt; i++) + if (nffw_fwinfo_loaded_get(&fwinfo[i])) + return &fwinfo[i]; + + return NULL; +} + +/* + * nfp_nffw_info_mip_first() - Retrieve the location of the first FW's MIP + * @state: NFP FW info state + * @cpp_id: Pointer to the CPP ID of the MIP + * @off: Pointer to the CPP Address of the MIP + * + * Return: 0, or -ERRNO + */ +int +nfp_nffw_info_mip_first(struct nfp_nffw_info *state, uint32_t *cpp_id, + uint64_t *off) +{ + struct nffw_fwinfo *fwinfo; + + fwinfo = nfp_nffw_info_fwid_first(state); + if (!fwinfo) + return -EINVAL; + + *cpp_id = nffw_fwinfo_mip_cppid_get(fwinfo); + *off = nffw_fwinfo_mip_offset_get(fwinfo); + + if (nffw_fwinfo_mip_mu_da_get(fwinfo)) { + int locality_off; + + if (NFP_CPP_ID_TARGET_of(*cpp_id) != NFP_CPP_TARGET_MU) + return 0; + + locality_off = nfp_mip_mu_locality_lsb(state->cpp); + if (locality_off < 0) + return locality_off; + + *off &= ~(NFP_MU_ADDR_ACCESS_TYPE_MASK << locality_off); + *off |= NFP_MU_ADDR_ACCESS_TYPE_DIRECT << locality_off; + } + + return 0; +} diff --git a/drivers/net/nfp/nfpcore/nfp_nffw.h b/drivers/net/nfp/nfpcore/nfp_nffw.h new file mode 100644 index 00000000..3bbdf1c1 --- /dev/null +++ b/drivers/net/nfp/nfpcore/nfp_nffw.h @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2018 Netronome Systems, Inc. + * All rights reserved. + */ + +#ifndef __NFP_NFFW_H__ +#define __NFP_NFFW_H__ + +#include "nfp-common/nfp_platform.h" +#include "nfp_cpp.h" + +/* + * Init-CSR owner IDs for firmware map to firmware IDs which start at 4. + * Lower IDs are reserved for target and loader IDs. + */ +#define NFFW_FWID_EXT 3 /* For active MEs that we didn't load. */ +#define NFFW_FWID_BASE 4 + +#define NFFW_FWID_ALL 255 + +/* Init-CSR owner IDs for firmware map to firmware IDs which start at 4. + * Lower IDs are reserved for target and loader IDs. + */ +#define NFFW_FWID_EXT 3 /* For active MEs that we didn't load. */ +#define NFFW_FWID_BASE 4 + +#define NFFW_FWID_ALL 255 + +/** + * NFFW_INFO_VERSION history: + * 0: This was never actually used (before versioning), but it refers to + * the previous struct which had FWINFO_CNT = MEINFO_CNT = 120 that later + * changed to 200. + * 1: First versioned struct, with + * FWINFO_CNT = 120 + * MEINFO_CNT = 120 + * 2: FWINFO_CNT = 200 + * MEINFO_CNT = 200 + */ +#define NFFW_INFO_VERSION_CURRENT 2 + +/* Enough for all current chip families */ +#define NFFW_MEINFO_CNT_V1 120 +#define NFFW_FWINFO_CNT_V1 120 +#define NFFW_MEINFO_CNT_V2 200 +#define NFFW_FWINFO_CNT_V2 200 + +struct nffw_meinfo { + uint32_t ctxmask__fwid__meid; +}; + +struct nffw_fwinfo { + uint32_t loaded__mu_da__mip_off_hi; + uint32_t mip_cppid; /* 0 means no MIP */ + uint32_t mip_offset_lo; +}; + +struct nfp_nffw_info_v1 { + struct nffw_meinfo meinfo[NFFW_MEINFO_CNT_V1]; + struct nffw_fwinfo fwinfo[NFFW_FWINFO_CNT_V1]; +}; + +struct nfp_nffw_info_v2 { + struct nffw_meinfo meinfo[NFFW_MEINFO_CNT_V2]; + struct nffw_fwinfo fwinfo[NFFW_FWINFO_CNT_V2]; +}; + +struct nfp_nffw_info_data { + uint32_t flags[2]; + union { + struct nfp_nffw_info_v1 v1; + struct nfp_nffw_info_v2 v2; + } info; +}; + +struct nfp_nffw_info { + struct nfp_cpp *cpp; + struct nfp_resource *res; + + struct nfp_nffw_info_data fwinf; +}; + +struct nfp_nffw_info *nfp_nffw_info_open(struct nfp_cpp *cpp); +void nfp_nffw_info_close(struct nfp_nffw_info *state); + +#endif diff --git a/drivers/net/nfp/nfpcore/nfp_nsp.c b/drivers/net/nfp/nfpcore/nfp_nsp.c new file mode 100644 index 00000000..876a4017 --- /dev/null +++ b/drivers/net/nfp/nfpcore/nfp_nsp.c @@ -0,0 +1,427 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2018 Netronome Systems, Inc. + * All rights reserved. + */ + +#define NFP_SUBSYS "nfp_nsp" + +#include <stdio.h> +#include <time.h> + +#include <rte_common.h> + +#include "nfp_cpp.h" +#include "nfp_nsp.h" +#include "nfp_resource.h" + +int +nfp_nsp_config_modified(struct nfp_nsp *state) +{ + return state->modified; +} + +void +nfp_nsp_config_set_modified(struct nfp_nsp *state, int modified) +{ + state->modified = modified; +} + +void * +nfp_nsp_config_entries(struct nfp_nsp *state) +{ + return state->entries; +} + +unsigned int +nfp_nsp_config_idx(struct nfp_nsp *state) +{ + return state->idx; +} + +void +nfp_nsp_config_set_state(struct nfp_nsp *state, void *entries, unsigned int idx) +{ + state->entries = entries; + state->idx = idx; +} + +void +nfp_nsp_config_clear_state(struct nfp_nsp *state) +{ + state->entries = NULL; + state->idx = 0; +} + +static void +nfp_nsp_print_extended_error(uint32_t ret_val) +{ + int i; + + if (!ret_val) + return; + + for (i = 0; i < (int)ARRAY_SIZE(nsp_errors); i++) + if (ret_val == (uint32_t)nsp_errors[i].code) + printf("err msg: %s\n", nsp_errors[i].msg); +} + +static int +nfp_nsp_check(struct nfp_nsp *state) +{ + struct nfp_cpp *cpp = state->cpp; + uint64_t nsp_status, reg; + uint32_t nsp_cpp; + int err; + + nsp_cpp = nfp_resource_cpp_id(state->res); + nsp_status = nfp_resource_address(state->res) + NSP_STATUS; + + err = nfp_cpp_readq(cpp, nsp_cpp, nsp_status, ®); + if (err < 0) + return err; + + if (FIELD_GET(NSP_STATUS_MAGIC, reg) != NSP_MAGIC) { + printf("Cannot detect NFP Service Processor\n"); + return -ENODEV; + } + + state->ver.major = FIELD_GET(NSP_STATUS_MAJOR, reg); + state->ver.minor = FIELD_GET(NSP_STATUS_MINOR, reg); + + if (state->ver.major != NSP_MAJOR || state->ver.minor < NSP_MINOR) { + printf("Unsupported ABI %hu.%hu\n", state->ver.major, + state->ver.minor); + return -EINVAL; + } + + if (reg & NSP_STATUS_BUSY) { + printf("Service processor busy!\n"); + return -EBUSY; + } + + return 0; +} + +/* + * nfp_nsp_open() - Prepare for communication and lock the NSP resource. + * @cpp: NFP CPP Handle + */ +struct nfp_nsp * +nfp_nsp_open(struct nfp_cpp *cpp) +{ + struct nfp_resource *res; + struct nfp_nsp *state; + int err; + + res = nfp_resource_acquire(cpp, NFP_RESOURCE_NSP); + if (!res) + return NULL; + + state = malloc(sizeof(*state)); + if (!state) { + nfp_resource_release(res); + return NULL; + } + memset(state, 0, sizeof(*state)); + state->cpp = cpp; + state->res = res; + + err = nfp_nsp_check(state); + if (err) { + nfp_nsp_close(state); + return NULL; + } + + return state; +} + +/* + * nfp_nsp_close() - Clean up and unlock the NSP resource. + * @state: NFP SP state + */ +void +nfp_nsp_close(struct nfp_nsp *state) +{ + nfp_resource_release(state->res); + free(state); +} + +uint16_t +nfp_nsp_get_abi_ver_major(struct nfp_nsp *state) +{ + return state->ver.major; +} + +uint16_t +nfp_nsp_get_abi_ver_minor(struct nfp_nsp *state) +{ + return state->ver.minor; +} + +static int +nfp_nsp_wait_reg(struct nfp_cpp *cpp, uint64_t *reg, uint32_t nsp_cpp, + uint64_t addr, uint64_t mask, uint64_t val) +{ + struct timespec wait; + int count; + int err; + + wait.tv_sec = 0; + wait.tv_nsec = 25000000; + count = 0; + + for (;;) { + err = nfp_cpp_readq(cpp, nsp_cpp, addr, reg); + if (err < 0) + return err; + + if ((*reg & mask) == val) + return 0; + + nanosleep(&wait, 0); + if (count++ > 1000) + return -ETIMEDOUT; + } +} + +/* + * nfp_nsp_command() - Execute a command on the NFP Service Processor + * @state: NFP SP state + * @code: NFP SP Command Code + * @option: NFP SP Command Argument + * @buff_cpp: NFP SP Buffer CPP Address info + * @buff_addr: NFP SP Buffer Host address + * + * Return: 0 for success with no result + * + * positive value for NSP completion with a result code + * + * -EAGAIN if the NSP is not yet present + * -ENODEV if the NSP is not a supported model + * -EBUSY if the NSP is stuck + * -EINTR if interrupted while waiting for completion + * -ETIMEDOUT if the NSP took longer than 30 seconds to complete + */ +static int +nfp_nsp_command(struct nfp_nsp *state, uint16_t code, uint32_t option, + uint32_t buff_cpp, uint64_t buff_addr) +{ + uint64_t reg, ret_val, nsp_base, nsp_buffer, nsp_status, nsp_command; + struct nfp_cpp *cpp = state->cpp; + uint32_t nsp_cpp; + int err; + + nsp_cpp = nfp_resource_cpp_id(state->res); + nsp_base = nfp_resource_address(state->res); + nsp_status = nsp_base + NSP_STATUS; + nsp_command = nsp_base + NSP_COMMAND; + nsp_buffer = nsp_base + NSP_BUFFER; + + err = nfp_nsp_check(state); + if (err) + return err; + + if (!FIELD_FIT(NSP_BUFFER_CPP, buff_cpp >> 8) || + !FIELD_FIT(NSP_BUFFER_ADDRESS, buff_addr)) { + printf("Host buffer out of reach %08x %" PRIx64 "\n", + buff_cpp, buff_addr); + return -EINVAL; + } + + err = nfp_cpp_writeq(cpp, nsp_cpp, nsp_buffer, + FIELD_PREP(NSP_BUFFER_CPP, buff_cpp >> 8) | + FIELD_PREP(NSP_BUFFER_ADDRESS, buff_addr)); + if (err < 0) + return err; + + err = nfp_cpp_writeq(cpp, nsp_cpp, nsp_command, + FIELD_PREP(NSP_COMMAND_OPTION, option) | + FIELD_PREP(NSP_COMMAND_CODE, code) | + FIELD_PREP(NSP_COMMAND_START, 1)); + if (err < 0) + return err; + + /* Wait for NSP_COMMAND_START to go to 0 */ + err = nfp_nsp_wait_reg(cpp, ®, nsp_cpp, nsp_command, + NSP_COMMAND_START, 0); + if (err) { + printf("Error %d waiting for code 0x%04x to start\n", + err, code); + return err; + } + + /* Wait for NSP_STATUS_BUSY to go to 0 */ + err = nfp_nsp_wait_reg(cpp, ®, nsp_cpp, nsp_status, NSP_STATUS_BUSY, + 0); + if (err) { + printf("Error %d waiting for code 0x%04x to complete\n", + err, code); + return err; + } + + err = nfp_cpp_readq(cpp, nsp_cpp, nsp_command, &ret_val); + if (err < 0) + return err; + ret_val = FIELD_GET(NSP_COMMAND_OPTION, ret_val); + + err = FIELD_GET(NSP_STATUS_RESULT, reg); + if (err) { + printf("Result (error) code set: %d (%d) command: %d\n", + -err, (int)ret_val, code); + nfp_nsp_print_extended_error(ret_val); + return -err; + } + + return ret_val; +} + +#define SZ_1M 0x00100000 + +static int +nfp_nsp_command_buf(struct nfp_nsp *nsp, uint16_t code, uint32_t option, + const void *in_buf, unsigned int in_size, void *out_buf, + unsigned int out_size) +{ + struct nfp_cpp *cpp = nsp->cpp; + unsigned int max_size; + uint64_t reg, cpp_buf; + int ret, err; + uint32_t cpp_id; + + if (nsp->ver.minor < 13) { + printf("NSP: Code 0x%04x with buffer not supported\n", code); + printf("\t(ABI %hu.%hu)\n", nsp->ver.major, nsp->ver.minor); + return -EOPNOTSUPP; + } + + err = nfp_cpp_readq(cpp, nfp_resource_cpp_id(nsp->res), + nfp_resource_address(nsp->res) + + NSP_DFLT_BUFFER_CONFIG, + ®); + if (err < 0) + return err; + + max_size = RTE_MAX(in_size, out_size); + if (FIELD_GET(NSP_DFLT_BUFFER_SIZE_MB, reg) * SZ_1M < max_size) { + printf("NSP: default buffer too small for command 0x%04x\n", + code); + printf("\t(%llu < %u)\n", + FIELD_GET(NSP_DFLT_BUFFER_SIZE_MB, reg) * SZ_1M, + max_size); + return -EINVAL; + } + + err = nfp_cpp_readq(cpp, nfp_resource_cpp_id(nsp->res), + nfp_resource_address(nsp->res) + + NSP_DFLT_BUFFER, + ®); + if (err < 0) + return err; + + cpp_id = FIELD_GET(NSP_BUFFER_CPP, reg) << 8; + cpp_buf = FIELD_GET(NSP_BUFFER_ADDRESS, reg); + + if (in_buf && in_size) { + err = nfp_cpp_write(cpp, cpp_id, cpp_buf, in_buf, in_size); + if (err < 0) + return err; + } + /* Zero out remaining part of the buffer */ + if (out_buf && out_size && out_size > in_size) { + memset(out_buf, 0, out_size - in_size); + err = nfp_cpp_write(cpp, cpp_id, cpp_buf + in_size, out_buf, + out_size - in_size); + if (err < 0) + return err; + } + + ret = nfp_nsp_command(nsp, code, option, cpp_id, cpp_buf); + if (ret < 0) + return ret; + + if (out_buf && out_size) { + err = nfp_cpp_read(cpp, cpp_id, cpp_buf, out_buf, out_size); + if (err < 0) + return err; + } + + return ret; +} + +int +nfp_nsp_wait(struct nfp_nsp *state) +{ + struct timespec wait; + int count; + int err; + + wait.tv_sec = 0; + wait.tv_nsec = 25000000; + count = 0; + + for (;;) { + err = nfp_nsp_command(state, SPCODE_NOOP, 0, 0, 0); + if (err != -EAGAIN) + break; + + nanosleep(&wait, 0); + + if (count++ > 1000) { + err = -ETIMEDOUT; + break; + } + } + if (err) + printf("NSP failed to respond %d\n", err); + + return err; +} + +int +nfp_nsp_device_soft_reset(struct nfp_nsp *state) +{ + return nfp_nsp_command(state, SPCODE_SOFT_RESET, 0, 0, 0); +} + +int +nfp_nsp_mac_reinit(struct nfp_nsp *state) +{ + return nfp_nsp_command(state, SPCODE_MAC_INIT, 0, 0, 0); +} + +int +nfp_nsp_load_fw(struct nfp_nsp *state, void *buf, unsigned int size) +{ + return nfp_nsp_command_buf(state, SPCODE_FW_LOAD, size, buf, size, + NULL, 0); +} + +int +nfp_nsp_read_eth_table(struct nfp_nsp *state, void *buf, unsigned int size) +{ + return nfp_nsp_command_buf(state, SPCODE_ETH_RESCAN, size, NULL, 0, + buf, size); +} + +int +nfp_nsp_write_eth_table(struct nfp_nsp *state, const void *buf, + unsigned int size) +{ + return nfp_nsp_command_buf(state, SPCODE_ETH_CONTROL, size, buf, size, + NULL, 0); +} + +int +nfp_nsp_read_identify(struct nfp_nsp *state, void *buf, unsigned int size) +{ + return nfp_nsp_command_buf(state, SPCODE_NSP_IDENTIFY, size, NULL, 0, + buf, size); +} + +int +nfp_nsp_read_sensors(struct nfp_nsp *state, unsigned int sensor_mask, void *buf, + unsigned int size) +{ + return nfp_nsp_command_buf(state, SPCODE_NSP_SENSORS, sensor_mask, NULL, + 0, buf, size); +} diff --git a/drivers/net/nfp/nfpcore/nfp_nsp.h b/drivers/net/nfp/nfpcore/nfp_nsp.h new file mode 100644 index 00000000..c9c7b0d0 --- /dev/null +++ b/drivers/net/nfp/nfpcore/nfp_nsp.h @@ -0,0 +1,304 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2018 Netronome Systems, Inc. + * All rights reserved. + */ + +#ifndef NSP_NSP_H +#define NSP_NSP_H 1 + +#include "nfp_cpp.h" +#include "nfp_nsp.h" + +#define GENMASK_ULL(h, l) \ + (((~0ULL) - (1ULL << (l)) + 1) & \ + (~0ULL >> (64 - 1 - (h)))) + +#define __bf_shf(x) (__builtin_ffsll(x) - 1) + +#define FIELD_GET(_mask, _reg) \ + (__extension__ ({ \ + typeof(_mask) _x = (_mask); \ + (typeof(_x))(((_reg) & (_x)) >> __bf_shf(_x)); \ + })) + +#define FIELD_FIT(_mask, _val) \ + (__extension__ ({ \ + typeof(_mask) _x = (_mask); \ + !((((typeof(_x))_val) << __bf_shf(_x)) & ~(_x)); \ + })) + +#define FIELD_PREP(_mask, _val) \ + (__extension__ ({ \ + typeof(_mask) _x = (_mask); \ + ((typeof(_x))(_val) << __bf_shf(_x)) & (_x); \ + })) + +/* Offsets relative to the CSR base */ +#define NSP_STATUS 0x00 +#define NSP_STATUS_MAGIC GENMASK_ULL(63, 48) +#define NSP_STATUS_MAJOR GENMASK_ULL(47, 44) +#define NSP_STATUS_MINOR GENMASK_ULL(43, 32) +#define NSP_STATUS_CODE GENMASK_ULL(31, 16) +#define NSP_STATUS_RESULT GENMASK_ULL(15, 8) +#define NSP_STATUS_BUSY BIT_ULL(0) + +#define NSP_COMMAND 0x08 +#define NSP_COMMAND_OPTION GENMASK_ULL(63, 32) +#define NSP_COMMAND_CODE GENMASK_ULL(31, 16) +#define NSP_COMMAND_START BIT_ULL(0) + +/* CPP address to retrieve the data from */ +#define NSP_BUFFER 0x10 +#define NSP_BUFFER_CPP GENMASK_ULL(63, 40) +#define NSP_BUFFER_PCIE GENMASK_ULL(39, 38) +#define NSP_BUFFER_ADDRESS GENMASK_ULL(37, 0) + +#define NSP_DFLT_BUFFER 0x18 + +#define NSP_DFLT_BUFFER_CONFIG 0x20 +#define NSP_DFLT_BUFFER_SIZE_MB GENMASK_ULL(7, 0) + +#define NSP_MAGIC 0xab10 +#define NSP_MAJOR 0 +#define NSP_MINOR 8 + +#define NSP_CODE_MAJOR GENMASK(15, 12) +#define NSP_CODE_MINOR GENMASK(11, 0) + +enum nfp_nsp_cmd { + SPCODE_NOOP = 0, /* No operation */ + SPCODE_SOFT_RESET = 1, /* Soft reset the NFP */ + SPCODE_FW_DEFAULT = 2, /* Load default (UNDI) FW */ + SPCODE_PHY_INIT = 3, /* Initialize the PHY */ + SPCODE_MAC_INIT = 4, /* Initialize the MAC */ + SPCODE_PHY_RXADAPT = 5, /* Re-run PHY RX Adaptation */ + SPCODE_FW_LOAD = 6, /* Load fw from buffer, len in option */ + SPCODE_ETH_RESCAN = 7, /* Rescan ETHs, write ETH_TABLE to buf */ + SPCODE_ETH_CONTROL = 8, /* Update media config from buffer */ + SPCODE_NSP_SENSORS = 12, /* Read NSP sensor(s) */ + SPCODE_NSP_IDENTIFY = 13, /* Read NSP version */ +}; + +static const struct { + int code; + const char *msg; +} nsp_errors[] = { + { 6010, "could not map to phy for port" }, + { 6011, "not an allowed rate/lanes for port" }, + { 6012, "not an allowed rate/lanes for port" }, + { 6013, "high/low error, change other port first" }, + { 6014, "config not found in flash" }, +}; + +struct nfp_nsp { + struct nfp_cpp *cpp; + struct nfp_resource *res; + struct { + uint16_t major; + uint16_t minor; + } ver; + + /* Eth table config state */ + int modified; + unsigned int idx; + void *entries; +}; + +struct nfp_nsp *nfp_nsp_open(struct nfp_cpp *cpp); +void nfp_nsp_close(struct nfp_nsp *state); +uint16_t nfp_nsp_get_abi_ver_major(struct nfp_nsp *state); +uint16_t nfp_nsp_get_abi_ver_minor(struct nfp_nsp *state); +int nfp_nsp_wait(struct nfp_nsp *state); +int nfp_nsp_device_soft_reset(struct nfp_nsp *state); +int nfp_nsp_load_fw(struct nfp_nsp *state, void *buf, unsigned int size); +int nfp_nsp_mac_reinit(struct nfp_nsp *state); +int nfp_nsp_read_identify(struct nfp_nsp *state, void *buf, unsigned int size); +int nfp_nsp_read_sensors(struct nfp_nsp *state, unsigned int sensor_mask, + void *buf, unsigned int size); + +static inline int nfp_nsp_has_mac_reinit(struct nfp_nsp *state) +{ + return nfp_nsp_get_abi_ver_minor(state) > 20; +} + +enum nfp_eth_interface { + NFP_INTERFACE_NONE = 0, + NFP_INTERFACE_SFP = 1, + NFP_INTERFACE_SFPP = 10, + NFP_INTERFACE_SFP28 = 28, + NFP_INTERFACE_QSFP = 40, + NFP_INTERFACE_CXP = 100, + NFP_INTERFACE_QSFP28 = 112, +}; + +enum nfp_eth_media { + NFP_MEDIA_DAC_PASSIVE = 0, + NFP_MEDIA_DAC_ACTIVE, + NFP_MEDIA_FIBRE, +}; + +enum nfp_eth_aneg { + NFP_ANEG_AUTO = 0, + NFP_ANEG_SEARCH, + NFP_ANEG_25G_CONSORTIUM, + NFP_ANEG_25G_IEEE, + NFP_ANEG_DISABLED, +}; + +enum nfp_eth_fec { + NFP_FEC_AUTO_BIT = 0, + NFP_FEC_BASER_BIT, + NFP_FEC_REED_SOLOMON_BIT, + NFP_FEC_DISABLED_BIT, +}; + +#define NFP_FEC_AUTO BIT(NFP_FEC_AUTO_BIT) +#define NFP_FEC_BASER BIT(NFP_FEC_BASER_BIT) +#define NFP_FEC_REED_SOLOMON BIT(NFP_FEC_REED_SOLOMON_BIT) +#define NFP_FEC_DISABLED BIT(NFP_FEC_DISABLED_BIT) + +#define ETH_ALEN 6 + +/** + * struct nfp_eth_table - ETH table information + * @count: number of table entries + * @max_index: max of @index fields of all @ports + * @ports: table of ports + * + * @eth_index: port index according to legacy ethX numbering + * @index: chip-wide first channel index + * @nbi: NBI index + * @base: first channel index (within NBI) + * @lanes: number of channels + * @speed: interface speed (in Mbps) + * @interface: interface (module) plugged in + * @media: media type of the @interface + * @fec: forward error correction mode + * @aneg: auto negotiation mode + * @mac_addr: interface MAC address + * @label_port: port id + * @label_subport: id of interface within port (for split ports) + * @enabled: is enabled? + * @tx_enabled: is TX enabled? + * @rx_enabled: is RX enabled? + * @override_changed: is media reconfig pending? + * + * @port_type: one of %PORT_* defines for ethtool + * @port_lanes: total number of lanes on the port (sum of lanes of all subports) + * @is_split: is interface part of a split port + * @fec_modes_supported: bitmap of FEC modes supported + */ +struct nfp_eth_table { + unsigned int count; + unsigned int max_index; + struct nfp_eth_table_port { + unsigned int eth_index; + unsigned int index; + unsigned int nbi; + unsigned int base; + unsigned int lanes; + unsigned int speed; + + unsigned int interface; + enum nfp_eth_media media; + + enum nfp_eth_fec fec; + enum nfp_eth_aneg aneg; + + uint8_t mac_addr[ETH_ALEN]; + + uint8_t label_port; + uint8_t label_subport; + + int enabled; + int tx_enabled; + int rx_enabled; + + int override_changed; + + /* Computed fields */ + uint8_t port_type; + + unsigned int port_lanes; + + int is_split; + + unsigned int fec_modes_supported; + } ports[0]; +}; + +struct nfp_eth_table *nfp_eth_read_ports(struct nfp_cpp *cpp); + +int nfp_eth_set_mod_enable(struct nfp_cpp *cpp, unsigned int idx, int enable); +int nfp_eth_set_configured(struct nfp_cpp *cpp, unsigned int idx, + int configed); +int +nfp_eth_set_fec(struct nfp_cpp *cpp, unsigned int idx, enum nfp_eth_fec mode); + +int nfp_nsp_read_eth_table(struct nfp_nsp *state, void *buf, unsigned int size); +int nfp_nsp_write_eth_table(struct nfp_nsp *state, const void *buf, + unsigned int size); +void nfp_nsp_config_set_state(struct nfp_nsp *state, void *entries, + unsigned int idx); +void nfp_nsp_config_clear_state(struct nfp_nsp *state); +void nfp_nsp_config_set_modified(struct nfp_nsp *state, int modified); +void *nfp_nsp_config_entries(struct nfp_nsp *state); +int nfp_nsp_config_modified(struct nfp_nsp *state); +unsigned int nfp_nsp_config_idx(struct nfp_nsp *state); + +static inline int nfp_eth_can_support_fec(struct nfp_eth_table_port *eth_port) +{ + return !!eth_port->fec_modes_supported; +} + +static inline unsigned int +nfp_eth_supported_fec_modes(struct nfp_eth_table_port *eth_port) +{ + return eth_port->fec_modes_supported; +} + +struct nfp_nsp *nfp_eth_config_start(struct nfp_cpp *cpp, unsigned int idx); +int nfp_eth_config_commit_end(struct nfp_nsp *nsp); +void nfp_eth_config_cleanup_end(struct nfp_nsp *nsp); + +int __nfp_eth_set_aneg(struct nfp_nsp *nsp, enum nfp_eth_aneg mode); +int __nfp_eth_set_speed(struct nfp_nsp *nsp, unsigned int speed); +int __nfp_eth_set_split(struct nfp_nsp *nsp, unsigned int lanes); + +/** + * struct nfp_nsp_identify - NSP static information + * @version: opaque version string + * @flags: version flags + * @br_primary: branch id of primary bootloader + * @br_secondary: branch id of secondary bootloader + * @br_nsp: branch id of NSP + * @primary: version of primarary bootloader + * @secondary: version id of secondary bootloader + * @nsp: version id of NSP + * @sensor_mask: mask of present sensors available on NIC + */ +struct nfp_nsp_identify { + char version[40]; + uint8_t flags; + uint8_t br_primary; + uint8_t br_secondary; + uint8_t br_nsp; + uint16_t primary; + uint16_t secondary; + uint16_t nsp; + uint64_t sensor_mask; +}; + +struct nfp_nsp_identify *__nfp_nsp_identify(struct nfp_nsp *nsp); + +enum nfp_nsp_sensor_id { + NFP_SENSOR_CHIP_TEMPERATURE, + NFP_SENSOR_ASSEMBLY_POWER, + NFP_SENSOR_ASSEMBLY_12V_POWER, + NFP_SENSOR_ASSEMBLY_3V3_POWER, +}; + +int nfp_hwmon_read_sensor(struct nfp_cpp *cpp, enum nfp_nsp_sensor_id id, + long *val); + +#endif diff --git a/drivers/net/nfp/nfpcore/nfp_nsp_cmds.c b/drivers/net/nfp/nfpcore/nfp_nsp_cmds.c new file mode 100644 index 00000000..bfd1eddb --- /dev/null +++ b/drivers/net/nfp/nfpcore/nfp_nsp_cmds.c @@ -0,0 +1,109 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2018 Netronome Systems, Inc. + * All rights reserved. + */ + +#include <stdio.h> +#include <rte_byteorder.h> +#include "nfp_cpp.h" +#include "nfp_nsp.h" +#include "nfp_nffw.h" + +struct nsp_identify { + uint8_t version[40]; + uint8_t flags; + uint8_t br_primary; + uint8_t br_secondary; + uint8_t br_nsp; + uint16_t primary; + uint16_t secondary; + uint16_t nsp; + uint8_t reserved[6]; + uint64_t sensor_mask; +}; + +struct nfp_nsp_identify * +__nfp_nsp_identify(struct nfp_nsp *nsp) +{ + struct nfp_nsp_identify *nspi = NULL; + struct nsp_identify *ni; + int ret; + + if (nfp_nsp_get_abi_ver_minor(nsp) < 15) + return NULL; + + ni = malloc(sizeof(*ni)); + if (!ni) + return NULL; + + memset(ni, 0, sizeof(*ni)); + ret = nfp_nsp_read_identify(nsp, ni, sizeof(*ni)); + if (ret < 0) { + printf("reading bsp version failed %d\n", + ret); + goto exit_free; + } + + nspi = malloc(sizeof(*nspi)); + if (!nspi) + goto exit_free; + + memset(nspi, 0, sizeof(*nspi)); + memcpy(nspi->version, ni->version, sizeof(nspi->version)); + nspi->version[sizeof(nspi->version) - 1] = '\0'; + nspi->flags = ni->flags; + nspi->br_primary = ni->br_primary; + nspi->br_secondary = ni->br_secondary; + nspi->br_nsp = ni->br_nsp; + nspi->primary = rte_le_to_cpu_16(ni->primary); + nspi->secondary = rte_le_to_cpu_16(ni->secondary); + nspi->nsp = rte_le_to_cpu_16(ni->nsp); + nspi->sensor_mask = rte_le_to_cpu_64(ni->sensor_mask); + +exit_free: + free(ni); + return nspi; +} + +struct nfp_sensors { + uint32_t chip_temp; + uint32_t assembly_power; + uint32_t assembly_12v_power; + uint32_t assembly_3v3_power; +}; + +int +nfp_hwmon_read_sensor(struct nfp_cpp *cpp, enum nfp_nsp_sensor_id id, long *val) +{ + struct nfp_sensors s; + struct nfp_nsp *nsp; + int ret; + + nsp = nfp_nsp_open(cpp); + if (!nsp) + return -EIO; + + ret = nfp_nsp_read_sensors(nsp, BIT(id), &s, sizeof(s)); + nfp_nsp_close(nsp); + + if (ret < 0) + return ret; + + switch (id) { + case NFP_SENSOR_CHIP_TEMPERATURE: + *val = rte_le_to_cpu_32(s.chip_temp); + break; + case NFP_SENSOR_ASSEMBLY_POWER: + *val = rte_le_to_cpu_32(s.assembly_power); + break; + case NFP_SENSOR_ASSEMBLY_12V_POWER: + *val = rte_le_to_cpu_32(s.assembly_12v_power); + break; + case NFP_SENSOR_ASSEMBLY_3V3_POWER: + *val = rte_le_to_cpu_32(s.assembly_3v3_power); + break; + default: + return -EINVAL; + } + return 0; +} diff --git a/drivers/net/nfp/nfpcore/nfp_nsp_eth.c b/drivers/net/nfp/nfpcore/nfp_nsp_eth.c new file mode 100644 index 00000000..67946891 --- /dev/null +++ b/drivers/net/nfp/nfpcore/nfp_nsp_eth.c @@ -0,0 +1,665 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2018 Netronome Systems, Inc. + * All rights reserved. + */ + +#include <stdio.h> +#include <rte_common.h> +#include <rte_byteorder.h> +#include "nfp_cpp.h" +#include "nfp_nsp.h" +#include "nfp6000/nfp6000.h" + +#define GENMASK_ULL(h, l) \ + (((~0ULL) - (1ULL << (l)) + 1) & \ + (~0ULL >> (64 - 1 - (h)))) + +#define __bf_shf(x) (__builtin_ffsll(x) - 1) + +#define FIELD_GET(_mask, _reg) \ + (__extension__ ({ \ + typeof(_mask) _x = (_mask); \ + (typeof(_x))(((_reg) & (_x)) >> __bf_shf(_x)); \ + })) + +#define FIELD_FIT(_mask, _val) \ + (__extension__ ({ \ + typeof(_mask) _x = (_mask); \ + !((((typeof(_x))_val) << __bf_shf(_x)) & ~(_x)); \ + })) + +#define FIELD_PREP(_mask, _val) \ + (__extension__ ({ \ + typeof(_mask) _x = (_mask); \ + ((typeof(_x))(_val) << __bf_shf(_x)) & (_x); \ + })) + +#define NSP_ETH_NBI_PORT_COUNT 24 +#define NSP_ETH_MAX_COUNT (2 * NSP_ETH_NBI_PORT_COUNT) +#define NSP_ETH_TABLE_SIZE (NSP_ETH_MAX_COUNT * \ + sizeof(union eth_table_entry)) + +#define NSP_ETH_PORT_LANES GENMASK_ULL(3, 0) +#define NSP_ETH_PORT_INDEX GENMASK_ULL(15, 8) +#define NSP_ETH_PORT_LABEL GENMASK_ULL(53, 48) +#define NSP_ETH_PORT_PHYLABEL GENMASK_ULL(59, 54) +#define NSP_ETH_PORT_FEC_SUPP_BASER BIT_ULL(60) +#define NSP_ETH_PORT_FEC_SUPP_RS BIT_ULL(61) + +#define NSP_ETH_PORT_LANES_MASK rte_cpu_to_le_64(NSP_ETH_PORT_LANES) + +#define NSP_ETH_STATE_CONFIGURED BIT_ULL(0) +#define NSP_ETH_STATE_ENABLED BIT_ULL(1) +#define NSP_ETH_STATE_TX_ENABLED BIT_ULL(2) +#define NSP_ETH_STATE_RX_ENABLED BIT_ULL(3) +#define NSP_ETH_STATE_RATE GENMASK_ULL(11, 8) +#define NSP_ETH_STATE_INTERFACE GENMASK_ULL(19, 12) +#define NSP_ETH_STATE_MEDIA GENMASK_ULL(21, 20) +#define NSP_ETH_STATE_OVRD_CHNG BIT_ULL(22) +#define NSP_ETH_STATE_ANEG GENMASK_ULL(25, 23) +#define NSP_ETH_STATE_FEC GENMASK_ULL(27, 26) + +#define NSP_ETH_CTRL_CONFIGURED BIT_ULL(0) +#define NSP_ETH_CTRL_ENABLED BIT_ULL(1) +#define NSP_ETH_CTRL_TX_ENABLED BIT_ULL(2) +#define NSP_ETH_CTRL_RX_ENABLED BIT_ULL(3) +#define NSP_ETH_CTRL_SET_RATE BIT_ULL(4) +#define NSP_ETH_CTRL_SET_LANES BIT_ULL(5) +#define NSP_ETH_CTRL_SET_ANEG BIT_ULL(6) +#define NSP_ETH_CTRL_SET_FEC BIT_ULL(7) + +/* Which connector port. */ +#define PORT_TP 0x00 +#define PORT_AUI 0x01 +#define PORT_MII 0x02 +#define PORT_FIBRE 0x03 +#define PORT_BNC 0x04 +#define PORT_DA 0x05 +#define PORT_NONE 0xef +#define PORT_OTHER 0xff + +#define SPEED_10 10 +#define SPEED_100 100 +#define SPEED_1000 1000 +#define SPEED_2500 2500 +#define SPEED_5000 5000 +#define SPEED_10000 10000 +#define SPEED_14000 14000 +#define SPEED_20000 20000 +#define SPEED_25000 25000 +#define SPEED_40000 40000 +#define SPEED_50000 50000 +#define SPEED_56000 56000 +#define SPEED_100000 100000 + +enum nfp_eth_raw { + NSP_ETH_RAW_PORT = 0, + NSP_ETH_RAW_STATE, + NSP_ETH_RAW_MAC, + NSP_ETH_RAW_CONTROL, + + NSP_ETH_NUM_RAW +}; + +enum nfp_eth_rate { + RATE_INVALID = 0, + RATE_10M, + RATE_100M, + RATE_1G, + RATE_10G, + RATE_25G, +}; + +union eth_table_entry { + struct { + uint64_t port; + uint64_t state; + uint8_t mac_addr[6]; + uint8_t resv[2]; + uint64_t control; + }; + uint64_t raw[NSP_ETH_NUM_RAW]; +}; + +static const struct { + enum nfp_eth_rate rate; + unsigned int speed; +} nsp_eth_rate_tbl[] = { + { RATE_INVALID, 0, }, + { RATE_10M, SPEED_10, }, + { RATE_100M, SPEED_100, }, + { RATE_1G, SPEED_1000, }, + { RATE_10G, SPEED_10000, }, + { RATE_25G, SPEED_25000, }, +}; + +static unsigned int +nfp_eth_rate2speed(enum nfp_eth_rate rate) +{ + int i; + + for (i = 0; i < (int)ARRAY_SIZE(nsp_eth_rate_tbl); i++) + if (nsp_eth_rate_tbl[i].rate == rate) + return nsp_eth_rate_tbl[i].speed; + + return 0; +} + +static unsigned int +nfp_eth_speed2rate(unsigned int speed) +{ + int i; + + for (i = 0; i < (int)ARRAY_SIZE(nsp_eth_rate_tbl); i++) + if (nsp_eth_rate_tbl[i].speed == speed) + return nsp_eth_rate_tbl[i].rate; + + return RATE_INVALID; +} + +static void +nfp_eth_copy_mac_reverse(uint8_t *dst, const uint8_t *src) +{ + int i; + + for (i = 0; i < (int)ETH_ALEN; i++) + dst[ETH_ALEN - i - 1] = src[i]; +} + +static void +nfp_eth_port_translate(struct nfp_nsp *nsp, const union eth_table_entry *src, + unsigned int index, struct nfp_eth_table_port *dst) +{ + unsigned int rate; + unsigned int fec; + uint64_t port, state; + + port = rte_le_to_cpu_64(src->port); + state = rte_le_to_cpu_64(src->state); + + dst->eth_index = FIELD_GET(NSP_ETH_PORT_INDEX, port); + dst->index = index; + dst->nbi = index / NSP_ETH_NBI_PORT_COUNT; + dst->base = index % NSP_ETH_NBI_PORT_COUNT; + dst->lanes = FIELD_GET(NSP_ETH_PORT_LANES, port); + + dst->enabled = FIELD_GET(NSP_ETH_STATE_ENABLED, state); + dst->tx_enabled = FIELD_GET(NSP_ETH_STATE_TX_ENABLED, state); + dst->rx_enabled = FIELD_GET(NSP_ETH_STATE_RX_ENABLED, state); + + rate = nfp_eth_rate2speed(FIELD_GET(NSP_ETH_STATE_RATE, state)); + dst->speed = dst->lanes * rate; + + dst->interface = FIELD_GET(NSP_ETH_STATE_INTERFACE, state); + dst->media = FIELD_GET(NSP_ETH_STATE_MEDIA, state); + + nfp_eth_copy_mac_reverse(dst->mac_addr, src->mac_addr); + + dst->label_port = FIELD_GET(NSP_ETH_PORT_PHYLABEL, port); + dst->label_subport = FIELD_GET(NSP_ETH_PORT_LABEL, port); + + if (nfp_nsp_get_abi_ver_minor(nsp) < 17) + return; + + dst->override_changed = FIELD_GET(NSP_ETH_STATE_OVRD_CHNG, state); + dst->aneg = FIELD_GET(NSP_ETH_STATE_ANEG, state); + + if (nfp_nsp_get_abi_ver_minor(nsp) < 22) + return; + + fec = FIELD_GET(NSP_ETH_PORT_FEC_SUPP_BASER, port); + dst->fec_modes_supported |= fec << NFP_FEC_BASER_BIT; + fec = FIELD_GET(NSP_ETH_PORT_FEC_SUPP_RS, port); + dst->fec_modes_supported |= fec << NFP_FEC_REED_SOLOMON_BIT; + if (dst->fec_modes_supported) + dst->fec_modes_supported |= NFP_FEC_AUTO | NFP_FEC_DISABLED; + + dst->fec = 1 << FIELD_GET(NSP_ETH_STATE_FEC, state); +} + +static void +nfp_eth_calc_port_geometry(struct nfp_eth_table *table) +{ + unsigned int i, j; + + for (i = 0; i < table->count; i++) { + table->max_index = RTE_MAX(table->max_index, + table->ports[i].index); + + for (j = 0; j < table->count; j++) { + if (table->ports[i].label_port != + table->ports[j].label_port) + continue; + table->ports[i].port_lanes += table->ports[j].lanes; + + if (i == j) + continue; + if (table->ports[i].label_subport == + table->ports[j].label_subport) + printf("Port %d subport %d is a duplicate\n", + table->ports[i].label_port, + table->ports[i].label_subport); + + table->ports[i].is_split = 1; + } + } +} + +static void +nfp_eth_calc_port_type(struct nfp_eth_table_port *entry) +{ + if (entry->interface == NFP_INTERFACE_NONE) { + entry->port_type = PORT_NONE; + return; + } + + if (entry->media == NFP_MEDIA_FIBRE) + entry->port_type = PORT_FIBRE; + else + entry->port_type = PORT_DA; +} + +static struct nfp_eth_table * +__nfp_eth_read_ports(struct nfp_nsp *nsp) +{ + union eth_table_entry *entries; + struct nfp_eth_table *table; + uint32_t table_sz; + int i, j, ret, cnt = 0; + + entries = malloc(NSP_ETH_TABLE_SIZE); + if (!entries) + return NULL; + + memset(entries, 0, NSP_ETH_TABLE_SIZE); + ret = nfp_nsp_read_eth_table(nsp, entries, NSP_ETH_TABLE_SIZE); + if (ret < 0) { + printf("reading port table failed %d\n", ret); + goto err; + } + + for (i = 0; i < NSP_ETH_MAX_COUNT; i++) + if (entries[i].port & NSP_ETH_PORT_LANES_MASK) + cnt++; + + /* Some versions of flash will give us 0 instead of port count. For + * those that give a port count, verify it against the value calculated + * above. + */ + if (ret && ret != cnt) { + printf("table entry count (%d) unmatch entries present (%d)\n", + ret, cnt); + goto err; + } + + table_sz = sizeof(*table) + sizeof(struct nfp_eth_table_port) * cnt; + table = malloc(table_sz); + if (!table) + goto err; + + memset(table, 0, table_sz); + table->count = cnt; + for (i = 0, j = 0; i < NSP_ETH_MAX_COUNT; i++) + if (entries[i].port & NSP_ETH_PORT_LANES_MASK) + nfp_eth_port_translate(nsp, &entries[i], i, + &table->ports[j++]); + + nfp_eth_calc_port_geometry(table); + for (i = 0; i < (int)table->count; i++) + nfp_eth_calc_port_type(&table->ports[i]); + + free(entries); + + return table; + +err: + free(entries); + return NULL; +} + +/* + * nfp_eth_read_ports() - retrieve port information + * @cpp: NFP CPP handle + * + * Read the port information from the device. Returned structure should + * be freed with kfree() once no longer needed. + * + * Return: populated ETH table or NULL on error. + */ +struct nfp_eth_table * +nfp_eth_read_ports(struct nfp_cpp *cpp) +{ + struct nfp_eth_table *ret; + struct nfp_nsp *nsp; + + nsp = nfp_nsp_open(cpp); + if (!nsp) + return NULL; + + ret = __nfp_eth_read_ports(nsp); + nfp_nsp_close(nsp); + + return ret; +} + +struct nfp_nsp * +nfp_eth_config_start(struct nfp_cpp *cpp, unsigned int idx) +{ + union eth_table_entry *entries; + struct nfp_nsp *nsp; + int ret; + + entries = malloc(NSP_ETH_TABLE_SIZE); + if (!entries) + return NULL; + + memset(entries, 0, NSP_ETH_TABLE_SIZE); + nsp = nfp_nsp_open(cpp); + if (!nsp) { + free(entries); + return nsp; + } + + ret = nfp_nsp_read_eth_table(nsp, entries, NSP_ETH_TABLE_SIZE); + if (ret < 0) { + printf("reading port table failed %d\n", ret); + goto err; + } + + if (!(entries[idx].port & NSP_ETH_PORT_LANES_MASK)) { + printf("trying to set port state on disabled port %d\n", idx); + goto err; + } + + nfp_nsp_config_set_state(nsp, entries, idx); + return nsp; + +err: + nfp_nsp_close(nsp); + free(entries); + return NULL; +} + +void +nfp_eth_config_cleanup_end(struct nfp_nsp *nsp) +{ + union eth_table_entry *entries = nfp_nsp_config_entries(nsp); + + nfp_nsp_config_set_modified(nsp, 0); + nfp_nsp_config_clear_state(nsp); + nfp_nsp_close(nsp); + free(entries); +} + +/* + * nfp_eth_config_commit_end() - perform recorded configuration changes + * @nsp: NFP NSP handle returned from nfp_eth_config_start() + * + * Perform the configuration which was requested with __nfp_eth_set_*() + * helpers and recorded in @nsp state. If device was already configured + * as requested or no __nfp_eth_set_*() operations were made no NSP command + * will be performed. + * + * Return: + * 0 - configuration successful; + * 1 - no changes were needed; + * -ERRNO - configuration failed. + */ +int +nfp_eth_config_commit_end(struct nfp_nsp *nsp) +{ + union eth_table_entry *entries = nfp_nsp_config_entries(nsp); + int ret = 1; + + if (nfp_nsp_config_modified(nsp)) { + ret = nfp_nsp_write_eth_table(nsp, entries, NSP_ETH_TABLE_SIZE); + ret = ret < 0 ? ret : 0; + } + + nfp_eth_config_cleanup_end(nsp); + + return ret; +} + +/* + * nfp_eth_set_mod_enable() - set PHY module enable control bit + * @cpp: NFP CPP handle + * @idx: NFP chip-wide port index + * @enable: Desired state + * + * Enable or disable PHY module (this usually means setting the TX lanes + * disable bits). + * + * Return: + * 0 - configuration successful; + * 1 - no changes were needed; + * -ERRNO - configuration failed. + */ +int +nfp_eth_set_mod_enable(struct nfp_cpp *cpp, unsigned int idx, int enable) +{ + union eth_table_entry *entries; + struct nfp_nsp *nsp; + uint64_t reg; + + nsp = nfp_eth_config_start(cpp, idx); + if (!nsp) + return -1; + + entries = nfp_nsp_config_entries(nsp); + + /* Check if we are already in requested state */ + reg = rte_le_to_cpu_64(entries[idx].state); + if (enable != (int)FIELD_GET(NSP_ETH_CTRL_ENABLED, reg)) { + reg = rte_le_to_cpu_64(entries[idx].control); + reg &= ~NSP_ETH_CTRL_ENABLED; + reg |= FIELD_PREP(NSP_ETH_CTRL_ENABLED, enable); + entries[idx].control = rte_cpu_to_le_64(reg); + + nfp_nsp_config_set_modified(nsp, 1); + } + + return nfp_eth_config_commit_end(nsp); +} + +/* + * nfp_eth_set_configured() - set PHY module configured control bit + * @cpp: NFP CPP handle + * @idx: NFP chip-wide port index + * @configed: Desired state + * + * Set the ifup/ifdown state on the PHY. + * + * Return: + * 0 - configuration successful; + * 1 - no changes were needed; + * -ERRNO - configuration failed. + */ +int +nfp_eth_set_configured(struct nfp_cpp *cpp, unsigned int idx, int configed) +{ + union eth_table_entry *entries; + struct nfp_nsp *nsp; + uint64_t reg; + + nsp = nfp_eth_config_start(cpp, idx); + if (!nsp) + return -EIO; + + /* + * Older ABI versions did support this feature, however this has only + * been reliable since ABI 20. + */ + if (nfp_nsp_get_abi_ver_minor(nsp) < 20) { + nfp_eth_config_cleanup_end(nsp); + return -EOPNOTSUPP; + } + + entries = nfp_nsp_config_entries(nsp); + + /* Check if we are already in requested state */ + reg = rte_le_to_cpu_64(entries[idx].state); + if (configed != (int)FIELD_GET(NSP_ETH_STATE_CONFIGURED, reg)) { + reg = rte_le_to_cpu_64(entries[idx].control); + reg &= ~NSP_ETH_CTRL_CONFIGURED; + reg |= FIELD_PREP(NSP_ETH_CTRL_CONFIGURED, configed); + entries[idx].control = rte_cpu_to_le_64(reg); + + nfp_nsp_config_set_modified(nsp, 1); + } + + return nfp_eth_config_commit_end(nsp); +} + +static int +nfp_eth_set_bit_config(struct nfp_nsp *nsp, unsigned int raw_idx, + const uint64_t mask, const unsigned int shift, + unsigned int val, const uint64_t ctrl_bit) +{ + union eth_table_entry *entries = nfp_nsp_config_entries(nsp); + unsigned int idx = nfp_nsp_config_idx(nsp); + uint64_t reg; + + /* + * Note: set features were added in ABI 0.14 but the error + * codes were initially not populated correctly. + */ + if (nfp_nsp_get_abi_ver_minor(nsp) < 17) { + printf("set operations not supported, please update flash\n"); + return -EOPNOTSUPP; + } + + /* Check if we are already in requested state */ + reg = rte_le_to_cpu_64(entries[idx].raw[raw_idx]); + if (val == (reg & mask) >> shift) + return 0; + + reg &= ~mask; + reg |= (val << shift) & mask; + entries[idx].raw[raw_idx] = rte_cpu_to_le_64(reg); + + entries[idx].control |= rte_cpu_to_le_64(ctrl_bit); + + nfp_nsp_config_set_modified(nsp, 1); + + return 0; +} + +#define NFP_ETH_SET_BIT_CONFIG(nsp, raw_idx, mask, val, ctrl_bit) \ + (__extension__ ({ \ + typeof(mask) _x = (mask); \ + nfp_eth_set_bit_config(nsp, raw_idx, _x, __bf_shf(_x), \ + val, ctrl_bit); \ + })) + +/* + * __nfp_eth_set_aneg() - set PHY autonegotiation control bit + * @nsp: NFP NSP handle returned from nfp_eth_config_start() + * @mode: Desired autonegotiation mode + * + * Allow/disallow PHY module to advertise/perform autonegotiation. + * Will write to hwinfo overrides in the flash (persistent config). + * + * Return: 0 or -ERRNO. + */ +int +__nfp_eth_set_aneg(struct nfp_nsp *nsp, enum nfp_eth_aneg mode) +{ + return NFP_ETH_SET_BIT_CONFIG(nsp, NSP_ETH_RAW_STATE, + NSP_ETH_STATE_ANEG, mode, + NSP_ETH_CTRL_SET_ANEG); +} + +/* + * __nfp_eth_set_fec() - set PHY forward error correction control bit + * @nsp: NFP NSP handle returned from nfp_eth_config_start() + * @mode: Desired fec mode + * + * Set the PHY module forward error correction mode. + * Will write to hwinfo overrides in the flash (persistent config). + * + * Return: 0 or -ERRNO. + */ +static int +__nfp_eth_set_fec(struct nfp_nsp *nsp, enum nfp_eth_fec mode) +{ + return NFP_ETH_SET_BIT_CONFIG(nsp, NSP_ETH_RAW_STATE, + NSP_ETH_STATE_FEC, mode, + NSP_ETH_CTRL_SET_FEC); +} + +/* + * nfp_eth_set_fec() - set PHY forward error correction control mode + * @cpp: NFP CPP handle + * @idx: NFP chip-wide port index + * @mode: Desired fec mode + * + * Return: + * 0 - configuration successful; + * 1 - no changes were needed; + * -ERRNO - configuration failed. + */ +int +nfp_eth_set_fec(struct nfp_cpp *cpp, unsigned int idx, enum nfp_eth_fec mode) +{ + struct nfp_nsp *nsp; + int err; + + nsp = nfp_eth_config_start(cpp, idx); + if (!nsp) + return -EIO; + + err = __nfp_eth_set_fec(nsp, mode); + if (err) { + nfp_eth_config_cleanup_end(nsp); + return err; + } + + return nfp_eth_config_commit_end(nsp); +} + +/* + * __nfp_eth_set_speed() - set interface speed/rate + * @nsp: NFP NSP handle returned from nfp_eth_config_start() + * @speed: Desired speed (per lane) + * + * Set lane speed. Provided @speed value should be subport speed divided + * by number of lanes this subport is spanning (i.e. 10000 for 40G, 25000 for + * 50G, etc.) + * Will write to hwinfo overrides in the flash (persistent config). + * + * Return: 0 or -ERRNO. + */ +int +__nfp_eth_set_speed(struct nfp_nsp *nsp, unsigned int speed) +{ + enum nfp_eth_rate rate; + + rate = nfp_eth_speed2rate(speed); + if (rate == RATE_INVALID) { + printf("could not find matching lane rate for speed %u\n", + speed); + return -EINVAL; + } + + return NFP_ETH_SET_BIT_CONFIG(nsp, NSP_ETH_RAW_STATE, + NSP_ETH_STATE_RATE, rate, + NSP_ETH_CTRL_SET_RATE); +} + +/* + * __nfp_eth_set_split() - set interface lane split + * @nsp: NFP NSP handle returned from nfp_eth_config_start() + * @lanes: Desired lanes per port + * + * Set number of lanes in the port. + * Will write to hwinfo overrides in the flash (persistent config). + * + * Return: 0 or -ERRNO. + */ +int +__nfp_eth_set_split(struct nfp_nsp *nsp, unsigned int lanes) +{ + return NFP_ETH_SET_BIT_CONFIG(nsp, NSP_ETH_RAW_PORT, NSP_ETH_PORT_LANES, + lanes, NSP_ETH_CTRL_SET_LANES); +} diff --git a/drivers/net/nfp/nfpcore/nfp_resource.c b/drivers/net/nfp/nfpcore/nfp_resource.c new file mode 100644 index 00000000..dd41fa4d --- /dev/null +++ b/drivers/net/nfp/nfpcore/nfp_resource.c @@ -0,0 +1,266 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2018 Netronome Systems, Inc. + * All rights reserved. + */ + +#include <stdio.h> +#include <time.h> +#include <endian.h> + +#include <rte_string_fns.h> + +#include "nfp_cpp.h" +#include "nfp6000/nfp6000.h" +#include "nfp_resource.h" +#include "nfp_crc.h" + +#define NFP_RESOURCE_TBL_TARGET NFP_CPP_TARGET_MU +#define NFP_RESOURCE_TBL_BASE 0x8100000000ULL + +/* NFP Resource Table self-identifier */ +#define NFP_RESOURCE_TBL_NAME "nfp.res" +#define NFP_RESOURCE_TBL_KEY 0x00000000 /* Special key for entry 0 */ + +#define NFP_RESOURCE_ENTRY_NAME_SZ 8 + +/* + * struct nfp_resource_entry - Resource table entry + * @owner: NFP CPP Lock, interface owner + * @key: NFP CPP Lock, posix_crc32(name, 8) + * @region: Memory region descriptor + * @name: ASCII, zero padded name + * @reserved + * @cpp_action: CPP Action + * @cpp_token: CPP Token + * @cpp_target: CPP Target ID + * @page_offset: 256-byte page offset into target's CPP address + * @page_size: size, in 256-byte pages + */ +struct nfp_resource_entry { + struct nfp_resource_entry_mutex { + uint32_t owner; + uint32_t key; + } mutex; + struct nfp_resource_entry_region { + uint8_t name[NFP_RESOURCE_ENTRY_NAME_SZ]; + uint8_t reserved[5]; + uint8_t cpp_action; + uint8_t cpp_token; + uint8_t cpp_target; + uint32_t page_offset; + uint32_t page_size; + } region; +}; + +#define NFP_RESOURCE_TBL_SIZE 4096 +#define NFP_RESOURCE_TBL_ENTRIES (int)(NFP_RESOURCE_TBL_SIZE / \ + sizeof(struct nfp_resource_entry)) + +struct nfp_resource { + char name[NFP_RESOURCE_ENTRY_NAME_SZ + 1]; + uint32_t cpp_id; + uint64_t addr; + uint64_t size; + struct nfp_cpp_mutex *mutex; +}; + +static int +nfp_cpp_resource_find(struct nfp_cpp *cpp, struct nfp_resource *res) +{ + char name_pad[NFP_RESOURCE_ENTRY_NAME_SZ + 2]; + struct nfp_resource_entry entry; + uint32_t cpp_id, key; + int ret, i; + + cpp_id = NFP_CPP_ID(NFP_RESOURCE_TBL_TARGET, 3, 0); /* Atomic read */ + + memset(name_pad, 0, sizeof(name_pad)); + strlcpy(name_pad, res->name, sizeof(name_pad)); + + /* Search for a matching entry */ + if (!memcmp(name_pad, NFP_RESOURCE_TBL_NAME "\0\0\0\0\0\0\0\0", 8)) { + printf("Grabbing device lock not supported\n"); + return -EOPNOTSUPP; + } + key = nfp_crc32_posix(name_pad, NFP_RESOURCE_ENTRY_NAME_SZ); + + for (i = 0; i < NFP_RESOURCE_TBL_ENTRIES; i++) { + uint64_t addr = NFP_RESOURCE_TBL_BASE + + sizeof(struct nfp_resource_entry) * i; + + ret = nfp_cpp_read(cpp, cpp_id, addr, &entry, sizeof(entry)); + if (ret != sizeof(entry)) + return -EIO; + + if (entry.mutex.key != key) + continue; + + /* Found key! */ + res->mutex = + nfp_cpp_mutex_alloc(cpp, + NFP_RESOURCE_TBL_TARGET, addr, key); + res->cpp_id = NFP_CPP_ID(entry.region.cpp_target, + entry.region.cpp_action, + entry.region.cpp_token); + res->addr = ((uint64_t)entry.region.page_offset) << 8; + res->size = (uint64_t)entry.region.page_size << 8; + return 0; + } + + return -ENOENT; +} + +static int +nfp_resource_try_acquire(struct nfp_cpp *cpp, struct nfp_resource *res, + struct nfp_cpp_mutex *dev_mutex) +{ + int err; + + if (nfp_cpp_mutex_lock(dev_mutex)) + return -EINVAL; + + err = nfp_cpp_resource_find(cpp, res); + if (err) + goto err_unlock_dev; + + err = nfp_cpp_mutex_trylock(res->mutex); + if (err) + goto err_res_mutex_free; + + nfp_cpp_mutex_unlock(dev_mutex); + + return 0; + +err_res_mutex_free: + nfp_cpp_mutex_free(res->mutex); +err_unlock_dev: + nfp_cpp_mutex_unlock(dev_mutex); + + return err; +} + +/* + * nfp_resource_acquire() - Acquire a resource handle + * @cpp: NFP CPP handle + * @name: Name of the resource + * + * NOTE: This function locks the acquired resource + * + * Return: NFP Resource handle, or ERR_PTR() + */ +struct nfp_resource * +nfp_resource_acquire(struct nfp_cpp *cpp, const char *name) +{ + struct nfp_cpp_mutex *dev_mutex; + struct nfp_resource *res; + int err; + struct timespec wait; + int count; + + res = malloc(sizeof(*res)); + if (!res) + return NULL; + + memset(res, 0, sizeof(*res)); + + strncpy(res->name, name, NFP_RESOURCE_ENTRY_NAME_SZ); + + dev_mutex = nfp_cpp_mutex_alloc(cpp, NFP_RESOURCE_TBL_TARGET, + NFP_RESOURCE_TBL_BASE, + NFP_RESOURCE_TBL_KEY); + if (!dev_mutex) { + free(res); + return NULL; + } + + wait.tv_sec = 0; + wait.tv_nsec = 1000000; + count = 0; + + for (;;) { + err = nfp_resource_try_acquire(cpp, res, dev_mutex); + if (!err) + break; + if (err != -EBUSY) + goto err_free; + + if (count++ > 1000) { + printf("Error: resource %s timed out\n", name); + err = -EBUSY; + goto err_free; + } + + nanosleep(&wait, NULL); + } + + nfp_cpp_mutex_free(dev_mutex); + + return res; + +err_free: + nfp_cpp_mutex_free(dev_mutex); + free(res); + return NULL; +} + +/* + * nfp_resource_release() - Release a NFP Resource handle + * @res: NFP Resource handle + * + * NOTE: This function implictly unlocks the resource handle + */ +void +nfp_resource_release(struct nfp_resource *res) +{ + nfp_cpp_mutex_unlock(res->mutex); + nfp_cpp_mutex_free(res->mutex); + free(res); +} + +/* + * nfp_resource_cpp_id() - Return the cpp_id of a resource handle + * @res: NFP Resource handle + * + * Return: NFP CPP ID + */ +uint32_t +nfp_resource_cpp_id(const struct nfp_resource *res) +{ + return res->cpp_id; +} + +/* + * nfp_resource_name() - Return the name of a resource handle + * @res: NFP Resource handle + * + * Return: const char pointer to the name of the resource + */ +const char +*nfp_resource_name(const struct nfp_resource *res) +{ + return res->name; +} + +/* + * nfp_resource_address() - Return the address of a resource handle + * @res: NFP Resource handle + * + * Return: Address of the resource + */ +uint64_t +nfp_resource_address(const struct nfp_resource *res) +{ + return res->addr; +} + +/* + * nfp_resource_size() - Return the size in bytes of a resource handle + * @res: NFP Resource handle + * + * Return: Size of the resource in bytes + */ +uint64_t +nfp_resource_size(const struct nfp_resource *res) +{ + return res->size; +} diff --git a/drivers/net/nfp/nfpcore/nfp_resource.h b/drivers/net/nfp/nfpcore/nfp_resource.h new file mode 100644 index 00000000..06cc6f74 --- /dev/null +++ b/drivers/net/nfp/nfpcore/nfp_resource.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2018 Netronome Systems, Inc. + * All rights reserved. + */ + +#ifndef NFP_RESOURCE_H +#define NFP_RESOURCE_H + +#include "nfp_cpp.h" + +#define NFP_RESOURCE_NFP_NFFW "nfp.nffw" +#define NFP_RESOURCE_NFP_HWINFO "nfp.info" +#define NFP_RESOURCE_NSP "nfp.sp" + +/** + * Opaque handle to a NFP Resource + */ +struct nfp_resource; + +struct nfp_resource *nfp_resource_acquire(struct nfp_cpp *cpp, + const char *name); + +/** + * Release a NFP Resource, and free the handle + * @param[in] res NFP Resource handle + */ +void nfp_resource_release(struct nfp_resource *res); + +/** + * Return the CPP ID of a NFP Resource + * @param[in] res NFP Resource handle + * @return CPP ID of the NFP Resource + */ +uint32_t nfp_resource_cpp_id(const struct nfp_resource *res); + +/** + * Return the name of a NFP Resource + * @param[in] res NFP Resource handle + * @return Name of the NFP Resource + */ +const char *nfp_resource_name(const struct nfp_resource *res); + +/** + * Return the target address of a NFP Resource + * @param[in] res NFP Resource handle + * @return Address of the NFP Resource + */ +uint64_t nfp_resource_address(const struct nfp_resource *res); + +uint64_t nfp_resource_size(const struct nfp_resource *res); + +#endif /* NFP_RESOURCE_H */ diff --git a/drivers/net/nfp/nfpcore/nfp_rtsym.c b/drivers/net/nfp/nfpcore/nfp_rtsym.c new file mode 100644 index 00000000..cb7d83db --- /dev/null +++ b/drivers/net/nfp/nfpcore/nfp_rtsym.c @@ -0,0 +1,327 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2018 Netronome Systems, Inc. + * All rights reserved. + */ + +/* + * nfp_rtsym.c + * Interface for accessing run-time symbol table + */ + +#include <stdio.h> +#include <rte_byteorder.h> +#include "nfp_cpp.h" +#include "nfp_mip.h" +#include "nfp_rtsym.h" +#include "nfp6000/nfp6000.h" + +/* These need to match the linker */ +#define SYM_TGT_LMEM 0 +#define SYM_TGT_EMU_CACHE 0x17 + +struct nfp_rtsym_entry { + uint8_t type; + uint8_t target; + uint8_t island; + uint8_t addr_hi; + uint32_t addr_lo; + uint16_t name; + uint8_t menum; + uint8_t size_hi; + uint32_t size_lo; +}; + +struct nfp_rtsym_table { + struct nfp_cpp *cpp; + int num; + char *strtab; + struct nfp_rtsym symtab[]; +}; + +static int +nfp_meid(uint8_t island_id, uint8_t menum) +{ + return (island_id & 0x3F) == island_id && menum < 12 ? + (island_id << 4) | (menum + 4) : -1; +} + +static void +nfp_rtsym_sw_entry_init(struct nfp_rtsym_table *cache, uint32_t strtab_size, + struct nfp_rtsym *sw, struct nfp_rtsym_entry *fw) +{ + sw->type = fw->type; + sw->name = cache->strtab + rte_le_to_cpu_16(fw->name) % strtab_size; + sw->addr = ((uint64_t)fw->addr_hi << 32) | + rte_le_to_cpu_32(fw->addr_lo); + sw->size = ((uint64_t)fw->size_hi << 32) | + rte_le_to_cpu_32(fw->size_lo); + +#ifdef DEBUG + printf("rtsym_entry_init\n"); + printf("\tname=%s, addr=%" PRIx64 ", size=%" PRIu64 ",target=%d\n", + sw->name, sw->addr, sw->size, sw->target); +#endif + switch (fw->target) { + case SYM_TGT_LMEM: + sw->target = NFP_RTSYM_TARGET_LMEM; + break; + case SYM_TGT_EMU_CACHE: + sw->target = NFP_RTSYM_TARGET_EMU_CACHE; + break; + default: + sw->target = fw->target; + break; + } + + if (fw->menum != 0xff) + sw->domain = nfp_meid(fw->island, fw->menum); + else if (fw->island != 0xff) + sw->domain = fw->island; + else + sw->domain = -1; +} + +struct nfp_rtsym_table * +nfp_rtsym_table_read(struct nfp_cpp *cpp) +{ + struct nfp_rtsym_table *rtbl; + struct nfp_mip *mip; + + mip = nfp_mip_open(cpp); + rtbl = __nfp_rtsym_table_read(cpp, mip); + nfp_mip_close(mip); + + return rtbl; +} + +/* + * This looks more complex than it should be. But we need to get the type for + * the ~ right in round_down (it needs to be as wide as the result!), and we + * want to evaluate the macro arguments just once each. + */ +#define __round_mask(x, y) ((__typeof__(x))((y) - 1)) + +#define round_up(x, y) \ + (__extension__ ({ \ + typeof(x) _x = (x); \ + ((((_x) - 1) | __round_mask(_x, y)) + 1); \ + })) + +#define round_down(x, y) \ + (__extension__ ({ \ + typeof(x) _x = (x); \ + ((_x) & ~__round_mask(_x, y)); \ + })) + +struct nfp_rtsym_table * +__nfp_rtsym_table_read(struct nfp_cpp *cpp, const struct nfp_mip *mip) +{ + uint32_t strtab_addr, symtab_addr, strtab_size, symtab_size; + struct nfp_rtsym_entry *rtsymtab; + struct nfp_rtsym_table *cache; + const uint32_t dram = + NFP_CPP_ID(NFP_CPP_TARGET_MU, NFP_CPP_ACTION_RW, 0) | + NFP_ISL_EMEM0; + int err, n, size; + + if (!mip) + return NULL; + + nfp_mip_strtab(mip, &strtab_addr, &strtab_size); + nfp_mip_symtab(mip, &symtab_addr, &symtab_size); + + if (!symtab_size || !strtab_size || symtab_size % sizeof(*rtsymtab)) + return NULL; + + /* Align to 64 bits */ + symtab_size = round_up(symtab_size, 8); + strtab_size = round_up(strtab_size, 8); + + rtsymtab = malloc(symtab_size); + if (!rtsymtab) + return NULL; + + size = sizeof(*cache); + size += symtab_size / sizeof(*rtsymtab) * sizeof(struct nfp_rtsym); + size += strtab_size + 1; + cache = malloc(size); + if (!cache) + goto exit_free_rtsym_raw; + + cache->cpp = cpp; + cache->num = symtab_size / sizeof(*rtsymtab); + cache->strtab = (void *)&cache->symtab[cache->num]; + + err = nfp_cpp_read(cpp, dram, symtab_addr, rtsymtab, symtab_size); + if (err != (int)symtab_size) + goto exit_free_cache; + + err = nfp_cpp_read(cpp, dram, strtab_addr, cache->strtab, strtab_size); + if (err != (int)strtab_size) + goto exit_free_cache; + cache->strtab[strtab_size] = '\0'; + + for (n = 0; n < cache->num; n++) + nfp_rtsym_sw_entry_init(cache, strtab_size, + &cache->symtab[n], &rtsymtab[n]); + + free(rtsymtab); + + return cache; + +exit_free_cache: + free(cache); +exit_free_rtsym_raw: + free(rtsymtab); + return NULL; +} + +/* + * nfp_rtsym_count() - Get the number of RTSYM descriptors + * @rtbl: NFP RTsym table + * + * Return: Number of RTSYM descriptors + */ +int +nfp_rtsym_count(struct nfp_rtsym_table *rtbl) +{ + if (!rtbl) + return -EINVAL; + + return rtbl->num; +} + +/* + * nfp_rtsym_get() - Get the Nth RTSYM descriptor + * @rtbl: NFP RTsym table + * @idx: Index (0-based) of the RTSYM descriptor + * + * Return: const pointer to a struct nfp_rtsym descriptor, or NULL + */ +const struct nfp_rtsym * +nfp_rtsym_get(struct nfp_rtsym_table *rtbl, int idx) +{ + if (!rtbl) + return NULL; + + if (idx >= rtbl->num) + return NULL; + + return &rtbl->symtab[idx]; +} + +/* + * nfp_rtsym_lookup() - Return the RTSYM descriptor for a symbol name + * @rtbl: NFP RTsym table + * @name: Symbol name + * + * Return: const pointer to a struct nfp_rtsym descriptor, or NULL + */ +const struct nfp_rtsym * +nfp_rtsym_lookup(struct nfp_rtsym_table *rtbl, const char *name) +{ + int n; + + if (!rtbl) + return NULL; + + for (n = 0; n < rtbl->num; n++) + if (strcmp(name, rtbl->symtab[n].name) == 0) + return &rtbl->symtab[n]; + + return NULL; +} + +/* + * nfp_rtsym_read_le() - Read a simple unsigned scalar value from symbol + * @rtbl: NFP RTsym table + * @name: Symbol name + * @error: Poniter to error code (optional) + * + * Lookup a symbol, map, read it and return it's value. Value of the symbol + * will be interpreted as a simple little-endian unsigned value. Symbol can + * be 4 or 8 bytes in size. + * + * Return: value read, on error sets the error and returns ~0ULL. + */ +uint64_t +nfp_rtsym_read_le(struct nfp_rtsym_table *rtbl, const char *name, int *error) +{ + const struct nfp_rtsym *sym; + uint32_t val32, id; + uint64_t val; + int err; + + sym = nfp_rtsym_lookup(rtbl, name); + if (!sym) { + err = -ENOENT; + goto exit; + } + + id = NFP_CPP_ISLAND_ID(sym->target, NFP_CPP_ACTION_RW, 0, sym->domain); + +#ifdef DEBUG + printf("Reading symbol %s with size %" PRIu64 " at %" PRIx64 "\n", + name, sym->size, sym->addr); +#endif + switch (sym->size) { + case 4: + err = nfp_cpp_readl(rtbl->cpp, id, sym->addr, &val32); + val = val32; + break; + case 8: + err = nfp_cpp_readq(rtbl->cpp, id, sym->addr, &val); + break; + default: + printf("rtsym '%s' unsupported size: %" PRId64 "\n", + name, sym->size); + err = -EINVAL; + break; + } + + if (err) + err = -EIO; +exit: + if (error) + *error = err; + + if (err) + return ~0ULL; + + return val; +} + +uint8_t * +nfp_rtsym_map(struct nfp_rtsym_table *rtbl, const char *name, + unsigned int min_size, struct nfp_cpp_area **area) +{ + const struct nfp_rtsym *sym; + uint8_t *mem; + +#ifdef DEBUG + printf("mapping symbol %s\n", name); +#endif + sym = nfp_rtsym_lookup(rtbl, name); + if (!sym) { + printf("symbol lookup fails for %s\n", name); + return NULL; + } + + if (sym->size < min_size) { + printf("Symbol %s too small (%" PRIu64 " < %u)\n", name, + sym->size, min_size); + return NULL; + } + + mem = nfp_cpp_map_area(rtbl->cpp, sym->domain, sym->target, sym->addr, + sym->size, area); + if (!mem) { + printf("Failed to map symbol %s\n", name); + return NULL; + } +#ifdef DEBUG + printf("symbol %s with address %p\n", name, mem); +#endif + + return mem; +} diff --git a/drivers/net/nfp/nfpcore/nfp_rtsym.h b/drivers/net/nfp/nfpcore/nfp_rtsym.h new file mode 100644 index 00000000..8b494211 --- /dev/null +++ b/drivers/net/nfp/nfpcore/nfp_rtsym.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2018 Netronome Systems, Inc. + * All rights reserved. + */ + +#ifndef __NFP_RTSYM_H__ +#define __NFP_RTSYM_H__ + +#define NFP_RTSYM_TYPE_NONE 0 +#define NFP_RTSYM_TYPE_OBJECT 1 +#define NFP_RTSYM_TYPE_FUNCTION 2 +#define NFP_RTSYM_TYPE_ABS 3 + +#define NFP_RTSYM_TARGET_NONE 0 +#define NFP_RTSYM_TARGET_LMEM -1 +#define NFP_RTSYM_TARGET_EMU_CACHE -7 + +/* + * Structure describing a run-time NFP symbol. + * + * The memory target of the symbol is generally the CPP target number and can be + * used directly by the nfp_cpp API calls. However, in some cases (i.e., for + * local memory or control store) the target is encoded using a negative number. + * + * When the target type can not be used to fully describe the location of a + * symbol the domain field is used to further specify the location (i.e., the + * specific ME or island number). + * + * For ME target resources, 'domain' is an MEID. + * For Island target resources, 'domain' is an island ID, with the one exception + * of "sram" symbols for backward compatibility, which are viewed as global. + */ +struct nfp_rtsym { + const char *name; + uint64_t addr; + uint64_t size; + int type; + int target; + int domain; +}; + +struct nfp_rtsym_table; + +struct nfp_rtsym_table *nfp_rtsym_table_read(struct nfp_cpp *cpp); + +struct nfp_rtsym_table * +__nfp_rtsym_table_read(struct nfp_cpp *cpp, const struct nfp_mip *mip); + +int nfp_rtsym_count(struct nfp_rtsym_table *rtbl); + +const struct nfp_rtsym *nfp_rtsym_get(struct nfp_rtsym_table *rtbl, int idx); + +const struct nfp_rtsym * +nfp_rtsym_lookup(struct nfp_rtsym_table *rtbl, const char *name); + +uint64_t nfp_rtsym_read_le(struct nfp_rtsym_table *rtbl, const char *name, + int *error); +uint8_t * +nfp_rtsym_map(struct nfp_rtsym_table *rtbl, const char *name, + unsigned int min_size, struct nfp_cpp_area **area); +#endif diff --git a/drivers/net/nfp/nfpcore/nfp_target.h b/drivers/net/nfp/nfpcore/nfp_target.h new file mode 100644 index 00000000..2884a003 --- /dev/null +++ b/drivers/net/nfp/nfpcore/nfp_target.h @@ -0,0 +1,579 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2018 Netronome Systems, Inc. + * All rights reserved. + */ + +#ifndef NFP_TARGET_H +#define NFP_TARGET_H + +#include "nfp-common/nfp_resid.h" +#include "nfp-common/nfp_cppat.h" +#include "nfp-common/nfp_platform.h" +#include "nfp_cpp.h" + +#define P32 1 +#define P64 2 + +#define PUSHPULL(_pull, _push) (((_pull) << 4) | ((_push) << 0)) + +#ifndef NFP_ERRNO +#include <errno.h> +#define NFP_ERRNO(x) (errno = (x), -1) +#endif + +static inline int +pushpull_width(int pp) +{ + pp &= 0xf; + + if (pp == 0) + return NFP_ERRNO(EINVAL); + return (2 << pp); +} + +#define PUSH_WIDTH(_pushpull) pushpull_width((_pushpull) >> 0) +#define PULL_WIDTH(_pushpull) pushpull_width((_pushpull) >> 4) + +static inline int +target_rw(uint32_t cpp_id, int pp, int start, int len) +{ + int island = NFP_CPP_ID_ISLAND_of(cpp_id); + + if (island && (island < start || island > (start + len))) + return NFP_ERRNO(EINVAL); + + switch (cpp_id & NFP_CPP_ID(0, ~0, ~0)) { + case NFP_CPP_ID(0, 0, 0): + return PUSHPULL(0, pp); + case NFP_CPP_ID(0, 1, 0): + return PUSHPULL(pp, 0); + case NFP_CPP_ID(0, NFP_CPP_ACTION_RW, 0): + return PUSHPULL(pp, pp); + default: + return NFP_ERRNO(EINVAL); + } +} + +static inline int +nfp6000_nbi_dma(uint32_t cpp_id) +{ + switch (cpp_id & NFP_CPP_ID(0, ~0, ~0)) { + case NFP_CPP_ID(0, 0, 0): /* ReadNbiDma */ + return PUSHPULL(0, P64); + case NFP_CPP_ID(0, 1, 0): /* WriteNbiDma */ + return PUSHPULL(P64, 0); + case NFP_CPP_ID(0, NFP_CPP_ACTION_RW, 0): + return PUSHPULL(P64, P64); + default: + return NFP_ERRNO(EINVAL); + } +} + +static inline int +nfp6000_nbi_stats(uint32_t cpp_id) +{ + switch (cpp_id & NFP_CPP_ID(0, ~0, ~0)) { + case NFP_CPP_ID(0, 0, 0): /* ReadNbiStats */ + return PUSHPULL(0, P64); + case NFP_CPP_ID(0, 1, 0): /* WriteNbiStats */ + return PUSHPULL(P64, 0); + case NFP_CPP_ID(0, NFP_CPP_ACTION_RW, 0): + return PUSHPULL(P64, P64); + default: + return NFP_ERRNO(EINVAL); + } +} + +static inline int +nfp6000_nbi_tm(uint32_t cpp_id) +{ + switch (cpp_id & NFP_CPP_ID(0, ~0, ~0)) { + case NFP_CPP_ID(0, 0, 0): /* ReadNbiTM */ + return PUSHPULL(0, P64); + case NFP_CPP_ID(0, 1, 0): /* WriteNbiTM */ + return PUSHPULL(P64, 0); + case NFP_CPP_ID(0, NFP_CPP_ACTION_RW, 0): + return PUSHPULL(P64, P64); + default: + return NFP_ERRNO(EINVAL); + } +} + +static inline int +nfp6000_nbi_ppc(uint32_t cpp_id) +{ + switch (cpp_id & NFP_CPP_ID(0, ~0, ~0)) { + case NFP_CPP_ID(0, 0, 0): /* ReadNbiPreclassifier */ + return PUSHPULL(0, P64); + case NFP_CPP_ID(0, 1, 0): /* WriteNbiPreclassifier */ + return PUSHPULL(P64, 0); + case NFP_CPP_ID(0, NFP_CPP_ACTION_RW, 0): + return PUSHPULL(P64, P64); + default: + return NFP_ERRNO(EINVAL); + } +} + +static inline int +nfp6000_nbi(uint32_t cpp_id, uint64_t address) +{ + int island = NFP_CPP_ID_ISLAND_of(cpp_id); + uint64_t rel_addr = address & 0x3fFFFF; + + if (island && (island < 8 || island > 9)) + return NFP_ERRNO(EINVAL); + + if (rel_addr < (1 << 20)) + return nfp6000_nbi_dma(cpp_id); + if (rel_addr < (2 << 20)) + return nfp6000_nbi_stats(cpp_id); + if (rel_addr < (3 << 20)) + return nfp6000_nbi_tm(cpp_id); + return nfp6000_nbi_ppc(cpp_id); +} + +/* + * This structure ONLY includes items that can be done with a read or write of + * 32-bit or 64-bit words. All others are not listed. + */ +static inline int +nfp6000_mu_common(uint32_t cpp_id) +{ + switch (cpp_id & NFP_CPP_ID(0, ~0, ~0)) { + case NFP_CPP_ID(0, NFP_CPP_ACTION_RW, 0): /* read_be/write_be */ + return PUSHPULL(P64, P64); + case NFP_CPP_ID(0, NFP_CPP_ACTION_RW, 1): /* read_le/write_le */ + return PUSHPULL(P64, P64); + case NFP_CPP_ID(0, NFP_CPP_ACTION_RW, 2): /* {read/write}_swap_be */ + return PUSHPULL(P64, P64); + case NFP_CPP_ID(0, NFP_CPP_ACTION_RW, 3): /* {read/write}_swap_le */ + return PUSHPULL(P64, P64); + case NFP_CPP_ID(0, 0, 0): /* read_be */ + return PUSHPULL(0, P64); + case NFP_CPP_ID(0, 0, 1): /* read_le */ + return PUSHPULL(0, P64); + case NFP_CPP_ID(0, 0, 2): /* read_swap_be */ + return PUSHPULL(0, P64); + case NFP_CPP_ID(0, 0, 3): /* read_swap_le */ + return PUSHPULL(0, P64); + case NFP_CPP_ID(0, 1, 0): /* write_be */ + return PUSHPULL(P64, 0); + case NFP_CPP_ID(0, 1, 1): /* write_le */ + return PUSHPULL(P64, 0); + case NFP_CPP_ID(0, 1, 2): /* write_swap_be */ + return PUSHPULL(P64, 0); + case NFP_CPP_ID(0, 1, 3): /* write_swap_le */ + return PUSHPULL(P64, 0); + case NFP_CPP_ID(0, 3, 0): /* atomic_read */ + return PUSHPULL(0, P32); + case NFP_CPP_ID(0, 3, 2): /* mask_compare_write */ + return PUSHPULL(P32, 0); + case NFP_CPP_ID(0, 4, 0): /* atomic_write */ + return PUSHPULL(P32, 0); + case NFP_CPP_ID(0, 4, 2): /* atomic_write_imm */ + return PUSHPULL(0, 0); + case NFP_CPP_ID(0, 4, 3): /* swap_imm */ + return PUSHPULL(0, P32); + case NFP_CPP_ID(0, 5, 0): /* set */ + return PUSHPULL(P32, 0); + case NFP_CPP_ID(0, 5, 3): /* test_set_imm */ + return PUSHPULL(0, P32); + case NFP_CPP_ID(0, 6, 0): /* clr */ + return PUSHPULL(P32, 0); + case NFP_CPP_ID(0, 6, 3): /* test_clr_imm */ + return PUSHPULL(0, P32); + case NFP_CPP_ID(0, 7, 0): /* add */ + return PUSHPULL(P32, 0); + case NFP_CPP_ID(0, 7, 3): /* test_add_imm */ + return PUSHPULL(0, P32); + case NFP_CPP_ID(0, 8, 0): /* addsat */ + return PUSHPULL(P32, 0); + case NFP_CPP_ID(0, 8, 3): /* test_subsat_imm */ + return PUSHPULL(0, P32); + case NFP_CPP_ID(0, 9, 0): /* sub */ + return PUSHPULL(P32, 0); + case NFP_CPP_ID(0, 9, 3): /* test_sub_imm */ + return PUSHPULL(0, P32); + case NFP_CPP_ID(0, 10, 0): /* subsat */ + return PUSHPULL(P32, 0); + case NFP_CPP_ID(0, 10, 3): /* test_subsat_imm */ + return PUSHPULL(0, P32); + case NFP_CPP_ID(0, 13, 0): /* microq128_get */ + return PUSHPULL(0, P32); + case NFP_CPP_ID(0, 13, 1): /* microq128_pop */ + return PUSHPULL(0, P32); + case NFP_CPP_ID(0, 13, 2): /* microq128_put */ + return PUSHPULL(P32, 0); + case NFP_CPP_ID(0, 15, 0): /* xor */ + return PUSHPULL(P32, 0); + case NFP_CPP_ID(0, 15, 3): /* test_xor_imm */ + return PUSHPULL(0, P32); + case NFP_CPP_ID(0, 28, 0): /* read32_be */ + return PUSHPULL(0, P32); + case NFP_CPP_ID(0, 28, 1): /* read32_le */ + return PUSHPULL(0, P32); + case NFP_CPP_ID(0, 28, 2): /* read32_swap_be */ + return PUSHPULL(0, P32); + case NFP_CPP_ID(0, 28, 3): /* read32_swap_le */ + return PUSHPULL(0, P32); + case NFP_CPP_ID(0, 31, 0): /* write32_be */ + return PUSHPULL(P32, 0); + case NFP_CPP_ID(0, 31, 1): /* write32_le */ + return PUSHPULL(P32, 0); + case NFP_CPP_ID(0, 31, 2): /* write32_swap_be */ + return PUSHPULL(P32, 0); + case NFP_CPP_ID(0, 31, 3): /* write32_swap_le */ + return PUSHPULL(P32, 0); + default: + return NFP_ERRNO(EINVAL); + } +} + +static inline int +nfp6000_mu_ctm(uint32_t cpp_id) +{ + switch (cpp_id & NFP_CPP_ID(0, ~0, ~0)) { + case NFP_CPP_ID(0, 16, 1): /* packet_read_packet_status */ + return PUSHPULL(0, P32); + default: + return nfp6000_mu_common(cpp_id); + } +} + +static inline int +nfp6000_mu_emu(uint32_t cpp_id) +{ + switch (cpp_id & NFP_CPP_ID(0, ~0, ~0)) { + case NFP_CPP_ID(0, 18, 0): /* read_queue */ + return PUSHPULL(0, P32); + case NFP_CPP_ID(0, 18, 1): /* read_queue_ring */ + return PUSHPULL(0, P32); + case NFP_CPP_ID(0, 18, 2): /* write_queue */ + return PUSHPULL(P32, 0); + case NFP_CPP_ID(0, 18, 3): /* write_queue_ring */ + return PUSHPULL(P32, 0); + case NFP_CPP_ID(0, 20, 2): /* journal */ + return PUSHPULL(P32, 0); + case NFP_CPP_ID(0, 21, 0): /* get */ + return PUSHPULL(0, P32); + case NFP_CPP_ID(0, 21, 1): /* get_eop */ + return PUSHPULL(0, P32); + case NFP_CPP_ID(0, 21, 2): /* get_freely */ + return PUSHPULL(0, P32); + case NFP_CPP_ID(0, 22, 0): /* pop */ + return PUSHPULL(0, P32); + case NFP_CPP_ID(0, 22, 1): /* pop_eop */ + return PUSHPULL(0, P32); + case NFP_CPP_ID(0, 22, 2): /* pop_freely */ + return PUSHPULL(0, P32); + default: + return nfp6000_mu_common(cpp_id); + } +} + +static inline int +nfp6000_mu_imu(uint32_t cpp_id) +{ + return nfp6000_mu_common(cpp_id); +} + +static inline int +nfp6000_mu(uint32_t cpp_id, uint64_t address) +{ + int pp; + int island = NFP_CPP_ID_ISLAND_of(cpp_id); + + if (island == 0) { + if (address < 0x2000000000ULL) + pp = nfp6000_mu_ctm(cpp_id); + else if (address < 0x8000000000ULL) + pp = nfp6000_mu_emu(cpp_id); + else if (address < 0x9800000000ULL) + pp = nfp6000_mu_ctm(cpp_id); + else if (address < 0x9C00000000ULL) + pp = nfp6000_mu_emu(cpp_id); + else if (address < 0xA000000000ULL) + pp = nfp6000_mu_imu(cpp_id); + else + pp = nfp6000_mu_ctm(cpp_id); + } else if (island >= 24 && island <= 27) { + pp = nfp6000_mu_emu(cpp_id); + } else if (island >= 28 && island <= 31) { + pp = nfp6000_mu_imu(cpp_id); + } else if (island == 1 || + (island >= 4 && island <= 7) || + (island >= 12 && island <= 13) || + (island >= 32 && island <= 47) || + (island >= 48 && island <= 51)) { + pp = nfp6000_mu_ctm(cpp_id); + } else { + pp = NFP_ERRNO(EINVAL); + } + + return pp; +} + +static inline int +nfp6000_ila(uint32_t cpp_id) +{ + int island = NFP_CPP_ID_ISLAND_of(cpp_id); + + if (island && (island < 48 || island > 51)) + return NFP_ERRNO(EINVAL); + + switch (cpp_id & NFP_CPP_ID(0, ~0, ~0)) { + case NFP_CPP_ID(0, 0, 1): /* read_check_error */ + return PUSHPULL(0, P32); + case NFP_CPP_ID(0, 2, 0): /* read_int */ + return PUSHPULL(0, P32); + case NFP_CPP_ID(0, 3, 0): /* write_int */ + return PUSHPULL(P32, 0); + default: + return target_rw(cpp_id, P32, 48, 4); + } +} + +static inline int +nfp6000_pci(uint32_t cpp_id) +{ + int island = NFP_CPP_ID_ISLAND_of(cpp_id); + + if (island && (island < 4 || island > 7)) + return NFP_ERRNO(EINVAL); + + switch (cpp_id & NFP_CPP_ID(0, ~0, ~0)) { + case NFP_CPP_ID(0, 2, 0): + return PUSHPULL(0, P32); + case NFP_CPP_ID(0, 3, 0): + return PUSHPULL(P32, 0); + default: + return target_rw(cpp_id, P32, 4, 4); + } +} + +static inline int +nfp6000_crypto(uint32_t cpp_id) +{ + int island = NFP_CPP_ID_ISLAND_of(cpp_id); + + if (island && (island < 12 || island > 15)) + return NFP_ERRNO(EINVAL); + + switch (cpp_id & NFP_CPP_ID(0, ~0, ~0)) { + case NFP_CPP_ID(0, 2, 0): + return PUSHPULL(P64, 0); + default: + return target_rw(cpp_id, P64, 12, 4); + } +} + +static inline int +nfp6000_cap_xpb(uint32_t cpp_id) +{ + int island = NFP_CPP_ID_ISLAND_of(cpp_id); + + if (island && (island < 1 || island > 63)) + return NFP_ERRNO(EINVAL); + + switch (cpp_id & NFP_CPP_ID(0, ~0, ~0)) { + case NFP_CPP_ID(0, 0, 1): /* RingGet */ + return PUSHPULL(0, P32); + case NFP_CPP_ID(0, 0, 2): /* Interthread Signal */ + return PUSHPULL(P32, 0); + case NFP_CPP_ID(0, 1, 1): /* RingPut */ + return PUSHPULL(P32, 0); + case NFP_CPP_ID(0, 1, 2): /* CTNNWr */ + return PUSHPULL(P32, 0); + case NFP_CPP_ID(0, 2, 0): /* ReflectRd, signal none */ + return PUSHPULL(0, P32); + case NFP_CPP_ID(0, 2, 1): /* ReflectRd, signal self */ + return PUSHPULL(0, P32); + case NFP_CPP_ID(0, 2, 2): /* ReflectRd, signal remote */ + return PUSHPULL(0, P32); + case NFP_CPP_ID(0, 2, 3): /* ReflectRd, signal both */ + return PUSHPULL(0, P32); + case NFP_CPP_ID(0, 3, 0): /* ReflectWr, signal none */ + return PUSHPULL(P32, 0); + case NFP_CPP_ID(0, 3, 1): /* ReflectWr, signal self */ + return PUSHPULL(P32, 0); + case NFP_CPP_ID(0, 3, 2): /* ReflectWr, signal remote */ + return PUSHPULL(P32, 0); + case NFP_CPP_ID(0, 3, 3): /* ReflectWr, signal both */ + return PUSHPULL(P32, 0); + case NFP_CPP_ID(0, NFP_CPP_ACTION_RW, 1): + return PUSHPULL(P32, P32); + default: + return target_rw(cpp_id, P32, 1, 63); + } +} + +static inline int +nfp6000_cls(uint32_t cpp_id) +{ + int island = NFP_CPP_ID_ISLAND_of(cpp_id); + + if (island && (island < 1 || island > 63)) + return NFP_ERRNO(EINVAL); + + switch (cpp_id & NFP_CPP_ID(0, ~0, ~0)) { + case NFP_CPP_ID(0, 0, 3): /* xor */ + return PUSHPULL(P32, 0); + case NFP_CPP_ID(0, 2, 0): /* set */ + return PUSHPULL(P32, 0); + case NFP_CPP_ID(0, 2, 1): /* clr */ + return PUSHPULL(P32, 0); + case NFP_CPP_ID(0, 4, 0): /* add */ + return PUSHPULL(P32, 0); + case NFP_CPP_ID(0, 4, 1): /* add64 */ + return PUSHPULL(P32, 0); + case NFP_CPP_ID(0, 6, 0): /* sub */ + return PUSHPULL(P32, 0); + case NFP_CPP_ID(0, 6, 1): /* sub64 */ + return PUSHPULL(P32, 0); + case NFP_CPP_ID(0, 6, 2): /* subsat */ + return PUSHPULL(P32, 0); + case NFP_CPP_ID(0, 8, 2): /* hash_mask */ + return PUSHPULL(P32, 0); + case NFP_CPP_ID(0, 8, 3): /* hash_clear */ + return PUSHPULL(P32, 0); + case NFP_CPP_ID(0, 9, 0): /* ring_get */ + return PUSHPULL(0, P32); + case NFP_CPP_ID(0, 9, 1): /* ring_pop */ + return PUSHPULL(0, P32); + case NFP_CPP_ID(0, 9, 2): /* ring_get_freely */ + return PUSHPULL(0, P32); + case NFP_CPP_ID(0, 9, 3): /* ring_pop_freely */ + return PUSHPULL(0, P32); + case NFP_CPP_ID(0, 10, 0): /* ring_put */ + return PUSHPULL(P32, 0); + case NFP_CPP_ID(0, 10, 2): /* ring_journal */ + return PUSHPULL(P32, 0); + case NFP_CPP_ID(0, 14, 0): /* reflect_write_sig_local */ + return PUSHPULL(P32, 0); + case NFP_CPP_ID(0, 15, 1): /* reflect_read_sig_local */ + return PUSHPULL(0, P32); + case NFP_CPP_ID(0, 17, 2): /* statistic */ + return PUSHPULL(P32, 0); + case NFP_CPP_ID(0, 24, 0): /* ring_read */ + return PUSHPULL(0, P32); + case NFP_CPP_ID(0, 24, 1): /* ring_write */ + return PUSHPULL(P32, 0); + case NFP_CPP_ID(0, 25, 0): /* ring_workq_add_thread */ + return PUSHPULL(0, P32); + case NFP_CPP_ID(0, 25, 1): /* ring_workq_add_work */ + return PUSHPULL(P32, 0); + default: + return target_rw(cpp_id, P32, 0, 64); + } +} + +static inline int +nfp6000_target_pushpull(uint32_t cpp_id, uint64_t address) +{ + switch (NFP_CPP_ID_TARGET_of(cpp_id)) { + case NFP6000_CPPTGT_NBI: + return nfp6000_nbi(cpp_id, address); + case NFP6000_CPPTGT_VQDR: + return target_rw(cpp_id, P32, 24, 4); + case NFP6000_CPPTGT_ILA: + return nfp6000_ila(cpp_id); + case NFP6000_CPPTGT_MU: + return nfp6000_mu(cpp_id, address); + case NFP6000_CPPTGT_PCIE: + return nfp6000_pci(cpp_id); + case NFP6000_CPPTGT_ARM: + if (address < 0x10000) + return target_rw(cpp_id, P64, 1, 1); + else + return target_rw(cpp_id, P32, 1, 1); + case NFP6000_CPPTGT_CRYPTO: + return nfp6000_crypto(cpp_id); + case NFP6000_CPPTGT_CTXPB: + return nfp6000_cap_xpb(cpp_id); + case NFP6000_CPPTGT_CLS: + return nfp6000_cls(cpp_id); + case 0: + return target_rw(cpp_id, P32, 4, 4); + default: + return NFP_ERRNO(EINVAL); + } +} + +static inline int +nfp_target_pushpull_width(int pp, int write_not_read) +{ + if (pp < 0) + return pp; + + if (write_not_read) + return PULL_WIDTH(pp); + else + return PUSH_WIDTH(pp); +} + +static inline int +nfp6000_target_action_width(uint32_t cpp_id, uint64_t address, + int write_not_read) +{ + int pp; + + pp = nfp6000_target_pushpull(cpp_id, address); + + return nfp_target_pushpull_width(pp, write_not_read); +} + +static inline int +nfp_target_action_width(uint32_t model, uint32_t cpp_id, uint64_t address, + int write_not_read) +{ + if (NFP_CPP_MODEL_IS_6000(model)) { + return nfp6000_target_action_width(cpp_id, address, + write_not_read); + } else { + return NFP_ERRNO(EINVAL); + } +} + +static inline int +nfp_target_cpp(uint32_t cpp_island_id, uint64_t cpp_island_address, + uint32_t *cpp_target_id, uint64_t *cpp_target_address, + const uint32_t *imb_table) +{ + int err; + int island = NFP_CPP_ID_ISLAND_of(cpp_island_id); + int target = NFP_CPP_ID_TARGET_of(cpp_island_id); + uint32_t imb; + + if (target < 0 || target >= 16) + return NFP_ERRNO(EINVAL); + + if (island == 0) { + /* Already translated */ + *cpp_target_id = cpp_island_id; + *cpp_target_address = cpp_island_address; + return 0; + } + + if (!imb_table) { + /* CPP + Island only allowed on systems with IMB tables */ + return NFP_ERRNO(EINVAL); + } + + imb = imb_table[target]; + + *cpp_target_address = cpp_island_address; + err = _nfp6000_cppat_addr_encode(cpp_target_address, island, target, + ((imb >> 13) & 7), + ((imb >> 12) & 1), + ((imb >> 6) & 0x3f), + ((imb >> 0) & 0x3f)); + if (err == 0) { + *cpp_target_id = + NFP_CPP_ID(target, NFP_CPP_ID_ACTION_of(cpp_island_id), + NFP_CPP_ID_TOKEN_of(cpp_island_id)); + } + + return err; +} + +#endif /* NFP_TARGET_H */ |