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-rw-r--r--drivers/net/nfp/Makefile5
-rw-r--r--drivers/net/nfp/nfp_net.c602
-rw-r--r--drivers/net/nfp/nfp_net_ctrl.h10
-rw-r--r--drivers/net/nfp/nfp_net_eth.h82
-rw-r--r--drivers/net/nfp/nfp_net_pmd.h15
-rw-r--r--drivers/net/nfp/nfp_nfpu.c103
-rw-r--r--drivers/net/nfp/nfp_nfpu.h55
-rw-r--r--drivers/net/nfp/nfp_nspu.c623
-rw-r--r--drivers/net/nfp/nfp_nspu.h83
9 files changed, 1501 insertions, 77 deletions
diff --git a/drivers/net/nfp/Makefile b/drivers/net/nfp/Makefile
index 4ee2c2dc..4ba066ac 100644
--- a/drivers/net/nfp/Makefile
+++ b/drivers/net/nfp/Makefile
@@ -40,6 +40,9 @@ CFLAGS += -O3
CFLAGS += $(WERROR_FLAGS)
LDLIBS += -lm
+LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool -lrte_ring
+LDLIBS += -lrte_ethdev -lrte_net -lrte_kvargs
+LDLIBS += -lrte_bus_pci
EXPORT_MAP := rte_pmd_nfp_version.map
@@ -49,5 +52,7 @@ LIBABIVER := 1
# all source are stored in SRCS-y
#
SRCS-$(CONFIG_RTE_LIBRTE_NFP_PMD) += nfp_net.c
+SRCS-$(CONFIG_RTE_LIBRTE_NFP_PMD) += nfp_nfpu.c
+SRCS-$(CONFIG_RTE_LIBRTE_NFP_PMD) += nfp_nspu.c
include $(RTE_SDK)/mk/rte.lib.mk
diff --git a/drivers/net/nfp/nfp_net.c b/drivers/net/nfp/nfp_net.c
index 92b03c4c..83dec061 100644
--- a/drivers/net/nfp/nfp_net.c
+++ b/drivers/net/nfp/nfp_net.c
@@ -55,6 +55,7 @@
#include <rte_alarm.h>
#include <rte_spinlock.h>
+#include "nfp_nfpu.h"
#include "nfp_net_pmd.h"
#include "nfp_net_logs.h"
#include "nfp_net_ctrl.h"
@@ -87,7 +88,7 @@ static int nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
uint16_t nb_desc, unsigned int socket_id,
const struct rte_eth_txconf *tx_conf);
static int nfp_net_start(struct rte_eth_dev *dev);
-static void nfp_net_stats_get(struct rte_eth_dev *dev,
+static int nfp_net_stats_get(struct rte_eth_dev *dev,
struct rte_eth_stats *stats);
static void nfp_net_stats_reset(struct rte_eth_dev *dev);
static void nfp_net_stop(struct rte_eth_dev *dev);
@@ -99,13 +100,13 @@ static uint16_t nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
* happen to be at the same offset on the NFP6000 and the NFP3200 so
* we use a single macro here.
*/
-#define NFP_PCIE_QUEUE(_q) (0x80000 + (0x800 * ((_q) & 0xff)))
+#define NFP_PCIE_QUEUE(_q) (0x800 * ((_q) & 0xff))
/* Maximum value which can be added to a queue with one transaction */
#define NFP_QCP_MAX_ADD 0x7f
#define RTE_MBUF_DMA_ADDR_DEFAULT(mb) \
- (uint64_t)((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)
+ (uint64_t)((mb)->buf_iova + RTE_PKTMBUF_HEADROOM)
/* nfp_qcp_ptr - Read or Write Pointer of a queue */
enum nfp_qcp_ptr {
@@ -487,10 +488,6 @@ nfp_net_configure(struct rte_eth_dev *dev)
return -EINVAL;
}
- /* Supporting VLAN insertion by default */
- if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
- new_ctrl |= NFP_NET_CFG_CTRL_TXVLAN;
-
if (rxmode->jumbo_frame)
/* this is handled in rte_eth_dev_configure */
@@ -504,6 +501,32 @@ nfp_net_configure(struct rte_eth_dev *dev)
return -EINVAL;
}
+ /* If next capabilities are supported, configure them by default */
+
+ /* VLAN insertion */
+ if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
+ new_ctrl |= NFP_NET_CFG_CTRL_TXVLAN;
+
+ /* L2 broadcast */
+ if (hw->cap & NFP_NET_CFG_CTRL_L2BC)
+ new_ctrl |= NFP_NET_CFG_CTRL_L2BC;
+
+ /* L2 multicast */
+ if (hw->cap & NFP_NET_CFG_CTRL_L2MC)
+ new_ctrl |= NFP_NET_CFG_CTRL_L2MC;
+
+ /* TX checksum offload */
+ if (hw->cap & NFP_NET_CFG_CTRL_TXCSUM)
+ new_ctrl |= NFP_NET_CFG_CTRL_TXCSUM;
+
+ /* LSO offload */
+ if (hw->cap & NFP_NET_CFG_CTRL_LSO)
+ new_ctrl |= NFP_NET_CFG_CTRL_LSO;
+
+ /* RX gather */
+ if (hw->cap & NFP_NET_CFG_CTRL_GATHER)
+ new_ctrl |= NFP_NET_CFG_CTRL_GATHER;
+
if (!new_ctrl)
return 0;
@@ -592,7 +615,55 @@ nfp_net_cfg_queue_setup(struct nfp_net_hw *hw)
hw->qcp_cfg = hw->tx_bar + NFP_QCP_QUEUE_ADDR_SZ;
}
-static void nfp_net_read_mac(struct nfp_net_hw *hw)
+#define ETH_ADDR_LEN 6
+
+static void
+nfp_eth_copy_mac_reverse(uint8_t *dst, const uint8_t *src)
+{
+ int i;
+
+ for (i = 0; i < ETH_ADDR_LEN; i++)
+ dst[ETH_ADDR_LEN - i - 1] = src[i];
+}
+
+static int
+nfp_net_pf_read_mac(struct nfp_net_hw *hw, int port)
+{
+ union eth_table_entry *entry;
+ int idx, i;
+
+ idx = port;
+ entry = hw->eth_table;
+
+ /* Reading NFP ethernet table obtained before */
+ for (i = 0; i < NSP_ETH_MAX_COUNT; i++) {
+ if (!(entry->port & NSP_ETH_PORT_LANES_MASK)) {
+ /* port not in use */
+ entry++;
+ continue;
+ }
+ if (idx == 0)
+ break;
+ idx--;
+ entry++;
+ }
+
+ if (i == NSP_ETH_MAX_COUNT)
+ return -EINVAL;
+
+ /*
+ * hw points to port0 private data. We need hw now pointing to
+ * right port.
+ */
+ hw += port;
+ nfp_eth_copy_mac_reverse((uint8_t *)&hw->mac_addr,
+ (uint8_t *)&entry->mac_addr);
+
+ return 0;
+}
+
+static void
+nfp_net_vf_read_mac(struct nfp_net_hw *hw)
{
uint32_t tmp;
@@ -603,6 +674,20 @@ static void nfp_net_read_mac(struct nfp_net_hw *hw)
memcpy(&hw->mac_addr[4], &tmp, 2);
}
+static void
+nfp_net_write_mac(struct nfp_net_hw *hw, uint8_t *mac)
+{
+ uint32_t mac0 = *(uint32_t *)mac;
+ uint16_t mac1;
+
+ nn_writel(rte_cpu_to_be_32(mac0), hw->ctrl_bar + NFP_NET_CFG_MACADDR);
+
+ mac += 4;
+ mac1 = *(uint16_t *)mac;
+ nn_writew(rte_cpu_to_be_16(mac1),
+ hw->ctrl_bar + NFP_NET_CFG_MACADDR + 6);
+}
+
static int
nfp_configure_rx_interrupt(struct rte_eth_dev *dev,
struct rte_intr_handle *intr_handle)
@@ -627,14 +712,19 @@ nfp_configure_rx_interrupt(struct rte_eth_dev *dev,
PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with UIO");
/* UIO just supports one queue and no LSC*/
nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(0), 0);
+ intr_handle->intr_vec[0] = 0;
} else {
PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with VFIO");
- for (i = 0; i < dev->data->nb_rx_queues; i++)
+ for (i = 0; i < dev->data->nb_rx_queues; i++) {
/*
* The first msix vector is reserved for non
* efd interrupts
*/
nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(i), i + 1);
+ intr_handle->intr_vec[i] = i + 1;
+ PMD_INIT_LOG(DEBUG, "intr_vec[%d]= %d\n", i,
+ intr_handle->intr_vec[i]);
+ }
}
/* Avoiding TX interrupts */
@@ -667,6 +757,11 @@ nfp_net_start(struct rte_eth_dev *dev)
/* check and configure queue intr-vector mapping */
if (dev->data->dev_conf.intr_conf.rxq != 0) {
+ if (hw->pf_multiport_enabled) {
+ PMD_INIT_LOG(ERR, "PMD rx interrupt is not supported "
+ "with NFP multiport PF");
+ return -EINVAL;
+ }
if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
/*
* Better not to share LSC with RX interrupts.
@@ -684,20 +779,17 @@ nfp_net_start(struct rte_eth_dev *dev)
intr_vector = dev->data->nb_rx_queues;
if (rte_intr_efd_enable(intr_handle, intr_vector))
return -1;
- }
- if (rte_intr_dp_is_en(intr_handle))
nfp_configure_rx_interrupt(dev, intr_handle);
+ update = NFP_NET_CFG_UPDATE_MSIX;
+ }
rte_intr_enable(intr_handle);
/* Enable device */
new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_ENABLE;
- update = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING;
- /* Just configuring queues interrupts when necessary */
- if (rte_intr_dp_is_en(intr_handle))
- update |= NFP_NET_CFG_UPDATE_MSIX;
+ update |= NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING;
if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
new_ctrl |= NFP_NET_CFG_CTRL_RINGCFG;
@@ -715,6 +807,10 @@ nfp_net_start(struct rte_eth_dev *dev)
goto error;
}
+ if (hw->is_pf)
+ /* Configure the physical port up */
+ nfp_nsp_eth_config(hw->nspu_desc, hw->pf_port_idx, 1);
+
hw->ctrl = new_ctrl;
return 0;
@@ -743,9 +839,12 @@ static void
nfp_net_stop(struct rte_eth_dev *dev)
{
int i;
+ struct nfp_net_hw *hw;
PMD_INIT_LOG(DEBUG, "Stop");
+ hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+
nfp_net_disable_queues(dev);
/* Clear queues */
@@ -758,6 +857,10 @@ nfp_net_stop(struct rte_eth_dev *dev)
nfp_net_reset_rx_queue(
(struct nfp_net_rxq *)dev->data->rx_queues[i]);
}
+
+ if (hw->is_pf)
+ /* Configure the physical port down */
+ nfp_nsp_eth_config(hw->nspu_desc, hw->pf_port_idx, 0);
}
/* Reset and stop device. The device can not be restarted. */
@@ -766,6 +869,7 @@ nfp_net_close(struct rte_eth_dev *dev)
{
struct nfp_net_hw *hw;
struct rte_pci_device *pci_dev;
+ int i;
PMD_INIT_LOG(DEBUG, "Close");
@@ -777,7 +881,18 @@ nfp_net_close(struct rte_eth_dev *dev)
* threads/queues before calling the device close function.
*/
- nfp_net_stop(dev);
+ nfp_net_disable_queues(dev);
+
+ /* Clear queues */
+ for (i = 0; i < dev->data->nb_tx_queues; i++) {
+ nfp_net_reset_tx_queue(
+ (struct nfp_net_txq *)dev->data->tx_queues[i]);
+ }
+
+ for (i = 0; i < dev->data->nb_rx_queues; i++) {
+ nfp_net_reset_rx_queue(
+ (struct nfp_net_rxq *)dev->data->rx_queues[i]);
+ }
rte_intr_disable(&pci_dev->intr_handle);
nn_cfg_writeb(hw, NFP_NET_CFG_LSC, 0xff);
@@ -895,17 +1010,10 @@ nfp_net_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)
nn_link_status = (nn_link_status >> NFP_NET_CFG_STS_LINK_RATE_SHIFT) &
NFP_NET_CFG_STS_LINK_RATE_MASK;
- if ((NFD_CFG_MAJOR_VERSION_of(hw->ver) < 4) ||
- ((NFD_CFG_MINOR_VERSION_of(hw->ver) == 4) &&
- (NFD_CFG_MINOR_VERSION_of(hw->ver) == 0)))
- /* We really do not know the speed wil old firmware */
+ if (nn_link_status >= RTE_DIM(ls_to_ethtool))
link.link_speed = ETH_SPEED_NUM_NONE;
- else {
- if (nn_link_status >= RTE_DIM(ls_to_ethtool))
- link.link_speed = ETH_SPEED_NUM_NONE;
- else
- link.link_speed = ls_to_ethtool[nn_link_status];
- }
+ else
+ link.link_speed = ls_to_ethtool[nn_link_status];
if (old.link_status != link.link_status) {
nfp_net_dev_atomic_write_link_status(dev, &link);
@@ -919,7 +1027,7 @@ nfp_net_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)
return -1;
}
-static void
+static int
nfp_net_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
{
int i;
@@ -1005,8 +1113,11 @@ nfp_net_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
nfp_dev_stats.imissed -= hw->eth_stats_base.imissed;
- if (stats)
+ if (stats) {
memcpy(stats, &nfp_dev_stats, sizeof(*stats));
+ return 0;
+ }
+ return -EINVAL;
}
static void
@@ -1125,6 +1236,11 @@ nfp_net_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
ETH_TXQ_FLAGS_NOOFFLOADS,
};
+ dev_info->flow_type_rss_offloads = ETH_RSS_NONFRAG_IPV4_TCP |
+ ETH_RSS_NONFRAG_IPV4_UDP |
+ ETH_RSS_NONFRAG_IPV6_TCP |
+ ETH_RSS_NONFRAG_IPV6_UDP;
+
dev_info->reta_size = NFP_NET_CFG_RSS_ITBL_SZ;
dev_info->hash_key_size = NFP_NET_CFG_RSS_KEY_SZ;
@@ -1240,12 +1356,12 @@ nfp_net_dev_link_status_print(struct rte_eth_dev *dev)
nfp_net_dev_atomic_read_link_status(dev, &link);
if (link.link_status)
RTE_LOG(INFO, PMD, "Port %d: Link Up - speed %u Mbps - %s\n",
- (int)(dev->data->port_id), (unsigned)link.link_speed,
+ dev->data->port_id, link.link_speed,
link.link_duplex == ETH_LINK_FULL_DUPLEX
? "full-duplex" : "half-duplex");
else
RTE_LOG(INFO, PMD, " Port %d: Link Down\n",
- (int)(dev->data->port_id));
+ dev->data->port_id);
RTE_LOG(INFO, PMD, "PCI Address: %04d:%02d:%02d:%d\n",
pci_dev->addr.domain, pci_dev->addr.bus,
@@ -1446,7 +1562,7 @@ nfp_net_rx_queue_setup(struct rte_eth_dev *dev,
}
/* Saving physical and virtual addresses for the RX ring */
- rxq->dma = (uint64_t)tz->phys_addr;
+ rxq->dma = (uint64_t)tz->iova;
rxq->rxds = (struct nfp_net_rx_desc *)tz->addr;
/* mbuf pointers array for referencing mbufs linked to RX descriptors */
@@ -1549,7 +1665,7 @@ nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
"tx_free_thresh must be less than the number of TX "
"descriptors. (tx_free_thresh=%u port=%d "
"queue=%d)\n", (unsigned int)tx_free_thresh,
- (int)dev->data->port_id, (int)queue_idx);
+ dev->data->port_id, (int)queue_idx);
return -(EINVAL);
}
@@ -1602,7 +1718,7 @@ nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
txq->txq_flags = tx_conf->txq_flags;
/* Saving physical and virtual addresses for the TX ring */
- txq->dma = (uint64_t)tz->phys_addr;
+ txq->dma = (uint64_t)tz->iova;
txq->txds = (struct nfp_net_tx_desc *)tz->addr;
/* mbuf pointers array for referencing mbufs linked to TX descriptors */
@@ -1720,6 +1836,8 @@ nfp_net_rx_cksum(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
#define NFP_HASH_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 4)
#define NFP_HASH_TYPE_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 8)
+#define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
+
/*
* nfp_net_set_hash - Set mbuf hash data
*
@@ -1730,18 +1848,57 @@ static inline void
nfp_net_set_hash(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
struct rte_mbuf *mbuf)
{
- uint32_t hash;
- uint32_t hash_type;
struct nfp_net_hw *hw = rxq->hw;
+ uint8_t *meta_offset;
+ uint32_t meta_info;
+ uint32_t hash = 0;
+ uint32_t hash_type = 0;
if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
return;
- if (!(rxd->rxd.flags & PCIE_DESC_RX_RSS))
- return;
+ if (NFD_CFG_MAJOR_VERSION_of(hw->ver) <= 3) {
+ if (!(rxd->rxd.flags & PCIE_DESC_RX_RSS))
+ return;
+
+ hash = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_OFFSET);
+ hash_type = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_TYPE_OFFSET);
- hash = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_OFFSET);
- hash_type = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_TYPE_OFFSET);
+ } else if (NFP_DESC_META_LEN(rxd)) {
+ /*
+ * new metadata api:
+ * <---- 32 bit ----->
+ * m field type word
+ * e data field #2
+ * t data field #1
+ * a data field #0
+ * ====================
+ * packet data
+ *
+ * Field type word contains up to 8 4bit field types
+ * A 4bit field type refers to a data field word
+ * A data field word can have several 4bit field types
+ */
+ meta_offset = rte_pktmbuf_mtod(mbuf, uint8_t *);
+ meta_offset -= NFP_DESC_META_LEN(rxd);
+ meta_info = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
+ meta_offset += 4;
+ /* NFP PMD just supports metadata for hashing */
+ switch (meta_info & NFP_NET_META_FIELD_MASK) {
+ case NFP_NET_META_HASH:
+ /* next field type is about the hash type */
+ meta_info >>= NFP_NET_META_FIELD_SIZE;
+ /* hash value is in the data field */
+ hash = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
+ hash_type = meta_info & NFP_NET_META_FIELD_MASK;
+ break;
+ default:
+ /* Unsupported metadata can be a performance issue */
+ return;
+ }
+ } else {
+ return;
+ }
mbuf->hash.rss = hash;
mbuf->ol_flags |= PKT_RX_RSS_HASH;
@@ -1847,9 +2004,9 @@ nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
*/
new_mb = rte_pktmbuf_alloc(rxq->mem_pool);
if (unlikely(new_mb == NULL)) {
- RTE_LOG_DP(DEBUG, PMD, "RX mbuf alloc failed port_id=%u "
- "queue_id=%u\n", (unsigned)rxq->port_id,
- (unsigned)rxq->qidx);
+ RTE_LOG_DP(DEBUG, PMD,
+ "RX mbuf alloc failed port_id=%u queue_id=%u\n",
+ rxq->port_id, (unsigned int)rxq->qidx);
nfp_net_mbuf_alloc_failed(rxq);
break;
}
@@ -1910,7 +2067,7 @@ nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
if ((rxds->rxd.flags & PCIE_DESC_RX_VLAN) &&
(hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN)) {
mb->vlan_tci = rte_cpu_to_le_32(rxds->rxd.vlan);
- mb->ol_flags |= PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
+ mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
}
/* Adding the mbuff to the mbuff array passed by the app */
@@ -1933,7 +2090,7 @@ nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
return nb_hold;
PMD_RX_LOG(DEBUG, "RX port_id=%u queue_id=%u, %d packets received\n",
- (unsigned)rxq->port_id, (unsigned)rxq->qidx, nb_hold);
+ rxq->port_id, (unsigned int)rxq->qidx, nb_hold);
nb_hold += rxq->nb_rx_hold;
@@ -1944,7 +2101,7 @@ nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
rte_wmb();
if (nb_hold > rxq->rx_free_thresh) {
PMD_RX_LOG(DEBUG, "port=%u queue=%u nb_hold=%u avail=%u\n",
- (unsigned)rxq->port_id, (unsigned)rxq->qidx,
+ rxq->port_id, (unsigned int)rxq->qidx,
(unsigned)nb_hold, (unsigned)avail);
nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, nb_hold);
nb_hold = 0;
@@ -2094,7 +2251,7 @@ nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
*/
pkt_size = pkt->pkt_len;
- while (pkt_size) {
+ while (pkt) {
/* Copying TSO, VLAN and cksum info */
*txds = txd;
@@ -2109,7 +2266,7 @@ nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
*lmbuf = pkt;
dma_size = pkt->data_len;
- dma_addr = rte_mbuf_data_dma_addr(pkt);
+ dma_addr = rte_mbuf_data_iova(pkt);
PMD_TX_LOG(DEBUG, "Working with mbuf at dma address:"
"%" PRIx64 "\n", dma_addr);
@@ -2126,13 +2283,13 @@ nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
txq->wr_p = 0;
pkt_size -= dma_size;
- if (!pkt_size) {
+ if (!pkt_size)
/* End of packet */
txds->offset_eop |= PCIE_DESC_TX_EOP;
- } else {
+ else
txds->offset_eop &= PCIE_DESC_TX_OFFSET_MASK;
- pkt = pkt->next;
- }
+
+ pkt = pkt->next;
/* Referencing next free TX descriptor */
txds = &txq->txds[txq->wr_p];
lmbuf = &txq->txbufs[txq->wr_p].mbuf;
@@ -2149,11 +2306,12 @@ xmit_end:
return i;
}
-static void
+static int
nfp_net_vlan_offload_set(struct rte_eth_dev *dev, int mask)
{
uint32_t new_ctrl, update;
struct nfp_net_hw *hw;
+ int ret;
hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
new_ctrl = 0;
@@ -2174,14 +2332,15 @@ nfp_net_vlan_offload_set(struct rte_eth_dev *dev, int mask)
new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_RXVLAN;
if (new_ctrl == 0)
- return;
+ return 0;
update = NFP_NET_CFG_UPDATE_GEN;
- if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
- return;
+ ret = nfp_net_reconfig(hw, new_ctrl, update);
+ if (!ret)
+ hw->ctrl = new_ctrl;
- hw->ctrl = new_ctrl;
+ return ret;
}
/* Update Redirection Table(RETA) of Receive Side Scaling of Ethernet device */
@@ -2233,7 +2392,8 @@ nfp_net_reta_update(struct rte_eth_dev *dev,
reta &= ~(0xFF << (8 * j));
reta |= reta_conf[idx].reta[shift + j] << (8 * j);
}
- nn_cfg_writel(hw, NFP_NET_CFG_RSS_ITBL + shift, reta);
+ nn_cfg_writel(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) + shift,
+ reta);
}
update = NFP_NET_CFG_UPDATE_RSS;
@@ -2280,7 +2440,8 @@ nfp_net_reta_query(struct rte_eth_dev *dev,
if (!mask)
continue;
- reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + shift);
+ reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) +
+ shift);
for (j = 0; j < 4; j++) {
if (!(mask & (0x1 << j)))
continue;
@@ -2330,6 +2491,9 @@ nfp_net_rss_hash_update(struct rte_eth_dev *dev,
NFP_NET_CFG_RSS_IPV6_TCP |
NFP_NET_CFG_RSS_IPV6_UDP;
+ cfg_rss_ctrl |= NFP_NET_CFG_RSS_MASK;
+ cfg_rss_ctrl |= NFP_NET_CFG_RSS_TOEPLITZ;
+
/* configuring where to apply the RSS hash */
nn_cfg_writel(hw, NFP_NET_CFG_RSS_CTRL, cfg_rss_ctrl);
@@ -2426,19 +2590,76 @@ static const struct eth_dev_ops nfp_net_eth_dev_ops = {
.rx_queue_intr_disable = nfp_rx_queue_intr_disable,
};
+/*
+ * All eth_dev created got its private data, but before nfp_net_init, that
+ * private data is referencing private data for all the PF ports. This is due
+ * to how the vNIC bars are mapped based on first port, so all ports need info
+ * about port 0 private data. Inside nfp_net_init the private data pointer is
+ * changed to the right address for each port once the bars have been mapped.
+ *
+ * This functions helps to find out which port and therefore which offset
+ * inside the private data array to use.
+ */
+static int
+get_pf_port_number(char *name)
+{
+ char *pf_str = name;
+ int size = 0;
+
+ while ((*pf_str != '_') && (*pf_str != '\0') && (size++ < 30))
+ pf_str++;
+
+ if (size == 30)
+ /*
+ * This should not happen at all and it would mean major
+ * implementation fault.
+ */
+ rte_panic("nfp_net: problem with pf device name\n");
+
+ /* Expecting _portX with X within [0,7] */
+ pf_str += 5;
+
+ return (int)strtol(pf_str, NULL, 10);
+}
+
static int
nfp_net_init(struct rte_eth_dev *eth_dev)
{
struct rte_pci_device *pci_dev;
- struct nfp_net_hw *hw;
+ struct nfp_net_hw *hw, *hwport0;
- uint32_t tx_bar_off, rx_bar_off;
+ uint64_t tx_bar_off = 0, rx_bar_off = 0;
uint32_t start_q;
int stride = 4;
+ nspu_desc_t *nspu_desc = NULL;
+ uint64_t bar_offset;
+ int port = 0;
+
PMD_INIT_FUNC_TRACE();
- hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
+ pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
+
+ if ((pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC) ||
+ (pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC)) {
+ port = get_pf_port_number(eth_dev->data->name);
+ if (port < 0 || port > 7) {
+ RTE_LOG(ERR, PMD, "Port value is wrong\n");
+ return -ENODEV;
+ }
+
+ PMD_INIT_LOG(DEBUG, "Working with PF port value %d\n", port);
+
+ /* This points to port 0 private data */
+ hwport0 = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
+
+ /* This points to the specific port private data */
+ hw = &hwport0[port];
+ hw->pf_port_idx = port;
+ } else {
+ hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
+ hwport0 = 0;
+ }
eth_dev->dev_ops = &nfp_net_eth_dev_ops;
eth_dev->rx_pkt_burst = &nfp_net_recv_pkts;
@@ -2448,9 +2669,7 @@ nfp_net_init(struct rte_eth_dev *eth_dev)
if (rte_eal_process_type() != RTE_PROC_PRIMARY)
return 0;
- pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
rte_eth_copy_pci_info(eth_dev, pci_dev);
- eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
hw->device_id = pci_dev->id.device_id;
hw->vendor_id = pci_dev->id.vendor_id;
@@ -2468,11 +2687,42 @@ nfp_net_init(struct rte_eth_dev *eth_dev)
"hw->ctrl_bar is NULL. BAR0 not configured\n");
return -ENODEV;
}
+
+ if (hw->is_pf && port == 0) {
+ nspu_desc = hw->nspu_desc;
+
+ if (nfp_nsp_map_ctrl_bar(nspu_desc, &bar_offset) != 0) {
+ /*
+ * A firmware should be there after PF probe so this
+ * should not happen.
+ */
+ RTE_LOG(ERR, PMD, "PF BAR symbol resolution failed\n");
+ return -ENODEV;
+ }
+
+ /* vNIC PF control BAR is a subset of PF PCI device BAR */
+ hw->ctrl_bar += bar_offset;
+ PMD_INIT_LOG(DEBUG, "ctrl bar: %p\n", hw->ctrl_bar);
+ }
+
+ if (port > 0) {
+ if (!hwport0->ctrl_bar)
+ return -ENODEV;
+
+ /* address based on port0 offset */
+ hw->ctrl_bar = hwport0->ctrl_bar +
+ (port * NFP_PF_CSR_SLICE_SIZE);
+ }
+
+ PMD_INIT_LOG(DEBUG, "ctrl bar: %p\n", hw->ctrl_bar);
+
hw->max_rx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_RXRINGS);
hw->max_tx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_TXRINGS);
/* Work out where in the BAR the queues start. */
switch (pci_dev->id.device_id) {
+ case PCI_DEVICE_ID_NFP4000_PF_NIC:
+ case PCI_DEVICE_ID_NFP6000_PF_NIC:
case PCI_DEVICE_ID_NFP6000_VF_NIC:
start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_TXQ);
tx_bar_off = NFP_PCIE_QUEUE(start_q);
@@ -2484,11 +2734,34 @@ nfp_net_init(struct rte_eth_dev *eth_dev)
return -ENODEV;
}
- PMD_INIT_LOG(DEBUG, "tx_bar_off: 0x%08x", tx_bar_off);
- PMD_INIT_LOG(DEBUG, "rx_bar_off: 0x%08x", rx_bar_off);
+ PMD_INIT_LOG(DEBUG, "tx_bar_off: 0x%" PRIx64 "\n", tx_bar_off);
+ PMD_INIT_LOG(DEBUG, "rx_bar_off: 0x%" PRIx64 "\n", rx_bar_off);
+
+ if (hw->is_pf && port == 0) {
+ /* configure access to tx/rx vNIC BARs */
+ nfp_nsp_map_queues_bar(nspu_desc, &bar_offset);
+ PMD_INIT_LOG(DEBUG, "tx/rx bar_offset: %" PRIx64 "\n",
+ bar_offset);
+ hwport0->hw_queues = (uint8_t *)pci_dev->mem_resource[0].addr;
- hw->tx_bar = (uint8_t *)pci_dev->mem_resource[2].addr + tx_bar_off;
- hw->rx_bar = (uint8_t *)pci_dev->mem_resource[2].addr + rx_bar_off;
+ /* vNIC PF tx/rx BARs are a subset of PF PCI device */
+ hwport0->hw_queues += bar_offset;
+
+ /* Lets seize the chance to read eth table from hw */
+ if (nfp_nsp_eth_read_table(nspu_desc, &hw->eth_table))
+ return -ENODEV;
+ }
+
+ if (hw->is_pf) {
+ hw->tx_bar = hwport0->hw_queues + tx_bar_off;
+ hw->rx_bar = hwport0->hw_queues + rx_bar_off;
+ eth_dev->data->dev_private = hw;
+ } else {
+ hw->tx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
+ tx_bar_off;
+ hw->rx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
+ rx_bar_off;
+ }
PMD_INIT_LOG(DEBUG, "ctrl_bar: %p, tx_bar: %p, rx_bar: %p",
hw->ctrl_bar, hw->tx_bar, hw->rx_bar);
@@ -2508,8 +2781,10 @@ nfp_net_init(struct rte_eth_dev *eth_dev)
PMD_INIT_LOG(INFO, "VER: %#x, Maximum supported MTU: %d",
hw->ver, hw->max_mtu);
- PMD_INIT_LOG(INFO, "CAP: %#x, %s%s%s%s%s%s%s%s%s", hw->cap,
+ PMD_INIT_LOG(INFO, "CAP: %#x, %s%s%s%s%s%s%s%s%s%s%s", hw->cap,
hw->cap & NFP_NET_CFG_CTRL_PROMISC ? "PROMISC " : "",
+ hw->cap & NFP_NET_CFG_CTRL_L2BC ? "L2BCFILT " : "",
+ hw->cap & NFP_NET_CFG_CTRL_L2MC ? "L2MCFILT " : "",
hw->cap & NFP_NET_CFG_CTRL_RXCSUM ? "RXCSUM " : "",
hw->cap & NFP_NET_CFG_CTRL_TXCSUM ? "TXCSUM " : "",
hw->cap & NFP_NET_CFG_CTRL_RXVLAN ? "RXVLAN " : "",
@@ -2537,11 +2812,18 @@ nfp_net_init(struct rte_eth_dev *eth_dev)
return -ENOMEM;
}
- nfp_net_read_mac(hw);
+ if (hw->is_pf) {
+ nfp_net_pf_read_mac(hwport0, port);
+ nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
+ } else {
+ nfp_net_vf_read_mac(hw);
+ }
- if (!is_valid_assigned_ether_addr((struct ether_addr *)&hw->mac_addr))
+ if (!is_valid_assigned_ether_addr((struct ether_addr *)&hw->mac_addr)) {
/* Using random mac addresses for VFs */
eth_random_addr(&hw->mac_addr[0]);
+ nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
+ }
/* Copying mac address to DPDK eth_dev struct */
ether_addr_copy((struct ether_addr *)hw->mac_addr,
@@ -2568,12 +2850,154 @@ nfp_net_init(struct rte_eth_dev *eth_dev)
return 0;
}
-static const struct rte_pci_id pci_id_nfp_net_map[] = {
+static int
+nfp_pf_create_dev(struct rte_pci_device *dev, int port, int ports,
+ nfpu_desc_t *nfpu_desc, void **priv)
+{
+ struct rte_eth_dev *eth_dev;
+ struct nfp_net_hw *hw;
+ char *port_name;
+ int ret;
+
+ port_name = rte_zmalloc("nfp_pf_port_name", 100, 0);
+ if (!port_name)
+ return -ENOMEM;
+
+ if (ports > 1)
+ sprintf(port_name, "%s_port%d", dev->device.name, port);
+ else
+ sprintf(port_name, "%s", dev->device.name);
+
+ eth_dev = rte_eth_dev_allocate(port_name);
+ if (!eth_dev)
+ return -ENOMEM;
+
+ if (port == 0) {
+ *priv = rte_zmalloc(port_name,
+ sizeof(struct nfp_net_adapter) * ports,
+ RTE_CACHE_LINE_SIZE);
+ if (!*priv) {
+ rte_eth_dev_release_port(eth_dev);
+ return -ENOMEM;
+ }
+ }
+
+ eth_dev->data->dev_private = *priv;
+
+ /*
+ * dev_private pointing to port0 dev_private because we need
+ * to configure vNIC bars based on port0 at nfp_net_init.
+ * Then dev_private is adjusted per port.
+ */
+ hw = (struct nfp_net_hw *)(eth_dev->data->dev_private) + port;
+ hw->nspu_desc = nfpu_desc->nspu;
+ hw->nfpu_desc = nfpu_desc;
+ hw->is_pf = 1;
+ if (ports > 1)
+ hw->pf_multiport_enabled = 1;
+
+ eth_dev->device = &dev->device;
+ rte_eth_copy_pci_info(eth_dev, dev);
+
+ ret = nfp_net_init(eth_dev);
+
+ if (ret)
+ rte_eth_dev_release_port(eth_dev);
+
+ rte_free(port_name);
+
+ return ret;
+}
+
+static int nfp_pf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
+ struct rte_pci_device *dev)
+{
+ nfpu_desc_t *nfpu_desc;
+ nspu_desc_t *nspu_desc;
+ uint64_t offset_symbol;
+ uint8_t *bar_offset;
+ int major, minor;
+ int total_ports;
+ void *priv = 0;
+ int ret = -ENODEV;
+ int i;
+
+ if (!dev)
+ return ret;
+
+ nfpu_desc = rte_malloc("nfp nfpu", sizeof(nfpu_desc_t), 0);
+ if (!nfpu_desc)
+ return -ENOMEM;
+
+ if (nfpu_open(dev, nfpu_desc, 0) < 0) {
+ RTE_LOG(ERR, PMD,
+ "nfpu_open failed\n");
+ goto nfpu_error;
+ }
+
+ nspu_desc = nfpu_desc->nspu;
+
+
+ /* Check NSP ABI version */
+ if (nfp_nsp_get_abi_version(nspu_desc, &major, &minor) < 0) {
+ RTE_LOG(INFO, PMD, "NFP NSP not present\n");
+ goto error;
+ }
+ PMD_INIT_LOG(INFO, "nspu ABI version: %d.%d\n", major, minor);
+
+ if ((major == 0) && (minor < 20)) {
+ RTE_LOG(INFO, PMD, "NFP NSP ABI version too old. Required 0.20 or higher\n");
+ goto error;
+ }
+
+ ret = nfp_nsp_fw_setup(nspu_desc, "nfd_cfg_pf0_num_ports",
+ &offset_symbol);
+ if (ret)
+ goto error;
+
+ bar_offset = (uint8_t *)dev->mem_resource[0].addr;
+ bar_offset += offset_symbol;
+ total_ports = (uint32_t)*bar_offset;
+ PMD_INIT_LOG(INFO, "Total pf ports: %d\n", total_ports);
+
+ if (total_ports <= 0 || total_ports > 8) {
+ RTE_LOG(ERR, PMD, "nfd_cfg_pf0_num_ports symbol with wrong value");
+ ret = -ENODEV;
+ goto error;
+ }
+
+ for (i = 0; i < total_ports; i++) {
+ ret = nfp_pf_create_dev(dev, i, total_ports, nfpu_desc, &priv);
+ if (ret)
+ goto error;
+ }
+
+ return 0;
+
+error:
+ nfpu_close(nfpu_desc);
+nfpu_error:
+ rte_free(nfpu_desc);
+
+ return ret;
+}
+
+static const struct rte_pci_id pci_id_nfp_pf_net_map[] = {
+ {
+ RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
+ PCI_DEVICE_ID_NFP4000_PF_NIC)
+ },
{
RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
PCI_DEVICE_ID_NFP6000_PF_NIC)
},
{
+ .vendor_id = 0,
+ },
+};
+
+static const struct rte_pci_id pci_id_nfp_vf_net_map[] = {
+ {
RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
PCI_DEVICE_ID_NFP6000_VF_NIC)
},
@@ -2591,19 +3015,45 @@ static int eth_nfp_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
static int eth_nfp_pci_remove(struct rte_pci_device *pci_dev)
{
+ struct rte_eth_dev *eth_dev;
+ struct nfp_net_hw *hw, *hwport0;
+ int port = 0;
+
+ eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
+ if ((pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC) ||
+ (pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC)) {
+ port = get_pf_port_number(eth_dev->data->name);
+ hwport0 = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
+ hw = &hwport0[port];
+ } else {
+ hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
+ }
+ /* hotplug is not possible with multiport PF */
+ if (hw->pf_multiport_enabled)
+ return -ENOTSUP;
return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
}
-static struct rte_pci_driver rte_nfp_net_pmd = {
- .id_table = pci_id_nfp_net_map,
+static struct rte_pci_driver rte_nfp_net_pf_pmd = {
+ .id_table = pci_id_nfp_pf_net_map,
+ .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
+ .probe = nfp_pf_pci_probe,
+ .remove = eth_nfp_pci_remove,
+};
+
+static struct rte_pci_driver rte_nfp_net_vf_pmd = {
+ .id_table = pci_id_nfp_vf_net_map,
.drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
.probe = eth_nfp_pci_probe,
.remove = eth_nfp_pci_remove,
};
-RTE_PMD_REGISTER_PCI(net_nfp, rte_nfp_net_pmd);
-RTE_PMD_REGISTER_PCI_TABLE(net_nfp, pci_id_nfp_net_map);
-RTE_PMD_REGISTER_KMOD_DEP(net_nfp, "* igb_uio | uio_pci_generic | vfio-pci");
+RTE_PMD_REGISTER_PCI(net_nfp_pf, rte_nfp_net_pf_pmd);
+RTE_PMD_REGISTER_PCI(net_nfp_vf, rte_nfp_net_vf_pmd);
+RTE_PMD_REGISTER_PCI_TABLE(net_nfp_pf, pci_id_nfp_pf_net_map);
+RTE_PMD_REGISTER_PCI_TABLE(net_nfp_vf, pci_id_nfp_vf_net_map);
+RTE_PMD_REGISTER_KMOD_DEP(net_nfp_pf, "* igb_uio | uio_pci_generic | vfio");
+RTE_PMD_REGISTER_KMOD_DEP(net_nfp_vf, "* igb_uio | uio_pci_generic | vfio");
/*
* Local variables:
diff --git a/drivers/net/nfp/nfp_net_ctrl.h b/drivers/net/nfp/nfp_net_ctrl.h
index 2c500433..1ebd99ca 100644
--- a/drivers/net/nfp/nfp_net_ctrl.h
+++ b/drivers/net/nfp/nfp_net_ctrl.h
@@ -52,6 +52,13 @@
/* Offset in Freelist buffer where packet starts on RX */
#define NFP_NET_RX_OFFSET 32
+/* working with metadata api (NFD version > 3.0) */
+#define NFP_NET_META_FIELD_SIZE 4
+#define NFP_NET_META_FIELD_MASK ((1 << NFP_NET_META_FIELD_SIZE) - 1)
+
+/* Prepend field types */
+#define NFP_NET_META_HASH 1 /* next field carries hash type */
+
/* Hash type pre-pended when a RSS hash was computed */
#define NFP_NET_RSS_NONE 0
#define NFP_NET_RSS_IPV4 1
@@ -327,6 +334,9 @@
#define NFP_NET_CFG_RXR_STATS(_x) (NFP_NET_CFG_RXR_STATS_BASE + \
((_x) * 0x10))
+/* PF multiport offset */
+#define NFP_PF_CSR_SLICE_SIZE (32 * 1024)
+
#endif /* _NFP_NET_CTRL_H_ */
/*
* Local variables:
diff --git a/drivers/net/nfp/nfp_net_eth.h b/drivers/net/nfp/nfp_net_eth.h
new file mode 100644
index 00000000..af57f03c
--- /dev/null
+++ b/drivers/net/nfp/nfp_net_eth.h
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2017 Netronome Systems, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * vim:shiftwidth=8:noexpandtab
+ *
+ * @file dpdk/pmd/nfp_net_eth.h
+ *
+ * Netronome NFP_NET PDM driver
+ */
+
+union eth_table_entry {
+ struct {
+ uint64_t port;
+ uint64_t state;
+ uint8_t mac_addr[6];
+ uint8_t resv[2];
+ uint64_t control;
+ };
+ uint64_t raw[4];
+};
+
+#ifndef BIT_ULL
+#define BIT_ULL(a) (1ULL << (a))
+#endif
+
+#define NSP_ETH_NBI_PORT_COUNT 24
+#define NSP_ETH_MAX_COUNT (2 * NSP_ETH_NBI_PORT_COUNT)
+#define NSP_ETH_TABLE_SIZE (NSP_ETH_MAX_COUNT * sizeof(union eth_table_entry))
+
+#define NSP_ETH_PORT_LANES 0xf
+#define NSP_ETH_PORT_INDEX 0xff00
+#define NSP_ETH_PORT_LABEL 0x3f000000000000
+#define NSP_ETH_PORT_PHYLABEL 0xfc0000000000000
+
+#define NSP_ETH_PORT_LANES_MASK rte_cpu_to_le_64(NSP_ETH_PORT_LANES)
+
+#define NSP_ETH_STATE_CONFIGURED BIT_ULL(0)
+#define NSP_ETH_STATE_ENABLED BIT_ULL(1)
+#define NSP_ETH_STATE_TX_ENABLED BIT_ULL(2)
+#define NSP_ETH_STATE_RX_ENABLED BIT_ULL(3)
+#define NSP_ETH_STATE_RATE 0xf00
+#define NSP_ETH_STATE_INTERFACE 0xff000
+#define NSP_ETH_STATE_MEDIA 0x300000
+#define NSP_ETH_STATE_OVRD_CHNG BIT_ULL(22)
+#define NSP_ETH_STATE_ANEG 0x3800000
+
+#define NSP_ETH_CTRL_CONFIGURED BIT_ULL(0)
+#define NSP_ETH_CTRL_ENABLED BIT_ULL(1)
+#define NSP_ETH_CTRL_TX_ENABLED BIT_ULL(2)
+#define NSP_ETH_CTRL_RX_ENABLED BIT_ULL(3)
+#define NSP_ETH_CTRL_SET_RATE BIT_ULL(4)
+#define NSP_ETH_CTRL_SET_LANES BIT_ULL(5)
+#define NSP_ETH_CTRL_SET_ANEG BIT_ULL(6)
diff --git a/drivers/net/nfp/nfp_net_pmd.h b/drivers/net/nfp/nfp_net_pmd.h
index eec56bc1..1ae0ea62 100644
--- a/drivers/net/nfp/nfp_net_pmd.h
+++ b/drivers/net/nfp/nfp_net_pmd.h
@@ -42,6 +42,7 @@
#define NFP_NET_PMD_VERSION "0.1"
#define PCI_VENDOR_ID_NETRONOME 0x19ee
+#define PCI_DEVICE_ID_NFP4000_PF_NIC 0x4000
#define PCI_DEVICE_ID_NFP6000_PF_NIC 0x6000
#define PCI_DEVICE_ID_NFP6000_VF_NIC 0x6003
@@ -143,6 +144,11 @@ static inline void nn_writel(uint32_t val, volatile void *addr)
rte_write32(val, addr);
}
+static inline void nn_writew(uint16_t val, volatile void *addr)
+{
+ rte_write16(val, addr);
+}
+
static inline uint64_t nn_readq(volatile void *addr)
{
const volatile uint32_t *p = addr;
@@ -250,7 +256,7 @@ struct nfp_net_txq {
uint32_t tx_hthresh; /* not used by now. Future? */
uint32_t tx_wthresh; /* not used by now. Future? */
uint32_t txq_flags; /* not used by now. Future? */
- uint8_t port_id;
+ uint16_t port_id;
int qidx;
int tx_qcidx;
__le64 dma;
@@ -431,6 +437,13 @@ struct nfp_net_hw {
struct nfp_cpp_area *rx_area;
struct nfp_cpp_area *msix_area;
#endif
+ uint8_t *hw_queues;
+ uint8_t is_pf;
+ uint8_t pf_port_idx;
+ uint8_t pf_multiport_enabled;
+ union eth_table_entry *eth_table;
+ nspu_desc_t *nspu_desc;
+ nfpu_desc_t *nfpu_desc;
};
struct nfp_net_adapter {
diff --git a/drivers/net/nfp/nfp_nfpu.c b/drivers/net/nfp/nfp_nfpu.c
new file mode 100644
index 00000000..5775d8da
--- /dev/null
+++ b/drivers/net/nfp/nfp_nfpu.c
@@ -0,0 +1,103 @@
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include <unistd.h>
+#include <errno.h>
+#include <sys/file.h>
+#include <sys/stat.h>
+#include <fcntl.h>
+#include <sys/types.h>
+
+#include <rte_bus_pci.h>
+#include <rte_malloc.h>
+
+#include "nfp_nfpu.h"
+
+/* PF BAR and expansion BAR for the NSP interface */
+#define NFP_CFG_PCIE_BAR 0
+#define NFP_CFG_EXP_BAR 7
+
+#define NFP_CFG_EXP_BAR_CFG_BASE 0x30000
+
+/* There could be other NFP userspace tools using the NSP interface.
+ * Make sure there is no other process using it and locking the access for
+ * avoiding problems.
+ */
+static int
+nspv_aquire_process_lock(nfpu_desc_t *desc)
+{
+ int rc;
+ struct flock lock;
+ char lockname[30];
+
+ memset(&lock, 0, sizeof(lock));
+
+ snprintf(lockname, sizeof(lockname), "/var/lock/nfp%d", desc->nfp);
+
+ /* Using S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP | S_IROTH | S_IWOTH */
+ desc->lock = open(lockname, O_RDWR | O_CREAT, 0666);
+
+ if (desc->lock < 0)
+ return desc->lock;
+
+ lock.l_type = F_WRLCK;
+ lock.l_whence = SEEK_SET;
+ rc = -1;
+ while (rc != 0) {
+ rc = fcntl(desc->lock, F_SETLK, &lock);
+ if (rc < 0) {
+ if ((errno != EAGAIN) && (errno != EACCES)) {
+ close(desc->lock);
+ return rc;
+ }
+ }
+ }
+
+ return 0;
+}
+
+int
+nfpu_open(struct rte_pci_device *pci_dev, nfpu_desc_t *desc, int nfp)
+{
+ void *cfg_base, *mem_base;
+ size_t barsz;
+ int ret = 0;
+ int i = 0;
+
+ desc->nfp = nfp;
+
+ ret = nspv_aquire_process_lock(desc);
+ if (ret)
+ return -1;
+
+ barsz = pci_dev->mem_resource[0].len;
+
+ /* barsz in log2 */
+ while (barsz >>= 1)
+ i++;
+ barsz = i;
+
+ /* Getting address for NFP expansion BAR registers */
+ cfg_base = pci_dev->mem_resource[0].addr;
+ cfg_base = (uint8_t *)cfg_base + NFP_CFG_EXP_BAR_CFG_BASE;
+
+ /* Getting address for NFP NSP interface registers */
+ mem_base = pci_dev->mem_resource[0].addr;
+ mem_base = (uint8_t *)mem_base + (NFP_CFG_EXP_BAR << (barsz - 3));
+
+
+ desc->nspu = rte_malloc("nfp nspu", sizeof(nspu_desc_t), 0);
+ nfp_nspu_init(desc->nspu, desc->nfp, NFP_CFG_PCIE_BAR, barsz,
+ NFP_CFG_EXP_BAR, cfg_base, mem_base);
+
+ return ret;
+}
+
+int
+nfpu_close(nfpu_desc_t *desc)
+{
+ rte_free(desc->nspu);
+ close(desc->lock);
+ unlink("/var/lock/nfp0");
+ return 0;
+}
diff --git a/drivers/net/nfp/nfp_nfpu.h b/drivers/net/nfp/nfp_nfpu.h
new file mode 100644
index 00000000..e56fa099
--- /dev/null
+++ b/drivers/net/nfp/nfp_nfpu.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2017 Netronome Systems, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * vim:shiftwidth=8:noexpandtab
+ *
+ * @file dpdk/pmd/nfp_nfpu.h
+ *
+ * Netronome NFP_NET PDM driver
+ */
+
+/*
+ * NFP User interface creates a window for talking with NFP NSP processor
+ */
+
+
+#include <rte_bus_pci.h>
+#include "nfp_nspu.h"
+
+typedef struct {
+ int nfp;
+ int lock;
+ nspu_desc_t *nspu;
+} nfpu_desc_t;
+
+int nfpu_open(struct rte_pci_device *pci_dev, nfpu_desc_t *desc, int nfp);
+int nfpu_close(nfpu_desc_t *desc);
diff --git a/drivers/net/nfp/nfp_nspu.c b/drivers/net/nfp/nfp_nspu.c
new file mode 100644
index 00000000..6ba940cb
--- /dev/null
+++ b/drivers/net/nfp/nfp_nspu.c
@@ -0,0 +1,623 @@
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include <unistd.h>
+#include <sys/types.h>
+#include <sys/file.h>
+#include <sys/stat.h>
+#include <fcntl.h>
+
+#include <rte_log.h>
+#include <rte_byteorder.h>
+
+#include "nfp_nfpu.h"
+
+#define CFG_EXP_BAR_ADDR_SZ 1
+#define CFG_EXP_BAR_MAP_TYPE 1
+
+#define EXP_BAR_TARGET_SHIFT 23
+#define EXP_BAR_LENGTH_SHIFT 27 /* 0=32, 1=64 bit increment */
+#define EXP_BAR_MAP_TYPE_SHIFT 29 /* Bulk BAR map */
+
+/* NFP target for NSP access */
+#define NFP_NSP_TARGET 7
+
+/* Expansion BARs for mapping PF vnic BARs */
+#define NFP_NET_PF_CFG_EXP_BAR 6
+#define NFP_NET_PF_HW_QUEUES_EXP_BAR 5
+
+/*
+ * This is an NFP internal address used for configuring properly an NFP
+ * expansion BAR.
+ */
+#define MEM_CMD_BASE_ADDR 0x8100000000
+
+/* NSP interface registers */
+#define NSP_BASE (MEM_CMD_BASE_ADDR + 0x22100)
+#define NSP_STATUS 0x00
+#define NSP_COMMAND 0x08
+#define NSP_BUFFER 0x10
+#define NSP_DEFAULT_BUF 0x18
+#define NSP_DEFAULT_BUF_CFG 0x20
+
+#define NSP_MAGIC 0xab10
+#define NSP_STATUS_MAGIC(x) (((x) >> 48) & 0xffff)
+#define NSP_STATUS_MAJOR(x) (int)(((x) >> 44) & 0xf)
+#define NSP_STATUS_MINOR(x) (int)(((x) >> 32) & 0xfff)
+
+/* NSP commands */
+#define NSP_CMD_RESET 1
+#define NSP_CMD_FW_LOAD 6
+#define NSP_CMD_READ_ETH_TABLE 7
+#define NSP_CMD_WRITE_ETH_TABLE 8
+#define NSP_CMD_GET_SYMBOL 14
+
+#define NSP_BUFFER_CFG_SIZE_MASK (0xff)
+
+#define NSP_REG_ADDR(d, off, reg) ((uint8_t *)(d)->mem_base + (off) + (reg))
+#define NSP_REG_VAL(p) (*(uint64_t *)(p))
+
+/*
+ * An NFP expansion BAR is configured for allowing access to a specific NFP
+ * target:
+ *
+ * IN:
+ * desc: struct with basic NSP addresses to work with
+ * expbar: NFP PF expansion BAR index to configure
+ * tgt: NFP target to configure access
+ * addr: NFP target address
+ *
+ * OUT:
+ * pcie_offset: NFP PCI BAR offset to work with
+ */
+static void
+nfp_nspu_mem_bar_cfg(nspu_desc_t *desc, int expbar, int tgt,
+ uint64_t addr, uint64_t *pcie_offset)
+{
+ uint64_t x, y, barsz;
+ uint32_t *expbar_ptr;
+
+ barsz = desc->barsz;
+
+ /*
+ * NFP CPP address to configure. This comes from NFP 6000
+ * datasheet document based on Bulk mapping.
+ */
+ x = (addr >> (barsz - 3)) << (21 - (40 - (barsz - 3)));
+ x |= CFG_EXP_BAR_MAP_TYPE << EXP_BAR_MAP_TYPE_SHIFT;
+ x |= CFG_EXP_BAR_ADDR_SZ << EXP_BAR_LENGTH_SHIFT;
+ x |= tgt << EXP_BAR_TARGET_SHIFT;
+
+ /* Getting expansion bar configuration register address */
+ expbar_ptr = (uint32_t *)desc->cfg_base;
+ /* Each physical PCI BAR has 8 NFP expansion BARs */
+ expbar_ptr += (desc->pcie_bar * 8) + expbar;
+
+ /* Writing to the expansion BAR register */
+ *expbar_ptr = (uint32_t)x;
+
+ /* Getting the pcie offset to work with from userspace */
+ y = addr & ((uint64_t)(1 << (barsz - 3)) - 1);
+ *pcie_offset = y;
+}
+
+/*
+ * Configuring an expansion bar for accessing NSP userspace interface. This
+ * function configures always the same expansion bar, which implies access to
+ * previously configured NFP target is lost.
+ */
+static void
+nspu_xlate(nspu_desc_t *desc, uint64_t addr, uint64_t *pcie_offset)
+{
+ nfp_nspu_mem_bar_cfg(desc, desc->exp_bar, NFP_NSP_TARGET, addr,
+ pcie_offset);
+}
+
+int
+nfp_nsp_get_abi_version(nspu_desc_t *desc, int *major, int *minor)
+{
+ uint64_t pcie_offset;
+ uint64_t nsp_reg;
+
+ nspu_xlate(desc, NSP_BASE, &pcie_offset);
+ nsp_reg = NSP_REG_VAL(NSP_REG_ADDR(desc, pcie_offset, NSP_STATUS));
+
+ if (NSP_STATUS_MAGIC(nsp_reg) != NSP_MAGIC)
+ return -1;
+
+ *major = NSP_STATUS_MAJOR(nsp_reg);
+ *minor = NSP_STATUS_MINOR(nsp_reg);
+
+ return 0;
+}
+
+int
+nfp_nspu_init(nspu_desc_t *desc, int nfp, int pcie_bar, size_t pcie_barsz,
+ int exp_bar, void *exp_bar_cfg_base, void *exp_bar_mmap)
+{
+ uint64_t offset, buffaddr;
+ uint64_t nsp_reg;
+
+ desc->nfp = nfp;
+ desc->pcie_bar = pcie_bar;
+ desc->exp_bar = exp_bar;
+ desc->barsz = pcie_barsz;
+ desc->windowsz = 1 << (desc->barsz - 3);
+ desc->cfg_base = exp_bar_cfg_base;
+ desc->mem_base = exp_bar_mmap;
+
+ nspu_xlate(desc, NSP_BASE, &offset);
+
+ /*
+ * Other NSPU clients can use other buffers. Let's tell NSPU we use the
+ * default buffer.
+ */
+ buffaddr = NSP_REG_VAL(NSP_REG_ADDR(desc, offset, NSP_DEFAULT_BUF));
+ NSP_REG_VAL(NSP_REG_ADDR(desc, offset, NSP_BUFFER)) = buffaddr;
+
+ /* NFP internal addresses are 40 bits. Clean all other bits here */
+ buffaddr = buffaddr & (((uint64_t)1 << 40) - 1);
+ desc->bufaddr = buffaddr;
+
+ /* Lets get information about the buffer */
+ nsp_reg = NSP_REG_VAL(NSP_REG_ADDR(desc, offset, NSP_DEFAULT_BUF_CFG));
+
+ /* Buffer size comes in MBs. Coversion to bytes */
+ desc->buf_size = ((size_t)nsp_reg & NSP_BUFFER_CFG_SIZE_MASK) << 20;
+
+ return 0;
+}
+
+#define NSPU_NFP_BUF(addr, base, off) \
+ (*(uint64_t *)((uint8_t *)(addr)->mem_base + ((base) | (off))))
+
+#define NSPU_HOST_BUF(base, off) (*(uint64_t *)((uint8_t *)(base) + (off)))
+
+static int
+nspu_buff_write(nspu_desc_t *desc, void *buffer, size_t size)
+{
+ uint64_t pcie_offset, pcie_window_base, pcie_window_offset;
+ uint64_t windowsz = desc->windowsz;
+ uint64_t buffaddr, j, i = 0;
+ int ret = 0;
+
+ if (size > desc->buf_size)
+ return -1;
+
+ buffaddr = desc->bufaddr;
+ windowsz = desc->windowsz;
+
+ while (i < size) {
+ /* Expansion bar reconfiguration per window size */
+ nspu_xlate(desc, buffaddr + i, &pcie_offset);
+ pcie_window_base = pcie_offset & (~(windowsz - 1));
+ pcie_window_offset = pcie_offset & (windowsz - 1);
+ for (j = pcie_window_offset; ((j < windowsz) && (i < size));
+ j += 8) {
+ NSPU_NFP_BUF(desc, pcie_window_base, j) =
+ NSPU_HOST_BUF(buffer, i);
+ i += 8;
+ }
+ }
+
+ return ret;
+}
+
+static int
+nspu_buff_read(nspu_desc_t *desc, void *buffer, size_t size)
+{
+ uint64_t pcie_offset, pcie_window_base, pcie_window_offset;
+ uint64_t windowsz, i = 0, j;
+ uint64_t buffaddr;
+ int ret = 0;
+
+ if (size > desc->buf_size)
+ return -1;
+
+ buffaddr = desc->bufaddr;
+ windowsz = desc->windowsz;
+
+ while (i < size) {
+ /* Expansion bar reconfiguration per window size */
+ nspu_xlate(desc, buffaddr + i, &pcie_offset);
+ pcie_window_base = pcie_offset & (~(windowsz - 1));
+ pcie_window_offset = pcie_offset & (windowsz - 1);
+ for (j = pcie_window_offset; ((j < windowsz) && (i < size));
+ j += 8) {
+ NSPU_HOST_BUF(buffer, i) =
+ NSPU_NFP_BUF(desc, pcie_window_base, j);
+ i += 8;
+ }
+ }
+
+ return ret;
+}
+
+static int
+nspu_command(nspu_desc_t *desc, uint16_t cmd, int read, int write,
+ void *buffer, size_t rsize, size_t wsize)
+{
+ uint64_t status, cmd_reg;
+ uint64_t offset;
+ int retry = 0;
+ int retries = 120;
+ int ret = 0;
+
+ /* Same expansion BAR is used for different things */
+ nspu_xlate(desc, NSP_BASE, &offset);
+
+ status = NSP_REG_VAL(NSP_REG_ADDR(desc, offset, NSP_STATUS));
+
+ while ((status & 0x1) && (retry < retries)) {
+ status = NSP_REG_VAL(NSP_REG_ADDR(desc, offset, NSP_STATUS));
+ retry++;
+ sleep(1);
+ }
+
+ if (retry == retries)
+ return -1;
+
+ if (write) {
+ ret = nspu_buff_write(desc, buffer, wsize);
+ if (ret)
+ return ret;
+
+ /* Expansion BAR changes when writing the buffer */
+ nspu_xlate(desc, NSP_BASE, &offset);
+ }
+
+ NSP_REG_VAL(NSP_REG_ADDR(desc, offset, NSP_COMMAND)) =
+ (uint64_t)wsize << 32 | (uint64_t)cmd << 16 | 1;
+
+ retry = 0;
+
+ cmd_reg = NSP_REG_VAL(NSP_REG_ADDR(desc, offset, NSP_COMMAND));
+ while ((cmd_reg & 0x1) && (retry < retries)) {
+ cmd_reg = NSP_REG_VAL(NSP_REG_ADDR(desc, offset, NSP_COMMAND));
+ retry++;
+ sleep(1);
+ }
+ if (retry == retries)
+ return -1;
+
+ retry = 0;
+ status = NSP_REG_VAL(NSP_REG_ADDR(desc, offset, NSP_STATUS));
+ while ((status & 0x1) && (retry < retries)) {
+ status = NSP_REG_VAL(NSP_REG_ADDR(desc, offset, NSP_STATUS));
+ retry++;
+ sleep(1);
+ }
+
+ if (retry == retries)
+ return -1;
+
+ ret = status & (0xff << 8);
+ if (ret)
+ return ret;
+
+ if (read) {
+ ret = nspu_buff_read(desc, buffer, rsize);
+ if (ret)
+ return ret;
+ }
+
+ return ret;
+}
+
+static int
+nfp_fw_reset(nspu_desc_t *nspu_desc)
+{
+ int res;
+
+ res = nspu_command(nspu_desc, NSP_CMD_RESET, 0, 0, 0, 0, 0);
+
+ if (res < 0)
+ RTE_LOG(INFO, PMD, "fw reset failed: error %d", res);
+
+ return res;
+}
+
+#define DEFAULT_FW_PATH "/lib/firmware/netronome"
+#define DEFAULT_FW_FILENAME "nic_dpdk_default.nffw"
+
+static int
+nfp_fw_upload(nspu_desc_t *nspu_desc)
+{
+ int fw_f;
+ char *fw_buf;
+ char filename[100];
+ struct stat file_stat;
+ off_t fsize, bytes;
+ ssize_t size;
+ int ret;
+
+ size = nspu_desc->buf_size;
+
+ sprintf(filename, "%s/%s", DEFAULT_FW_PATH, DEFAULT_FW_FILENAME);
+ fw_f = open(filename, O_RDONLY);
+ if (fw_f < 0) {
+ RTE_LOG(INFO, PMD, "Firmware file %s/%s not found.",
+ DEFAULT_FW_PATH, DEFAULT_FW_FILENAME);
+ return -ENOENT;
+ }
+
+ fstat(fw_f, &file_stat);
+
+ fsize = file_stat.st_size;
+ RTE_LOG(DEBUG, PMD, "Firmware file with size: %" PRIu64 "\n",
+ (uint64_t)fsize);
+
+ if (fsize > (off_t)size) {
+ RTE_LOG(INFO, PMD, "fw file too big: %" PRIu64
+ " bytes (%" PRIu64 " max)",
+ (uint64_t)fsize, (uint64_t)size);
+ return -EINVAL;
+ }
+
+ fw_buf = malloc((size_t)size);
+ if (!fw_buf) {
+ RTE_LOG(INFO, PMD, "malloc failed for fw buffer");
+ return -ENOMEM;
+ }
+ memset(fw_buf, 0, size);
+
+ bytes = read(fw_f, fw_buf, fsize);
+ if (bytes != fsize) {
+ RTE_LOG(INFO, PMD, "Reading fw to buffer failed.\n"
+ "Just %" PRIu64 " of %" PRIu64 " bytes read.",
+ (uint64_t)bytes, (uint64_t)fsize);
+ free(fw_buf);
+ return -EIO;
+ }
+
+ ret = nspu_command(nspu_desc, NSP_CMD_FW_LOAD, 0, 1, fw_buf, 0, bytes);
+
+ free(fw_buf);
+
+ return ret;
+}
+
+/* Firmware symbol descriptor size */
+#define NFP_SYM_DESC_LEN 40
+
+#define SYMBOL_DATA(b, off) (*(int64_t *)((b) + (off)))
+#define SYMBOL_UDATA(b, off) (*(uint64_t *)((b) + (off)))
+
+/* Firmware symbols contain information about how to access what they
+ * represent. It can be as simple as an numeric variable declared at a
+ * specific NFP memory, but it can also be more complex structures and
+ * related to specific hardware functionalities or components. Target,
+ * domain and address allow to create the BAR window for accessing such
+ * hw object and size defines the length to map.
+ *
+ * A vNIC is a network interface implemented inside the NFP and using a
+ * subset of device PCI BARs. Specific firmware symbols allow to map those
+ * vNIC bars by host drivers like the NFP PMD.
+ *
+ * Accessing what the symbol represents implies to map the access through
+ * a PCI BAR window. NFP expansion BARs are used in this regard through
+ * the NSPU interface.
+ */
+static int
+nfp_nspu_set_bar_from_symbl(nspu_desc_t *desc, const char *symbl,
+ uint32_t expbar, uint64_t *pcie_offset,
+ ssize_t *size)
+{
+ int64_t type;
+ int64_t target;
+ int64_t domain;
+ uint64_t addr;
+ char *sym_buf;
+ int ret = 0;
+
+ sym_buf = malloc(desc->buf_size);
+ strncpy(sym_buf, symbl, strlen(symbl));
+ ret = nspu_command(desc, NSP_CMD_GET_SYMBOL, 1, 1, sym_buf,
+ NFP_SYM_DESC_LEN, strlen(symbl));
+ if (ret) {
+ RTE_LOG(DEBUG, PMD, "symbol resolution (%s) failed\n", symbl);
+ goto clean;
+ }
+
+ /* Reading symbol information */
+ type = SYMBOL_DATA(sym_buf, 0);
+ target = SYMBOL_DATA(sym_buf, 8);
+ domain = SYMBOL_DATA(sym_buf, 16);
+ addr = SYMBOL_UDATA(sym_buf, 24);
+ *size = (ssize_t)SYMBOL_UDATA(sym_buf, 32);
+
+ if (type != 1) {
+ RTE_LOG(INFO, PMD, "wrong symbol type\n");
+ ret = -EINVAL;
+ goto clean;
+ }
+ if (!(target == 7 || target == -7)) {
+ RTE_LOG(INFO, PMD, "wrong symbol target\n");
+ ret = -EINVAL;
+ goto clean;
+ }
+ if (domain == 8 || domain == 9) {
+ RTE_LOG(INFO, PMD, "wrong symbol domain\n");
+ ret = -EINVAL;
+ goto clean;
+ }
+
+ /* Adjusting address based on symbol location */
+ if ((domain >= 24) && (domain < 28) && (target == 7)) {
+ addr = 1ULL << 37 | addr | ((uint64_t)domain & 0x3) << 35;
+ } else {
+ addr = 1ULL << 39 | addr | ((uint64_t)domain & 0x3f) << 32;
+ if (target == -7)
+ target = 7;
+ }
+
+ /* Configuring NFP expansion bar for mapping specific PCI BAR window */
+ nfp_nspu_mem_bar_cfg(desc, expbar, target, addr, pcie_offset);
+
+ /* This is the PCI BAR offset to use by the host */
+ *pcie_offset |= ((expbar & 0x7) << (desc->barsz - 3));
+
+clean:
+ free(sym_buf);
+ return ret;
+}
+
+int
+nfp_nsp_fw_setup(nspu_desc_t *desc, const char *sym, uint64_t *pcie_offset)
+{
+ ssize_t bar0_sym_size;
+
+ /* If the symbol resolution works, it implies a firmware app
+ * is already there.
+ */
+ if (!nfp_nspu_set_bar_from_symbl(desc, sym, NFP_NET_PF_CFG_EXP_BAR,
+ pcie_offset, &bar0_sym_size))
+ return 0;
+
+ /* No firmware app detected or not the right one */
+ RTE_LOG(INFO, PMD, "No firmware detected. Resetting NFP...\n");
+ if (nfp_fw_reset(desc) < 0) {
+ RTE_LOG(ERR, PMD, "nfp fw reset failed\n");
+ return -ENODEV;
+ }
+
+ RTE_LOG(INFO, PMD, "Reset done.\n");
+ RTE_LOG(INFO, PMD, "Uploading firmware...\n");
+
+ if (nfp_fw_upload(desc) < 0) {
+ RTE_LOG(ERR, PMD, "nfp fw upload failed\n");
+ return -ENODEV;
+ }
+
+ RTE_LOG(INFO, PMD, "Done.\n");
+
+ /* Now the symbol should be there */
+ if (nfp_nspu_set_bar_from_symbl(desc, sym, NFP_NET_PF_CFG_EXP_BAR,
+ pcie_offset, &bar0_sym_size)) {
+ RTE_LOG(ERR, PMD, "nfp PF BAR symbol resolution failed\n");
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
+int
+nfp_nsp_map_ctrl_bar(nspu_desc_t *desc, uint64_t *pcie_offset)
+{
+ ssize_t bar0_sym_size;
+
+ if (nfp_nspu_set_bar_from_symbl(desc, "_pf0_net_bar0",
+ NFP_NET_PF_CFG_EXP_BAR,
+ pcie_offset, &bar0_sym_size))
+ return -ENODEV;
+
+ return 0;
+}
+
+/*
+ * This is a hardcoded fixed NFP internal CPP bus address for the hw queues unit
+ * inside the PCIE island.
+ */
+#define NFP_CPP_PCIE_QUEUES ((uint64_t)(1ULL << 39) | 0x80000 | \
+ ((uint64_t)0x4 & 0x3f) << 32)
+
+/* Configure a specific NFP expansion bar for accessing the vNIC rx/tx BARs */
+void
+nfp_nsp_map_queues_bar(nspu_desc_t *desc, uint64_t *pcie_offset)
+{
+ nfp_nspu_mem_bar_cfg(desc, NFP_NET_PF_HW_QUEUES_EXP_BAR, 0,
+ NFP_CPP_PCIE_QUEUES, pcie_offset);
+
+ /* This is the pcie offset to use by the host */
+ *pcie_offset |= ((NFP_NET_PF_HW_QUEUES_EXP_BAR & 0x7) << (27 - 3));
+}
+
+int
+nfp_nsp_eth_config(nspu_desc_t *desc, int port, int up)
+{
+ union eth_table_entry *entries, *entry;
+ int modified;
+ int ret, idx;
+ int i;
+
+ idx = port;
+
+ RTE_LOG(INFO, PMD, "Hw ethernet port %d configure...\n", port);
+ rte_spinlock_lock(&desc->nsp_lock);
+ entries = malloc(NSP_ETH_TABLE_SIZE);
+ if (!entries) {
+ rte_spinlock_unlock(&desc->nsp_lock);
+ return -ENOMEM;
+ }
+
+ ret = nspu_command(desc, NSP_CMD_READ_ETH_TABLE, 1, 0, entries,
+ NSP_ETH_TABLE_SIZE, 0);
+ if (ret) {
+ rte_spinlock_unlock(&desc->nsp_lock);
+ return ret;
+ }
+
+ entry = entries;
+
+ for (i = 0; i < NSP_ETH_MAX_COUNT; i++) {
+ /* ports in use do not appear sequentially in the table */
+ if (!(entry->port & NSP_ETH_PORT_LANES_MASK)) {
+ /* entry not in use */
+ entry++;
+ continue;
+ }
+ if (idx == 0)
+ break;
+ idx--;
+ entry++;
+ }
+
+ if (i == NSP_ETH_MAX_COUNT) {
+ rte_spinlock_unlock(&desc->nsp_lock);
+ return -EINVAL;
+ }
+
+ if (up && !(entry->state & NSP_ETH_STATE_CONFIGURED)) {
+ entry->control |= NSP_ETH_STATE_CONFIGURED;
+ modified = 1;
+ }
+
+ if (!up && (entry->state & NSP_ETH_STATE_CONFIGURED)) {
+ entry->control &= ~NSP_ETH_STATE_CONFIGURED;
+ modified = 1;
+ }
+
+ if (modified) {
+ ret = nspu_command(desc, NSP_CMD_WRITE_ETH_TABLE, 0, 1, entries,
+ 0, NSP_ETH_TABLE_SIZE);
+ if (!ret)
+ RTE_LOG(INFO, PMD,
+ "Hw ethernet port %d configure done\n", port);
+ else
+ RTE_LOG(INFO, PMD,
+ "Hw ethernet port %d configure failed\n", port);
+ }
+ rte_spinlock_unlock(&desc->nsp_lock);
+ return ret;
+}
+
+int
+nfp_nsp_eth_read_table(nspu_desc_t *desc, union eth_table_entry **table)
+{
+ int ret;
+
+ RTE_LOG(INFO, PMD, "Reading hw ethernet table...\n");
+ /* port 0 allocates the eth table and read it using NSPU */
+ *table = malloc(NSP_ETH_TABLE_SIZE);
+ if (!table)
+ return -ENOMEM;
+
+ ret = nspu_command(desc, NSP_CMD_READ_ETH_TABLE, 1, 0, *table,
+ NSP_ETH_TABLE_SIZE, 0);
+ if (ret)
+ return ret;
+
+ RTE_LOG(INFO, PMD, "Done\n");
+
+ return 0;
+}
diff --git a/drivers/net/nfp/nfp_nspu.h b/drivers/net/nfp/nfp_nspu.h
new file mode 100644
index 00000000..8c33835e
--- /dev/null
+++ b/drivers/net/nfp/nfp_nspu.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2017 Netronome Systems, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * vim:shiftwidth=8:noexpandtab
+ *
+ * @file dpdk/pmd/nfp_nspu.h
+ *
+ * Netronome NFP_NET PDM driver
+ */
+
+/*
+ * NSP is the NFP Service Processor. NSPU is NSP Userspace interface.
+ *
+ * NFP NSP helps with firmware/hardware configuration. NSP is another component
+ * in NFP programmable processor and accessing it from host requires to firstly
+ * configure a specific NFP PCI expansion BAR.
+ *
+ * Once access is ready, configuration can be done reading and writing
+ * from/to a specific PF PCI BAR window. This same interface will allow to
+ * create other PCI BAR windows for accessing other NFP components.
+ *
+ * This file includes low-level functions, using the NSPU interface, and high
+ * level functions, invoked by the PMD for using NSP services. This allows
+ * firmware upload, vNIC PCI BARs mapping and other low-level configurations
+ * like link setup.
+ *
+ * NSP access is done during initialization and it is not involved at all with
+ * the fast path.
+ */
+
+#include <rte_spinlock.h>
+#include "nfp_net_eth.h"
+
+typedef struct {
+ int nfp; /* NFP device */
+ int pcie_bar; /* PF PCI BAR to work with */
+ int exp_bar; /* Expansion BAR number used by NSPU */
+ int barsz; /* PCIE BAR log2 size */
+ uint64_t bufaddr; /* commands buffer address */
+ size_t buf_size; /* commands buffer size */
+ uint64_t windowsz; /* NSPU BAR window size */
+ void *cfg_base; /* Expansion BARs address */
+ void *mem_base; /* NSP interface */
+ rte_spinlock_t nsp_lock;
+} nspu_desc_t;
+
+int nfp_nspu_init(nspu_desc_t *desc, int nfp, int pcie_bar, size_t pcie_barsz,
+ int exp_bar, void *exp_bar_cfg_base, void *exp_bar_mmap);
+int nfp_nsp_get_abi_version(nspu_desc_t *desc, int *major, int *minor);
+int nfp_nsp_fw_setup(nspu_desc_t *desc, const char *sym, uint64_t *pcie_offset);
+int nfp_nsp_map_ctrl_bar(nspu_desc_t *desc, uint64_t *pcie_offset);
+void nfp_nsp_map_queues_bar(nspu_desc_t *desc, uint64_t *pcie_offset);
+int nfp_nsp_eth_config(nspu_desc_t *desc, int port, int up);
+int nfp_nsp_eth_read_table(nspu_desc_t *desc, union eth_table_entry **table);